1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "cpu.h" 31 #ifdef CONFIG_TCG 32 #include "hw/core/tcg-cpu-ops.h" 33 #endif /* CONFIG_TCG */ 34 #include "internals.h" 35 #include "exec/exec-all.h" 36 #include "hw/qdev-properties.h" 37 #if !defined(CONFIG_USER_ONLY) 38 #include "hw/loader.h" 39 #include "hw/boards.h" 40 #endif 41 #include "sysemu/tcg.h" 42 #include "sysemu/qtest.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_arm.h" 45 #include "disas/capstone.h" 46 #include "fpu/softfloat.h" 47 #include "cpregs.h" 48 49 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 50 { 51 ARMCPU *cpu = ARM_CPU(cs); 52 CPUARMState *env = &cpu->env; 53 54 if (is_a64(env)) { 55 env->pc = value; 56 env->thumb = false; 57 } else { 58 env->regs[15] = value & ~1; 59 env->thumb = value & 1; 60 } 61 } 62 63 static vaddr arm_cpu_get_pc(CPUState *cs) 64 { 65 ARMCPU *cpu = ARM_CPU(cs); 66 CPUARMState *env = &cpu->env; 67 68 if (is_a64(env)) { 69 return env->pc; 70 } else { 71 return env->regs[15]; 72 } 73 } 74 75 #ifdef CONFIG_TCG 76 void arm_cpu_synchronize_from_tb(CPUState *cs, 77 const TranslationBlock *tb) 78 { 79 /* The program counter is always up to date with TARGET_TB_PCREL. */ 80 if (!TARGET_TB_PCREL) { 81 CPUARMState *env = cs->env_ptr; 82 /* 83 * It's OK to look at env for the current mode here, because it's 84 * never possible for an AArch64 TB to chain to an AArch32 TB. 85 */ 86 if (is_a64(env)) { 87 env->pc = tb_pc(tb); 88 } else { 89 env->regs[15] = tb_pc(tb); 90 } 91 } 92 } 93 94 void arm_restore_state_to_opc(CPUState *cs, 95 const TranslationBlock *tb, 96 const uint64_t *data) 97 { 98 CPUARMState *env = cs->env_ptr; 99 100 if (is_a64(env)) { 101 if (TARGET_TB_PCREL) { 102 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 103 } else { 104 env->pc = data[0]; 105 } 106 env->condexec_bits = 0; 107 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 108 } else { 109 if (TARGET_TB_PCREL) { 110 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 111 } else { 112 env->regs[15] = data[0]; 113 } 114 env->condexec_bits = data[1]; 115 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 116 } 117 } 118 #endif /* CONFIG_TCG */ 119 120 static bool arm_cpu_has_work(CPUState *cs) 121 { 122 ARMCPU *cpu = ARM_CPU(cs); 123 124 return (cpu->power_state != PSCI_OFF) 125 && cs->interrupt_request & 126 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 127 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 128 | CPU_INTERRUPT_EXITTB); 129 } 130 131 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 132 void *opaque) 133 { 134 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 135 136 entry->hook = hook; 137 entry->opaque = opaque; 138 139 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 140 } 141 142 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 143 void *opaque) 144 { 145 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 146 147 entry->hook = hook; 148 entry->opaque = opaque; 149 150 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 151 } 152 153 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 154 { 155 /* Reset a single ARMCPRegInfo register */ 156 ARMCPRegInfo *ri = value; 157 ARMCPU *cpu = opaque; 158 159 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 160 return; 161 } 162 163 if (ri->resetfn) { 164 ri->resetfn(&cpu->env, ri); 165 return; 166 } 167 168 /* A zero offset is never possible as it would be regs[0] 169 * so we use it to indicate that reset is being handled elsewhere. 170 * This is basically only used for fields in non-core coprocessors 171 * (like the pxa2xx ones). 172 */ 173 if (!ri->fieldoffset) { 174 return; 175 } 176 177 if (cpreg_field_is_64bit(ri)) { 178 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 179 } else { 180 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 181 } 182 } 183 184 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 185 { 186 /* Purely an assertion check: we've already done reset once, 187 * so now check that running the reset for the cpreg doesn't 188 * change its value. This traps bugs where two different cpregs 189 * both try to reset the same state field but to different values. 190 */ 191 ARMCPRegInfo *ri = value; 192 ARMCPU *cpu = opaque; 193 uint64_t oldvalue, newvalue; 194 195 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 196 return; 197 } 198 199 oldvalue = read_raw_cp_reg(&cpu->env, ri); 200 cp_reg_reset(key, value, opaque); 201 newvalue = read_raw_cp_reg(&cpu->env, ri); 202 assert(oldvalue == newvalue); 203 } 204 205 static void arm_cpu_reset_hold(Object *obj) 206 { 207 CPUState *s = CPU(obj); 208 ARMCPU *cpu = ARM_CPU(s); 209 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 210 CPUARMState *env = &cpu->env; 211 212 if (acc->parent_phases.hold) { 213 acc->parent_phases.hold(obj); 214 } 215 216 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 217 218 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 219 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 220 221 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 222 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 223 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 224 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 225 226 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 227 228 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 229 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 230 } 231 232 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 233 /* 64 bit CPUs always start in 64 bit mode */ 234 env->aarch64 = true; 235 #if defined(CONFIG_USER_ONLY) 236 env->pstate = PSTATE_MODE_EL0t; 237 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 238 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 239 /* Enable all PAC keys. */ 240 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 241 SCTLR_EnDA | SCTLR_EnDB); 242 /* Trap on btype=3 for PACIxSP. */ 243 env->cp15.sctlr_el[1] |= SCTLR_BT0; 244 /* and to the FP/Neon instructions */ 245 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 246 CPACR_EL1, FPEN, 3); 247 /* and to the SVE instructions, with default vector length */ 248 if (cpu_isar_feature(aa64_sve, cpu)) { 249 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 250 CPACR_EL1, ZEN, 3); 251 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 252 } 253 /* and for SME instructions, with default vector length, and TPIDR2 */ 254 if (cpu_isar_feature(aa64_sme, cpu)) { 255 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 256 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 257 CPACR_EL1, SMEN, 3); 258 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 259 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 260 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 261 SMCR, FA64, 1); 262 } 263 } 264 /* 265 * Enable 48-bit address space (TODO: take reserved_va into account). 266 * Enable TBI0 but not TBI1. 267 * Note that this must match useronly_clean_ptr. 268 */ 269 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 270 271 /* Enable MTE */ 272 if (cpu_isar_feature(aa64_mte, cpu)) { 273 /* Enable tag access, but leave TCF0 as No Effect (0). */ 274 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 275 /* 276 * Exclude all tags, so that tag 0 is always used. 277 * This corresponds to Linux current->thread.gcr_incl = 0. 278 * 279 * Set RRND, so that helper_irg() will generate a seed later. 280 * Here in cpu_reset(), the crypto subsystem has not yet been 281 * initialized. 282 */ 283 env->cp15.gcr_el1 = 0x1ffff; 284 } 285 /* 286 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 287 * This is not yet exposed from the Linux kernel in any way. 288 */ 289 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 290 #else 291 /* Reset into the highest available EL */ 292 if (arm_feature(env, ARM_FEATURE_EL3)) { 293 env->pstate = PSTATE_MODE_EL3h; 294 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 295 env->pstate = PSTATE_MODE_EL2h; 296 } else { 297 env->pstate = PSTATE_MODE_EL1h; 298 } 299 300 /* Sample rvbar at reset. */ 301 env->cp15.rvbar = cpu->rvbar_prop; 302 env->pc = env->cp15.rvbar; 303 #endif 304 } else { 305 #if defined(CONFIG_USER_ONLY) 306 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 307 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 308 CPACR, CP10, 3); 309 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 310 CPACR, CP11, 3); 311 #endif 312 if (arm_feature(env, ARM_FEATURE_V8)) { 313 env->cp15.rvbar = cpu->rvbar_prop; 314 env->regs[15] = cpu->rvbar_prop; 315 } 316 } 317 318 #if defined(CONFIG_USER_ONLY) 319 env->uncached_cpsr = ARM_CPU_MODE_USR; 320 /* For user mode we must enable access to coprocessors */ 321 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 322 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 323 env->cp15.c15_cpar = 3; 324 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 325 env->cp15.c15_cpar = 1; 326 } 327 #else 328 329 /* 330 * If the highest available EL is EL2, AArch32 will start in Hyp 331 * mode; otherwise it starts in SVC. Note that if we start in 332 * AArch64 then these values in the uncached_cpsr will be ignored. 333 */ 334 if (arm_feature(env, ARM_FEATURE_EL2) && 335 !arm_feature(env, ARM_FEATURE_EL3)) { 336 env->uncached_cpsr = ARM_CPU_MODE_HYP; 337 } else { 338 env->uncached_cpsr = ARM_CPU_MODE_SVC; 339 } 340 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 341 342 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 343 * executing as AArch32 then check if highvecs are enabled and 344 * adjust the PC accordingly. 345 */ 346 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 347 env->regs[15] = 0xFFFF0000; 348 } 349 350 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 351 #endif 352 353 if (arm_feature(env, ARM_FEATURE_M)) { 354 #ifndef CONFIG_USER_ONLY 355 uint32_t initial_msp; /* Loaded from 0x0 */ 356 uint32_t initial_pc; /* Loaded from 0x4 */ 357 uint8_t *rom; 358 uint32_t vecbase; 359 #endif 360 361 if (cpu_isar_feature(aa32_lob, cpu)) { 362 /* 363 * LTPSIZE is constant 4 if MVE not implemented, and resets 364 * to an UNKNOWN value if MVE is implemented. We choose to 365 * always reset to 4. 366 */ 367 env->v7m.ltpsize = 4; 368 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 369 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 370 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 371 } 372 373 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 374 env->v7m.secure = true; 375 } else { 376 /* This bit resets to 0 if security is supported, but 1 if 377 * it is not. The bit is not present in v7M, but we set it 378 * here so we can avoid having to make checks on it conditional 379 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 380 */ 381 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 382 /* 383 * Set NSACR to indicate "NS access permitted to everything"; 384 * this avoids having to have all the tests of it being 385 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 386 * v8.1M the guest-visible value of NSACR in a CPU without the 387 * Security Extension is 0xcff. 388 */ 389 env->v7m.nsacr = 0xcff; 390 } 391 392 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 393 * that it resets to 1, so QEMU always does that rather than making 394 * it dependent on CPU model. In v8M it is RES1. 395 */ 396 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 397 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 398 if (arm_feature(env, ARM_FEATURE_V8)) { 399 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 400 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 401 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 402 } 403 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 404 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 405 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 406 } 407 408 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 409 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 410 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 411 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 412 } 413 414 #ifndef CONFIG_USER_ONLY 415 /* Unlike A/R profile, M profile defines the reset LR value */ 416 env->regs[14] = 0xffffffff; 417 418 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 419 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 420 421 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 422 vecbase = env->v7m.vecbase[env->v7m.secure]; 423 rom = rom_ptr_for_as(s->as, vecbase, 8); 424 if (rom) { 425 /* Address zero is covered by ROM which hasn't yet been 426 * copied into physical memory. 427 */ 428 initial_msp = ldl_p(rom); 429 initial_pc = ldl_p(rom + 4); 430 } else { 431 /* Address zero not covered by a ROM blob, or the ROM blob 432 * is in non-modifiable memory and this is a second reset after 433 * it got copied into memory. In the latter case, rom_ptr 434 * will return a NULL pointer and we should use ldl_phys instead. 435 */ 436 initial_msp = ldl_phys(s->as, vecbase); 437 initial_pc = ldl_phys(s->as, vecbase + 4); 438 } 439 440 qemu_log_mask(CPU_LOG_INT, 441 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 442 initial_msp, initial_pc); 443 444 env->regs[13] = initial_msp & 0xFFFFFFFC; 445 env->regs[15] = initial_pc & ~1; 446 env->thumb = initial_pc & 1; 447 #else 448 /* 449 * For user mode we run non-secure and with access to the FPU. 450 * The FPU context is active (ie does not need further setup) 451 * and is owned by non-secure. 452 */ 453 env->v7m.secure = false; 454 env->v7m.nsacr = 0xcff; 455 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 456 env->v7m.fpccr[M_REG_S] &= 457 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 458 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 459 #endif 460 } 461 462 /* M profile requires that reset clears the exclusive monitor; 463 * A profile does not, but clearing it makes more sense than having it 464 * set with an exclusive access on address zero. 465 */ 466 arm_clear_exclusive(env); 467 468 if (arm_feature(env, ARM_FEATURE_PMSA)) { 469 if (cpu->pmsav7_dregion > 0) { 470 if (arm_feature(env, ARM_FEATURE_V8)) { 471 memset(env->pmsav8.rbar[M_REG_NS], 0, 472 sizeof(*env->pmsav8.rbar[M_REG_NS]) 473 * cpu->pmsav7_dregion); 474 memset(env->pmsav8.rlar[M_REG_NS], 0, 475 sizeof(*env->pmsav8.rlar[M_REG_NS]) 476 * cpu->pmsav7_dregion); 477 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 478 memset(env->pmsav8.rbar[M_REG_S], 0, 479 sizeof(*env->pmsav8.rbar[M_REG_S]) 480 * cpu->pmsav7_dregion); 481 memset(env->pmsav8.rlar[M_REG_S], 0, 482 sizeof(*env->pmsav8.rlar[M_REG_S]) 483 * cpu->pmsav7_dregion); 484 } 485 } else if (arm_feature(env, ARM_FEATURE_V7)) { 486 memset(env->pmsav7.drbar, 0, 487 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 488 memset(env->pmsav7.drsr, 0, 489 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 490 memset(env->pmsav7.dracr, 0, 491 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 492 } 493 } 494 env->pmsav7.rnr[M_REG_NS] = 0; 495 env->pmsav7.rnr[M_REG_S] = 0; 496 env->pmsav8.mair0[M_REG_NS] = 0; 497 env->pmsav8.mair0[M_REG_S] = 0; 498 env->pmsav8.mair1[M_REG_NS] = 0; 499 env->pmsav8.mair1[M_REG_S] = 0; 500 } 501 502 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 503 if (cpu->sau_sregion > 0) { 504 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 505 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 506 } 507 env->sau.rnr = 0; 508 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 509 * the Cortex-M33 does. 510 */ 511 env->sau.ctrl = 0; 512 } 513 514 set_flush_to_zero(1, &env->vfp.standard_fp_status); 515 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 516 set_default_nan_mode(1, &env->vfp.standard_fp_status); 517 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 518 set_float_detect_tininess(float_tininess_before_rounding, 519 &env->vfp.fp_status); 520 set_float_detect_tininess(float_tininess_before_rounding, 521 &env->vfp.standard_fp_status); 522 set_float_detect_tininess(float_tininess_before_rounding, 523 &env->vfp.fp_status_f16); 524 set_float_detect_tininess(float_tininess_before_rounding, 525 &env->vfp.standard_fp_status_f16); 526 #ifndef CONFIG_USER_ONLY 527 if (kvm_enabled()) { 528 kvm_arm_reset_vcpu(cpu); 529 } 530 #endif 531 532 hw_breakpoint_update_all(cpu); 533 hw_watchpoint_update_all(cpu); 534 arm_rebuild_hflags(env); 535 } 536 537 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 538 539 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 540 unsigned int target_el, 541 unsigned int cur_el, bool secure, 542 uint64_t hcr_el2) 543 { 544 CPUARMState *env = cs->env_ptr; 545 bool pstate_unmasked; 546 bool unmasked = false; 547 548 /* 549 * Don't take exceptions if they target a lower EL. 550 * This check should catch any exceptions that would not be taken 551 * but left pending. 552 */ 553 if (cur_el > target_el) { 554 return false; 555 } 556 557 switch (excp_idx) { 558 case EXCP_FIQ: 559 pstate_unmasked = !(env->daif & PSTATE_F); 560 break; 561 562 case EXCP_IRQ: 563 pstate_unmasked = !(env->daif & PSTATE_I); 564 break; 565 566 case EXCP_VFIQ: 567 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 568 /* VFIQs are only taken when hypervized. */ 569 return false; 570 } 571 return !(env->daif & PSTATE_F); 572 case EXCP_VIRQ: 573 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 574 /* VIRQs are only taken when hypervized. */ 575 return false; 576 } 577 return !(env->daif & PSTATE_I); 578 case EXCP_VSERR: 579 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 580 /* VIRQs are only taken when hypervized. */ 581 return false; 582 } 583 return !(env->daif & PSTATE_A); 584 default: 585 g_assert_not_reached(); 586 } 587 588 /* 589 * Use the target EL, current execution state and SCR/HCR settings to 590 * determine whether the corresponding CPSR bit is used to mask the 591 * interrupt. 592 */ 593 if ((target_el > cur_el) && (target_el != 1)) { 594 /* Exceptions targeting a higher EL may not be maskable */ 595 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 596 switch (target_el) { 597 case 2: 598 /* 599 * According to ARM DDI 0487H.a, an interrupt can be masked 600 * when HCR_E2H and HCR_TGE are both set regardless of the 601 * current Security state. Note that we need to revisit this 602 * part again once we need to support NMI. 603 */ 604 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 605 unmasked = true; 606 } 607 break; 608 case 3: 609 /* Interrupt cannot be masked when the target EL is 3 */ 610 unmasked = true; 611 break; 612 default: 613 g_assert_not_reached(); 614 } 615 } else { 616 /* 617 * The old 32-bit-only environment has a more complicated 618 * masking setup. HCR and SCR bits not only affect interrupt 619 * routing but also change the behaviour of masking. 620 */ 621 bool hcr, scr; 622 623 switch (excp_idx) { 624 case EXCP_FIQ: 625 /* 626 * If FIQs are routed to EL3 or EL2 then there are cases where 627 * we override the CPSR.F in determining if the exception is 628 * masked or not. If neither of these are set then we fall back 629 * to the CPSR.F setting otherwise we further assess the state 630 * below. 631 */ 632 hcr = hcr_el2 & HCR_FMO; 633 scr = (env->cp15.scr_el3 & SCR_FIQ); 634 635 /* 636 * When EL3 is 32-bit, the SCR.FW bit controls whether the 637 * CPSR.F bit masks FIQ interrupts when taken in non-secure 638 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 639 * when non-secure but only when FIQs are only routed to EL3. 640 */ 641 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 642 break; 643 case EXCP_IRQ: 644 /* 645 * When EL3 execution state is 32-bit, if HCR.IMO is set then 646 * we may override the CPSR.I masking when in non-secure state. 647 * The SCR.IRQ setting has already been taken into consideration 648 * when setting the target EL, so it does not have a further 649 * affect here. 650 */ 651 hcr = hcr_el2 & HCR_IMO; 652 scr = false; 653 break; 654 default: 655 g_assert_not_reached(); 656 } 657 658 if ((scr || hcr) && !secure) { 659 unmasked = true; 660 } 661 } 662 } 663 664 /* 665 * The PSTATE bits only mask the interrupt if we have not overriden the 666 * ability above. 667 */ 668 return unmasked || pstate_unmasked; 669 } 670 671 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 672 { 673 CPUClass *cc = CPU_GET_CLASS(cs); 674 CPUARMState *env = cs->env_ptr; 675 uint32_t cur_el = arm_current_el(env); 676 bool secure = arm_is_secure(env); 677 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 678 uint32_t target_el; 679 uint32_t excp_idx; 680 681 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 682 683 if (interrupt_request & CPU_INTERRUPT_FIQ) { 684 excp_idx = EXCP_FIQ; 685 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 686 if (arm_excp_unmasked(cs, excp_idx, target_el, 687 cur_el, secure, hcr_el2)) { 688 goto found; 689 } 690 } 691 if (interrupt_request & CPU_INTERRUPT_HARD) { 692 excp_idx = EXCP_IRQ; 693 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 694 if (arm_excp_unmasked(cs, excp_idx, target_el, 695 cur_el, secure, hcr_el2)) { 696 goto found; 697 } 698 } 699 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 700 excp_idx = EXCP_VIRQ; 701 target_el = 1; 702 if (arm_excp_unmasked(cs, excp_idx, target_el, 703 cur_el, secure, hcr_el2)) { 704 goto found; 705 } 706 } 707 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 708 excp_idx = EXCP_VFIQ; 709 target_el = 1; 710 if (arm_excp_unmasked(cs, excp_idx, target_el, 711 cur_el, secure, hcr_el2)) { 712 goto found; 713 } 714 } 715 if (interrupt_request & CPU_INTERRUPT_VSERR) { 716 excp_idx = EXCP_VSERR; 717 target_el = 1; 718 if (arm_excp_unmasked(cs, excp_idx, target_el, 719 cur_el, secure, hcr_el2)) { 720 /* Taking a virtual abort clears HCR_EL2.VSE */ 721 env->cp15.hcr_el2 &= ~HCR_VSE; 722 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 723 goto found; 724 } 725 } 726 return false; 727 728 found: 729 cs->exception_index = excp_idx; 730 env->exception.target_el = target_el; 731 cc->tcg_ops->do_interrupt(cs); 732 return true; 733 } 734 735 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 736 737 void arm_cpu_update_virq(ARMCPU *cpu) 738 { 739 /* 740 * Update the interrupt level for VIRQ, which is the logical OR of 741 * the HCR_EL2.VI bit and the input line level from the GIC. 742 */ 743 CPUARMState *env = &cpu->env; 744 CPUState *cs = CPU(cpu); 745 746 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 747 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 748 749 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 750 if (new_state) { 751 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 752 } else { 753 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 754 } 755 } 756 } 757 758 void arm_cpu_update_vfiq(ARMCPU *cpu) 759 { 760 /* 761 * Update the interrupt level for VFIQ, which is the logical OR of 762 * the HCR_EL2.VF bit and the input line level from the GIC. 763 */ 764 CPUARMState *env = &cpu->env; 765 CPUState *cs = CPU(cpu); 766 767 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 768 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 769 770 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 771 if (new_state) { 772 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 773 } else { 774 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 775 } 776 } 777 } 778 779 void arm_cpu_update_vserr(ARMCPU *cpu) 780 { 781 /* 782 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 783 */ 784 CPUARMState *env = &cpu->env; 785 CPUState *cs = CPU(cpu); 786 787 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 788 789 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 790 if (new_state) { 791 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 792 } else { 793 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 794 } 795 } 796 } 797 798 #ifndef CONFIG_USER_ONLY 799 static void arm_cpu_set_irq(void *opaque, int irq, int level) 800 { 801 ARMCPU *cpu = opaque; 802 CPUARMState *env = &cpu->env; 803 CPUState *cs = CPU(cpu); 804 static const int mask[] = { 805 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 806 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 807 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 808 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 809 }; 810 811 if (!arm_feature(env, ARM_FEATURE_EL2) && 812 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 813 /* 814 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 815 * have EL2 support we don't care. (Unless the guest is doing something 816 * silly this will only be calls saying "level is still 0".) 817 */ 818 return; 819 } 820 821 if (level) { 822 env->irq_line_state |= mask[irq]; 823 } else { 824 env->irq_line_state &= ~mask[irq]; 825 } 826 827 switch (irq) { 828 case ARM_CPU_VIRQ: 829 arm_cpu_update_virq(cpu); 830 break; 831 case ARM_CPU_VFIQ: 832 arm_cpu_update_vfiq(cpu); 833 break; 834 case ARM_CPU_IRQ: 835 case ARM_CPU_FIQ: 836 if (level) { 837 cpu_interrupt(cs, mask[irq]); 838 } else { 839 cpu_reset_interrupt(cs, mask[irq]); 840 } 841 break; 842 default: 843 g_assert_not_reached(); 844 } 845 } 846 847 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 848 { 849 #ifdef CONFIG_KVM 850 ARMCPU *cpu = opaque; 851 CPUARMState *env = &cpu->env; 852 CPUState *cs = CPU(cpu); 853 uint32_t linestate_bit; 854 int irq_id; 855 856 switch (irq) { 857 case ARM_CPU_IRQ: 858 irq_id = KVM_ARM_IRQ_CPU_IRQ; 859 linestate_bit = CPU_INTERRUPT_HARD; 860 break; 861 case ARM_CPU_FIQ: 862 irq_id = KVM_ARM_IRQ_CPU_FIQ; 863 linestate_bit = CPU_INTERRUPT_FIQ; 864 break; 865 default: 866 g_assert_not_reached(); 867 } 868 869 if (level) { 870 env->irq_line_state |= linestate_bit; 871 } else { 872 env->irq_line_state &= ~linestate_bit; 873 } 874 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 875 #endif 876 } 877 878 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 879 { 880 ARMCPU *cpu = ARM_CPU(cs); 881 CPUARMState *env = &cpu->env; 882 883 cpu_synchronize_state(cs); 884 return arm_cpu_data_is_big_endian(env); 885 } 886 887 #endif 888 889 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 890 { 891 ARMCPU *ac = ARM_CPU(cpu); 892 CPUARMState *env = &ac->env; 893 bool sctlr_b; 894 895 if (is_a64(env)) { 896 info->cap_arch = CS_ARCH_ARM64; 897 info->cap_insn_unit = 4; 898 info->cap_insn_split = 4; 899 } else { 900 int cap_mode; 901 if (env->thumb) { 902 info->cap_insn_unit = 2; 903 info->cap_insn_split = 4; 904 cap_mode = CS_MODE_THUMB; 905 } else { 906 info->cap_insn_unit = 4; 907 info->cap_insn_split = 4; 908 cap_mode = CS_MODE_ARM; 909 } 910 if (arm_feature(env, ARM_FEATURE_V8)) { 911 cap_mode |= CS_MODE_V8; 912 } 913 if (arm_feature(env, ARM_FEATURE_M)) { 914 cap_mode |= CS_MODE_MCLASS; 915 } 916 info->cap_arch = CS_ARCH_ARM; 917 info->cap_mode = cap_mode; 918 } 919 920 sctlr_b = arm_sctlr_b(env); 921 if (bswap_code(sctlr_b)) { 922 #if TARGET_BIG_ENDIAN 923 info->endian = BFD_ENDIAN_LITTLE; 924 #else 925 info->endian = BFD_ENDIAN_BIG; 926 #endif 927 } 928 info->flags &= ~INSN_ARM_BE32; 929 #ifndef CONFIG_USER_ONLY 930 if (sctlr_b) { 931 info->flags |= INSN_ARM_BE32; 932 } 933 #endif 934 } 935 936 #ifdef TARGET_AARCH64 937 938 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 939 { 940 ARMCPU *cpu = ARM_CPU(cs); 941 CPUARMState *env = &cpu->env; 942 uint32_t psr = pstate_read(env); 943 int i; 944 int el = arm_current_el(env); 945 const char *ns_status; 946 bool sve; 947 948 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 949 for (i = 0; i < 32; i++) { 950 if (i == 31) { 951 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 952 } else { 953 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 954 (i + 2) % 3 ? " " : "\n"); 955 } 956 } 957 958 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 959 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 960 } else { 961 ns_status = ""; 962 } 963 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 964 psr, 965 psr & PSTATE_N ? 'N' : '-', 966 psr & PSTATE_Z ? 'Z' : '-', 967 psr & PSTATE_C ? 'C' : '-', 968 psr & PSTATE_V ? 'V' : '-', 969 ns_status, 970 el, 971 psr & PSTATE_SP ? 'h' : 't'); 972 973 if (cpu_isar_feature(aa64_sme, cpu)) { 974 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 975 env->svcr, 976 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 977 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 978 } 979 if (cpu_isar_feature(aa64_bti, cpu)) { 980 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 981 } 982 if (!(flags & CPU_DUMP_FPU)) { 983 qemu_fprintf(f, "\n"); 984 return; 985 } 986 if (fp_exception_el(env, el) != 0) { 987 qemu_fprintf(f, " FPU disabled\n"); 988 return; 989 } 990 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 991 vfp_get_fpcr(env), vfp_get_fpsr(env)); 992 993 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 994 sve = sme_exception_el(env, el) == 0; 995 } else if (cpu_isar_feature(aa64_sve, cpu)) { 996 sve = sve_exception_el(env, el) == 0; 997 } else { 998 sve = false; 999 } 1000 1001 if (sve) { 1002 int j, zcr_len = sve_vqm1_for_el(env, el); 1003 1004 for (i = 0; i <= FFR_PRED_NUM; i++) { 1005 bool eol; 1006 if (i == FFR_PRED_NUM) { 1007 qemu_fprintf(f, "FFR="); 1008 /* It's last, so end the line. */ 1009 eol = true; 1010 } else { 1011 qemu_fprintf(f, "P%02d=", i); 1012 switch (zcr_len) { 1013 case 0: 1014 eol = i % 8 == 7; 1015 break; 1016 case 1: 1017 eol = i % 6 == 5; 1018 break; 1019 case 2: 1020 case 3: 1021 eol = i % 3 == 2; 1022 break; 1023 default: 1024 /* More than one quadword per predicate. */ 1025 eol = true; 1026 break; 1027 } 1028 } 1029 for (j = zcr_len / 4; j >= 0; j--) { 1030 int digits; 1031 if (j * 4 + 4 <= zcr_len + 1) { 1032 digits = 16; 1033 } else { 1034 digits = (zcr_len % 4 + 1) * 4; 1035 } 1036 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1037 env->vfp.pregs[i].p[j], 1038 j ? ":" : eol ? "\n" : " "); 1039 } 1040 } 1041 1042 for (i = 0; i < 32; i++) { 1043 if (zcr_len == 0) { 1044 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1045 i, env->vfp.zregs[i].d[1], 1046 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1047 } else if (zcr_len == 1) { 1048 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 1049 ":%016" PRIx64 ":%016" PRIx64 "\n", 1050 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 1051 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 1052 } else { 1053 for (j = zcr_len; j >= 0; j--) { 1054 bool odd = (zcr_len - j) % 2 != 0; 1055 if (j == zcr_len) { 1056 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 1057 } else if (!odd) { 1058 if (j > 0) { 1059 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 1060 } else { 1061 qemu_fprintf(f, " [%x]=", j); 1062 } 1063 } 1064 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1065 env->vfp.zregs[i].d[j * 2 + 1], 1066 env->vfp.zregs[i].d[j * 2], 1067 odd || j == 0 ? "\n" : ":"); 1068 } 1069 } 1070 } 1071 } else { 1072 for (i = 0; i < 32; i++) { 1073 uint64_t *q = aa64_vfp_qreg(env, i); 1074 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1075 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1076 } 1077 } 1078 } 1079 1080 #else 1081 1082 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1083 { 1084 g_assert_not_reached(); 1085 } 1086 1087 #endif 1088 1089 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1090 { 1091 ARMCPU *cpu = ARM_CPU(cs); 1092 CPUARMState *env = &cpu->env; 1093 int i; 1094 1095 if (is_a64(env)) { 1096 aarch64_cpu_dump_state(cs, f, flags); 1097 return; 1098 } 1099 1100 for (i = 0; i < 16; i++) { 1101 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1102 if ((i % 4) == 3) { 1103 qemu_fprintf(f, "\n"); 1104 } else { 1105 qemu_fprintf(f, " "); 1106 } 1107 } 1108 1109 if (arm_feature(env, ARM_FEATURE_M)) { 1110 uint32_t xpsr = xpsr_read(env); 1111 const char *mode; 1112 const char *ns_status = ""; 1113 1114 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1115 ns_status = env->v7m.secure ? "S " : "NS "; 1116 } 1117 1118 if (xpsr & XPSR_EXCP) { 1119 mode = "handler"; 1120 } else { 1121 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1122 mode = "unpriv-thread"; 1123 } else { 1124 mode = "priv-thread"; 1125 } 1126 } 1127 1128 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1129 xpsr, 1130 xpsr & XPSR_N ? 'N' : '-', 1131 xpsr & XPSR_Z ? 'Z' : '-', 1132 xpsr & XPSR_C ? 'C' : '-', 1133 xpsr & XPSR_V ? 'V' : '-', 1134 xpsr & XPSR_T ? 'T' : 'A', 1135 ns_status, 1136 mode); 1137 } else { 1138 uint32_t psr = cpsr_read(env); 1139 const char *ns_status = ""; 1140 1141 if (arm_feature(env, ARM_FEATURE_EL3) && 1142 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1143 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1144 } 1145 1146 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1147 psr, 1148 psr & CPSR_N ? 'N' : '-', 1149 psr & CPSR_Z ? 'Z' : '-', 1150 psr & CPSR_C ? 'C' : '-', 1151 psr & CPSR_V ? 'V' : '-', 1152 psr & CPSR_T ? 'T' : 'A', 1153 ns_status, 1154 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1155 } 1156 1157 if (flags & CPU_DUMP_FPU) { 1158 int numvfpregs = 0; 1159 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1160 numvfpregs = 32; 1161 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1162 numvfpregs = 16; 1163 } 1164 for (i = 0; i < numvfpregs; i++) { 1165 uint64_t v = *aa32_vfp_dreg(env, i); 1166 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1167 i * 2, (uint32_t)v, 1168 i * 2 + 1, (uint32_t)(v >> 32), 1169 i, v); 1170 } 1171 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1172 if (cpu_isar_feature(aa32_mve, cpu)) { 1173 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1174 } 1175 } 1176 } 1177 1178 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1179 { 1180 uint32_t Aff1 = idx / clustersz; 1181 uint32_t Aff0 = idx % clustersz; 1182 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1183 } 1184 1185 static void arm_cpu_initfn(Object *obj) 1186 { 1187 ARMCPU *cpu = ARM_CPU(obj); 1188 1189 cpu_set_cpustate_pointers(cpu); 1190 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1191 NULL, g_free); 1192 1193 QLIST_INIT(&cpu->pre_el_change_hooks); 1194 QLIST_INIT(&cpu->el_change_hooks); 1195 1196 #ifdef CONFIG_USER_ONLY 1197 # ifdef TARGET_AARCH64 1198 /* 1199 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1200 * These values were chosen to fit within the default signal frame. 1201 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1202 * and our corresponding cpu property. 1203 */ 1204 cpu->sve_default_vq = 4; 1205 cpu->sme_default_vq = 2; 1206 # endif 1207 #else 1208 /* Our inbound IRQ and FIQ lines */ 1209 if (kvm_enabled()) { 1210 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1211 * the same interface as non-KVM CPUs. 1212 */ 1213 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1214 } else { 1215 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1216 } 1217 1218 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1219 ARRAY_SIZE(cpu->gt_timer_outputs)); 1220 1221 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1222 "gicv3-maintenance-interrupt", 1); 1223 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1224 "pmu-interrupt", 1); 1225 #endif 1226 1227 /* DTB consumers generally don't in fact care what the 'compatible' 1228 * string is, so always provide some string and trust that a hypothetical 1229 * picky DTB consumer will also provide a helpful error message. 1230 */ 1231 cpu->dtb_compatible = "qemu,unknown"; 1232 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1233 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1234 1235 if (tcg_enabled() || hvf_enabled()) { 1236 /* TCG and HVF implement PSCI 1.1 */ 1237 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1238 } 1239 } 1240 1241 static Property arm_cpu_gt_cntfrq_property = 1242 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1243 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1244 1245 static Property arm_cpu_reset_cbar_property = 1246 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1247 1248 static Property arm_cpu_reset_hivecs_property = 1249 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1250 1251 #ifndef CONFIG_USER_ONLY 1252 static Property arm_cpu_has_el2_property = 1253 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1254 1255 static Property arm_cpu_has_el3_property = 1256 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1257 #endif 1258 1259 static Property arm_cpu_cfgend_property = 1260 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1261 1262 static Property arm_cpu_has_vfp_property = 1263 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1264 1265 static Property arm_cpu_has_neon_property = 1266 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1267 1268 static Property arm_cpu_has_dsp_property = 1269 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1270 1271 static Property arm_cpu_has_mpu_property = 1272 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1273 1274 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1275 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1276 * the right value for that particular CPU type, and we don't want 1277 * to override that with an incorrect constant value. 1278 */ 1279 static Property arm_cpu_pmsav7_dregion_property = 1280 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1281 pmsav7_dregion, 1282 qdev_prop_uint32, uint32_t); 1283 1284 static bool arm_get_pmu(Object *obj, Error **errp) 1285 { 1286 ARMCPU *cpu = ARM_CPU(obj); 1287 1288 return cpu->has_pmu; 1289 } 1290 1291 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1292 { 1293 ARMCPU *cpu = ARM_CPU(obj); 1294 1295 if (value) { 1296 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1297 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1298 return; 1299 } 1300 set_feature(&cpu->env, ARM_FEATURE_PMU); 1301 } else { 1302 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1303 } 1304 cpu->has_pmu = value; 1305 } 1306 1307 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1308 { 1309 /* 1310 * The exact approach to calculating guest ticks is: 1311 * 1312 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1313 * NANOSECONDS_PER_SECOND); 1314 * 1315 * We don't do that. Rather we intentionally use integer division 1316 * truncation below and in the caller for the conversion of host monotonic 1317 * time to guest ticks to provide the exact inverse for the semantics of 1318 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1319 * it loses precision when representing frequencies where 1320 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1321 * provide an exact inverse leads to scheduling timers with negative 1322 * periods, which in turn leads to sticky behaviour in the guest. 1323 * 1324 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1325 * cannot become zero. 1326 */ 1327 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1328 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1329 } 1330 1331 void arm_cpu_post_init(Object *obj) 1332 { 1333 ARMCPU *cpu = ARM_CPU(obj); 1334 1335 /* M profile implies PMSA. We have to do this here rather than 1336 * in realize with the other feature-implication checks because 1337 * we look at the PMSA bit to see if we should add some properties. 1338 */ 1339 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1340 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1341 } 1342 1343 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1344 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1345 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1346 } 1347 1348 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1349 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1350 } 1351 1352 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1353 object_property_add_uint64_ptr(obj, "rvbar", 1354 &cpu->rvbar_prop, 1355 OBJ_PROP_FLAG_READWRITE); 1356 } 1357 1358 #ifndef CONFIG_USER_ONLY 1359 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1360 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1361 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1362 */ 1363 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1364 1365 object_property_add_link(obj, "secure-memory", 1366 TYPE_MEMORY_REGION, 1367 (Object **)&cpu->secure_memory, 1368 qdev_prop_allow_set_link_before_realize, 1369 OBJ_PROP_LINK_STRONG); 1370 } 1371 1372 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1373 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1374 } 1375 #endif 1376 1377 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1378 cpu->has_pmu = true; 1379 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1380 } 1381 1382 /* 1383 * Allow user to turn off VFP and Neon support, but only for TCG -- 1384 * KVM does not currently allow us to lie to the guest about its 1385 * ID/feature registers, so the guest always sees what the host has. 1386 */ 1387 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1388 ? cpu_isar_feature(aa64_fp_simd, cpu) 1389 : cpu_isar_feature(aa32_vfp, cpu)) { 1390 cpu->has_vfp = true; 1391 if (!kvm_enabled()) { 1392 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1393 } 1394 } 1395 1396 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1397 cpu->has_neon = true; 1398 if (!kvm_enabled()) { 1399 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1400 } 1401 } 1402 1403 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1404 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1405 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1406 } 1407 1408 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1409 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1410 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1411 qdev_property_add_static(DEVICE(obj), 1412 &arm_cpu_pmsav7_dregion_property); 1413 } 1414 } 1415 1416 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1417 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1418 qdev_prop_allow_set_link_before_realize, 1419 OBJ_PROP_LINK_STRONG); 1420 /* 1421 * M profile: initial value of the Secure VTOR. We can't just use 1422 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1423 * the property to be set after realize. 1424 */ 1425 object_property_add_uint32_ptr(obj, "init-svtor", 1426 &cpu->init_svtor, 1427 OBJ_PROP_FLAG_READWRITE); 1428 } 1429 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1430 /* 1431 * Initial value of the NS VTOR (for cores without the Security 1432 * extension, this is the only VTOR) 1433 */ 1434 object_property_add_uint32_ptr(obj, "init-nsvtor", 1435 &cpu->init_nsvtor, 1436 OBJ_PROP_FLAG_READWRITE); 1437 } 1438 1439 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1440 object_property_add_uint32_ptr(obj, "psci-conduit", 1441 &cpu->psci_conduit, 1442 OBJ_PROP_FLAG_READWRITE); 1443 1444 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1445 1446 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1447 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1448 } 1449 1450 if (kvm_enabled()) { 1451 kvm_arm_add_vcpu_properties(obj); 1452 } 1453 1454 #ifndef CONFIG_USER_ONLY 1455 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1456 cpu_isar_feature(aa64_mte, cpu)) { 1457 object_property_add_link(obj, "tag-memory", 1458 TYPE_MEMORY_REGION, 1459 (Object **)&cpu->tag_memory, 1460 qdev_prop_allow_set_link_before_realize, 1461 OBJ_PROP_LINK_STRONG); 1462 1463 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1464 object_property_add_link(obj, "secure-tag-memory", 1465 TYPE_MEMORY_REGION, 1466 (Object **)&cpu->secure_tag_memory, 1467 qdev_prop_allow_set_link_before_realize, 1468 OBJ_PROP_LINK_STRONG); 1469 } 1470 } 1471 #endif 1472 } 1473 1474 static void arm_cpu_finalizefn(Object *obj) 1475 { 1476 ARMCPU *cpu = ARM_CPU(obj); 1477 ARMELChangeHook *hook, *next; 1478 1479 g_hash_table_destroy(cpu->cp_regs); 1480 1481 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1482 QLIST_REMOVE(hook, node); 1483 g_free(hook); 1484 } 1485 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1486 QLIST_REMOVE(hook, node); 1487 g_free(hook); 1488 } 1489 #ifndef CONFIG_USER_ONLY 1490 if (cpu->pmu_timer) { 1491 timer_free(cpu->pmu_timer); 1492 } 1493 #endif 1494 } 1495 1496 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1497 { 1498 Error *local_err = NULL; 1499 1500 #ifdef TARGET_AARCH64 1501 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1502 arm_cpu_sve_finalize(cpu, &local_err); 1503 if (local_err != NULL) { 1504 error_propagate(errp, local_err); 1505 return; 1506 } 1507 1508 arm_cpu_sme_finalize(cpu, &local_err); 1509 if (local_err != NULL) { 1510 error_propagate(errp, local_err); 1511 return; 1512 } 1513 1514 arm_cpu_pauth_finalize(cpu, &local_err); 1515 if (local_err != NULL) { 1516 error_propagate(errp, local_err); 1517 return; 1518 } 1519 1520 arm_cpu_lpa2_finalize(cpu, &local_err); 1521 if (local_err != NULL) { 1522 error_propagate(errp, local_err); 1523 return; 1524 } 1525 } 1526 #endif 1527 1528 if (kvm_enabled()) { 1529 kvm_arm_steal_time_finalize(cpu, &local_err); 1530 if (local_err != NULL) { 1531 error_propagate(errp, local_err); 1532 return; 1533 } 1534 } 1535 } 1536 1537 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1538 { 1539 CPUState *cs = CPU(dev); 1540 ARMCPU *cpu = ARM_CPU(dev); 1541 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1542 CPUARMState *env = &cpu->env; 1543 int pagebits; 1544 Error *local_err = NULL; 1545 bool no_aa32 = false; 1546 1547 /* If we needed to query the host kernel for the CPU features 1548 * then it's possible that might have failed in the initfn, but 1549 * this is the first point where we can report it. 1550 */ 1551 if (cpu->host_cpu_probe_failed) { 1552 if (!kvm_enabled() && !hvf_enabled()) { 1553 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1554 } else { 1555 error_setg(errp, "Failed to retrieve host CPU features"); 1556 } 1557 return; 1558 } 1559 1560 #ifndef CONFIG_USER_ONLY 1561 /* The NVIC and M-profile CPU are two halves of a single piece of 1562 * hardware; trying to use one without the other is a command line 1563 * error and will result in segfaults if not caught here. 1564 */ 1565 if (arm_feature(env, ARM_FEATURE_M)) { 1566 if (!env->nvic) { 1567 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1568 return; 1569 } 1570 } else { 1571 if (env->nvic) { 1572 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1573 return; 1574 } 1575 } 1576 1577 if (!tcg_enabled() && !qtest_enabled()) { 1578 /* 1579 * We assume that no accelerator except TCG (and the "not really an 1580 * accelerator" qtest) can handle these features, because Arm hardware 1581 * virtualization can't virtualize them. 1582 * 1583 * Catch all the cases which might cause us to create more than one 1584 * address space for the CPU (otherwise we will assert() later in 1585 * cpu_address_space_init()). 1586 */ 1587 if (arm_feature(env, ARM_FEATURE_M)) { 1588 error_setg(errp, 1589 "Cannot enable %s when using an M-profile guest CPU", 1590 current_accel_name()); 1591 return; 1592 } 1593 if (cpu->has_el3) { 1594 error_setg(errp, 1595 "Cannot enable %s when guest CPU has EL3 enabled", 1596 current_accel_name()); 1597 return; 1598 } 1599 if (cpu->tag_memory) { 1600 error_setg(errp, 1601 "Cannot enable %s when guest CPUs has MTE enabled", 1602 current_accel_name()); 1603 return; 1604 } 1605 } 1606 1607 { 1608 uint64_t scale; 1609 1610 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1611 if (!cpu->gt_cntfrq_hz) { 1612 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1613 cpu->gt_cntfrq_hz); 1614 return; 1615 } 1616 scale = gt_cntfrq_period_ns(cpu); 1617 } else { 1618 scale = GTIMER_SCALE; 1619 } 1620 1621 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1622 arm_gt_ptimer_cb, cpu); 1623 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1624 arm_gt_vtimer_cb, cpu); 1625 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1626 arm_gt_htimer_cb, cpu); 1627 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1628 arm_gt_stimer_cb, cpu); 1629 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1630 arm_gt_hvtimer_cb, cpu); 1631 } 1632 #endif 1633 1634 cpu_exec_realizefn(cs, &local_err); 1635 if (local_err != NULL) { 1636 error_propagate(errp, local_err); 1637 return; 1638 } 1639 1640 arm_cpu_finalize_features(cpu, &local_err); 1641 if (local_err != NULL) { 1642 error_propagate(errp, local_err); 1643 return; 1644 } 1645 1646 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1647 cpu->has_vfp != cpu->has_neon) { 1648 /* 1649 * This is an architectural requirement for AArch64; AArch32 is 1650 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1651 */ 1652 error_setg(errp, 1653 "AArch64 CPUs must have both VFP and Neon or neither"); 1654 return; 1655 } 1656 1657 if (!cpu->has_vfp) { 1658 uint64_t t; 1659 uint32_t u; 1660 1661 t = cpu->isar.id_aa64isar1; 1662 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1663 cpu->isar.id_aa64isar1 = t; 1664 1665 t = cpu->isar.id_aa64pfr0; 1666 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1667 cpu->isar.id_aa64pfr0 = t; 1668 1669 u = cpu->isar.id_isar6; 1670 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1671 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1672 cpu->isar.id_isar6 = u; 1673 1674 u = cpu->isar.mvfr0; 1675 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1676 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1677 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1678 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1679 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1680 if (!arm_feature(env, ARM_FEATURE_M)) { 1681 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1682 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1683 } 1684 cpu->isar.mvfr0 = u; 1685 1686 u = cpu->isar.mvfr1; 1687 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1688 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1689 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1690 if (arm_feature(env, ARM_FEATURE_M)) { 1691 u = FIELD_DP32(u, MVFR1, FP16, 0); 1692 } 1693 cpu->isar.mvfr1 = u; 1694 1695 u = cpu->isar.mvfr2; 1696 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1697 cpu->isar.mvfr2 = u; 1698 } 1699 1700 if (!cpu->has_neon) { 1701 uint64_t t; 1702 uint32_t u; 1703 1704 unset_feature(env, ARM_FEATURE_NEON); 1705 1706 t = cpu->isar.id_aa64isar0; 1707 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1708 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1709 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1710 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1711 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1712 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1713 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1714 cpu->isar.id_aa64isar0 = t; 1715 1716 t = cpu->isar.id_aa64isar1; 1717 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1718 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1719 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1720 cpu->isar.id_aa64isar1 = t; 1721 1722 t = cpu->isar.id_aa64pfr0; 1723 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1724 cpu->isar.id_aa64pfr0 = t; 1725 1726 u = cpu->isar.id_isar5; 1727 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1728 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1729 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1730 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1731 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1732 cpu->isar.id_isar5 = u; 1733 1734 u = cpu->isar.id_isar6; 1735 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1736 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1737 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1738 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1739 cpu->isar.id_isar6 = u; 1740 1741 if (!arm_feature(env, ARM_FEATURE_M)) { 1742 u = cpu->isar.mvfr1; 1743 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1744 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1745 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1746 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1747 cpu->isar.mvfr1 = u; 1748 1749 u = cpu->isar.mvfr2; 1750 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1751 cpu->isar.mvfr2 = u; 1752 } 1753 } 1754 1755 if (!cpu->has_neon && !cpu->has_vfp) { 1756 uint64_t t; 1757 uint32_t u; 1758 1759 t = cpu->isar.id_aa64isar0; 1760 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1761 cpu->isar.id_aa64isar0 = t; 1762 1763 t = cpu->isar.id_aa64isar1; 1764 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1765 cpu->isar.id_aa64isar1 = t; 1766 1767 u = cpu->isar.mvfr0; 1768 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1769 cpu->isar.mvfr0 = u; 1770 1771 /* Despite the name, this field covers both VFP and Neon */ 1772 u = cpu->isar.mvfr1; 1773 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1774 cpu->isar.mvfr1 = u; 1775 } 1776 1777 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1778 uint32_t u; 1779 1780 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1781 1782 u = cpu->isar.id_isar1; 1783 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1784 cpu->isar.id_isar1 = u; 1785 1786 u = cpu->isar.id_isar2; 1787 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1788 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1789 cpu->isar.id_isar2 = u; 1790 1791 u = cpu->isar.id_isar3; 1792 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1793 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1794 cpu->isar.id_isar3 = u; 1795 } 1796 1797 /* Some features automatically imply others: */ 1798 if (arm_feature(env, ARM_FEATURE_V8)) { 1799 if (arm_feature(env, ARM_FEATURE_M)) { 1800 set_feature(env, ARM_FEATURE_V7); 1801 } else { 1802 set_feature(env, ARM_FEATURE_V7VE); 1803 } 1804 } 1805 1806 /* 1807 * There exist AArch64 cpus without AArch32 support. When KVM 1808 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1809 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1810 * As a general principle, we also do not make ID register 1811 * consistency checks anywhere unless using TCG, because only 1812 * for TCG would a consistency-check failure be a QEMU bug. 1813 */ 1814 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1815 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1816 } 1817 1818 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1819 /* v7 Virtualization Extensions. In real hardware this implies 1820 * EL2 and also the presence of the Security Extensions. 1821 * For QEMU, for backwards-compatibility we implement some 1822 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1823 * include the various other features that V7VE implies. 1824 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1825 * Security Extensions is ARM_FEATURE_EL3. 1826 */ 1827 assert(!tcg_enabled() || no_aa32 || 1828 cpu_isar_feature(aa32_arm_div, cpu)); 1829 set_feature(env, ARM_FEATURE_LPAE); 1830 set_feature(env, ARM_FEATURE_V7); 1831 } 1832 if (arm_feature(env, ARM_FEATURE_V7)) { 1833 set_feature(env, ARM_FEATURE_VAPA); 1834 set_feature(env, ARM_FEATURE_THUMB2); 1835 set_feature(env, ARM_FEATURE_MPIDR); 1836 if (!arm_feature(env, ARM_FEATURE_M)) { 1837 set_feature(env, ARM_FEATURE_V6K); 1838 } else { 1839 set_feature(env, ARM_FEATURE_V6); 1840 } 1841 1842 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1843 * non-EL3 configs. This is needed by some legacy boards. 1844 */ 1845 set_feature(env, ARM_FEATURE_VBAR); 1846 } 1847 if (arm_feature(env, ARM_FEATURE_V6K)) { 1848 set_feature(env, ARM_FEATURE_V6); 1849 set_feature(env, ARM_FEATURE_MVFR); 1850 } 1851 if (arm_feature(env, ARM_FEATURE_V6)) { 1852 set_feature(env, ARM_FEATURE_V5); 1853 if (!arm_feature(env, ARM_FEATURE_M)) { 1854 assert(!tcg_enabled() || no_aa32 || 1855 cpu_isar_feature(aa32_jazelle, cpu)); 1856 set_feature(env, ARM_FEATURE_AUXCR); 1857 } 1858 } 1859 if (arm_feature(env, ARM_FEATURE_V5)) { 1860 set_feature(env, ARM_FEATURE_V4T); 1861 } 1862 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1863 set_feature(env, ARM_FEATURE_V7MP); 1864 } 1865 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1866 set_feature(env, ARM_FEATURE_CBAR); 1867 } 1868 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1869 !arm_feature(env, ARM_FEATURE_M)) { 1870 set_feature(env, ARM_FEATURE_THUMB_DSP); 1871 } 1872 1873 /* 1874 * We rely on no XScale CPU having VFP so we can use the same bits in the 1875 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1876 */ 1877 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1878 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1879 !arm_feature(env, ARM_FEATURE_XSCALE)); 1880 1881 if (arm_feature(env, ARM_FEATURE_V7) && 1882 !arm_feature(env, ARM_FEATURE_M) && 1883 !arm_feature(env, ARM_FEATURE_PMSA)) { 1884 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1885 * can use 4K pages. 1886 */ 1887 pagebits = 12; 1888 } else { 1889 /* For CPUs which might have tiny 1K pages, or which have an 1890 * MPU and might have small region sizes, stick with 1K pages. 1891 */ 1892 pagebits = 10; 1893 } 1894 if (!set_preferred_target_page_bits(pagebits)) { 1895 /* This can only ever happen for hotplugging a CPU, or if 1896 * the board code incorrectly creates a CPU which it has 1897 * promised via minimum_page_size that it will not. 1898 */ 1899 error_setg(errp, "This CPU requires a smaller page size than the " 1900 "system is using"); 1901 return; 1902 } 1903 1904 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1905 * We don't support setting cluster ID ([16..23]) (known as Aff2 1906 * in later ARM ARM versions), or any of the higher affinity level fields, 1907 * so these bits always RAZ. 1908 */ 1909 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1910 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1911 ARM_DEFAULT_CPUS_PER_CLUSTER); 1912 } 1913 1914 if (cpu->reset_hivecs) { 1915 cpu->reset_sctlr |= (1 << 13); 1916 } 1917 1918 if (cpu->cfgend) { 1919 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1920 cpu->reset_sctlr |= SCTLR_EE; 1921 } else { 1922 cpu->reset_sctlr |= SCTLR_B; 1923 } 1924 } 1925 1926 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1927 /* If the has_el3 CPU property is disabled then we need to disable the 1928 * feature. 1929 */ 1930 unset_feature(env, ARM_FEATURE_EL3); 1931 1932 /* 1933 * Disable the security extension feature bits in the processor 1934 * feature registers as well. 1935 */ 1936 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 1937 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 1938 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1939 ID_AA64PFR0, EL3, 0); 1940 } 1941 1942 if (!cpu->has_el2) { 1943 unset_feature(env, ARM_FEATURE_EL2); 1944 } 1945 1946 if (!cpu->has_pmu) { 1947 unset_feature(env, ARM_FEATURE_PMU); 1948 } 1949 if (arm_feature(env, ARM_FEATURE_PMU)) { 1950 pmu_init(cpu); 1951 1952 if (!kvm_enabled()) { 1953 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1954 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1955 } 1956 1957 #ifndef CONFIG_USER_ONLY 1958 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1959 cpu); 1960 #endif 1961 } else { 1962 cpu->isar.id_aa64dfr0 = 1963 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1964 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1965 cpu->pmceid0 = 0; 1966 cpu->pmceid1 = 0; 1967 } 1968 1969 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1970 /* 1971 * Disable the hypervisor feature bits in the processor feature 1972 * registers if we don't have EL2. 1973 */ 1974 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1975 ID_AA64PFR0, EL2, 0); 1976 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 1977 ID_PFR1, VIRTUALIZATION, 0); 1978 } 1979 1980 #ifndef CONFIG_USER_ONLY 1981 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1982 /* 1983 * Disable the MTE feature bits if we do not have tag-memory 1984 * provided by the machine. 1985 */ 1986 cpu->isar.id_aa64pfr1 = 1987 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1988 } 1989 #endif 1990 1991 if (tcg_enabled()) { 1992 /* 1993 * Don't report the Statistical Profiling Extension in the ID 1994 * registers, because TCG doesn't implement it yet (not even a 1995 * minimal stub version) and guests will fall over when they 1996 * try to access the non-existent system registers for it. 1997 */ 1998 cpu->isar.id_aa64dfr0 = 1999 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); 2000 } 2001 2002 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2003 * to false or by setting pmsav7-dregion to 0. 2004 */ 2005 if (!cpu->has_mpu) { 2006 cpu->pmsav7_dregion = 0; 2007 } 2008 if (cpu->pmsav7_dregion == 0) { 2009 cpu->has_mpu = false; 2010 } 2011 2012 if (arm_feature(env, ARM_FEATURE_PMSA) && 2013 arm_feature(env, ARM_FEATURE_V7)) { 2014 uint32_t nr = cpu->pmsav7_dregion; 2015 2016 if (nr > 0xff) { 2017 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2018 return; 2019 } 2020 2021 if (nr) { 2022 if (arm_feature(env, ARM_FEATURE_V8)) { 2023 /* PMSAv8 */ 2024 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2025 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2026 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2027 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2028 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2029 } 2030 } else { 2031 env->pmsav7.drbar = g_new0(uint32_t, nr); 2032 env->pmsav7.drsr = g_new0(uint32_t, nr); 2033 env->pmsav7.dracr = g_new0(uint32_t, nr); 2034 } 2035 } 2036 } 2037 2038 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2039 uint32_t nr = cpu->sau_sregion; 2040 2041 if (nr > 0xff) { 2042 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2043 return; 2044 } 2045 2046 if (nr) { 2047 env->sau.rbar = g_new0(uint32_t, nr); 2048 env->sau.rlar = g_new0(uint32_t, nr); 2049 } 2050 } 2051 2052 if (arm_feature(env, ARM_FEATURE_EL3)) { 2053 set_feature(env, ARM_FEATURE_VBAR); 2054 } 2055 2056 register_cp_regs_for_features(cpu); 2057 arm_cpu_register_gdb_regs_for_features(cpu); 2058 2059 init_cpreg_list(cpu); 2060 2061 #ifndef CONFIG_USER_ONLY 2062 MachineState *ms = MACHINE(qdev_get_machine()); 2063 unsigned int smp_cpus = ms->smp.cpus; 2064 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2065 2066 /* 2067 * We must set cs->num_ases to the final value before 2068 * the first call to cpu_address_space_init. 2069 */ 2070 if (cpu->tag_memory != NULL) { 2071 cs->num_ases = 3 + has_secure; 2072 } else { 2073 cs->num_ases = 1 + has_secure; 2074 } 2075 2076 if (has_secure) { 2077 if (!cpu->secure_memory) { 2078 cpu->secure_memory = cs->memory; 2079 } 2080 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2081 cpu->secure_memory); 2082 } 2083 2084 if (cpu->tag_memory != NULL) { 2085 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2086 cpu->tag_memory); 2087 if (has_secure) { 2088 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2089 cpu->secure_tag_memory); 2090 } 2091 } 2092 2093 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2094 2095 /* No core_count specified, default to smp_cpus. */ 2096 if (cpu->core_count == -1) { 2097 cpu->core_count = smp_cpus; 2098 } 2099 #endif 2100 2101 if (tcg_enabled()) { 2102 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2103 2104 /* 2105 * We only support DCZ blocklen that fits on one page. 2106 * 2107 * Architectually this is always true. However TARGET_PAGE_SIZE 2108 * is variable and, for compatibility with -machine virt-2.7, 2109 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2110 * But even then, while the largest architectural DCZ blocklen 2111 * is 2KiB, no cpu actually uses such a large blocklen. 2112 */ 2113 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2114 2115 /* 2116 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2117 * both nibbles of each byte storing tag data may be written at once. 2118 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2119 */ 2120 if (cpu_isar_feature(aa64_mte, cpu)) { 2121 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2122 } 2123 } 2124 2125 qemu_init_vcpu(cs); 2126 cpu_reset(cs); 2127 2128 acc->parent_realize(dev, errp); 2129 } 2130 2131 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2132 { 2133 ObjectClass *oc; 2134 char *typename; 2135 char **cpuname; 2136 const char *cpunamestr; 2137 2138 cpuname = g_strsplit(cpu_model, ",", 1); 2139 cpunamestr = cpuname[0]; 2140 #ifdef CONFIG_USER_ONLY 2141 /* For backwards compatibility usermode emulation allows "-cpu any", 2142 * which has the same semantics as "-cpu max". 2143 */ 2144 if (!strcmp(cpunamestr, "any")) { 2145 cpunamestr = "max"; 2146 } 2147 #endif 2148 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2149 oc = object_class_by_name(typename); 2150 g_strfreev(cpuname); 2151 g_free(typename); 2152 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 2153 object_class_is_abstract(oc)) { 2154 return NULL; 2155 } 2156 return oc; 2157 } 2158 2159 static Property arm_cpu_properties[] = { 2160 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2161 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2162 mp_affinity, ARM64_AFFINITY_INVALID), 2163 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2164 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2165 DEFINE_PROP_END_OF_LIST() 2166 }; 2167 2168 static gchar *arm_gdb_arch_name(CPUState *cs) 2169 { 2170 ARMCPU *cpu = ARM_CPU(cs); 2171 CPUARMState *env = &cpu->env; 2172 2173 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2174 return g_strdup("iwmmxt"); 2175 } 2176 return g_strdup("arm"); 2177 } 2178 2179 #ifndef CONFIG_USER_ONLY 2180 #include "hw/core/sysemu-cpu-ops.h" 2181 2182 static const struct SysemuCPUOps arm_sysemu_ops = { 2183 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2184 .asidx_from_attrs = arm_asidx_from_attrs, 2185 .write_elf32_note = arm_cpu_write_elf32_note, 2186 .write_elf64_note = arm_cpu_write_elf64_note, 2187 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2188 .legacy_vmsd = &vmstate_arm_cpu, 2189 }; 2190 #endif 2191 2192 #ifdef CONFIG_TCG 2193 static const struct TCGCPUOps arm_tcg_ops = { 2194 .initialize = arm_translate_init, 2195 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2196 .debug_excp_handler = arm_debug_excp_handler, 2197 .restore_state_to_opc = arm_restore_state_to_opc, 2198 2199 #ifdef CONFIG_USER_ONLY 2200 .record_sigsegv = arm_cpu_record_sigsegv, 2201 .record_sigbus = arm_cpu_record_sigbus, 2202 #else 2203 .tlb_fill = arm_cpu_tlb_fill, 2204 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2205 .do_interrupt = arm_cpu_do_interrupt, 2206 .do_transaction_failed = arm_cpu_do_transaction_failed, 2207 .do_unaligned_access = arm_cpu_do_unaligned_access, 2208 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2209 .debug_check_watchpoint = arm_debug_check_watchpoint, 2210 .debug_check_breakpoint = arm_debug_check_breakpoint, 2211 #endif /* !CONFIG_USER_ONLY */ 2212 }; 2213 #endif /* CONFIG_TCG */ 2214 2215 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2216 { 2217 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2218 CPUClass *cc = CPU_CLASS(acc); 2219 DeviceClass *dc = DEVICE_CLASS(oc); 2220 ResettableClass *rc = RESETTABLE_CLASS(oc); 2221 2222 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2223 &acc->parent_realize); 2224 2225 device_class_set_props(dc, arm_cpu_properties); 2226 2227 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2228 &acc->parent_phases); 2229 2230 cc->class_by_name = arm_cpu_class_by_name; 2231 cc->has_work = arm_cpu_has_work; 2232 cc->dump_state = arm_cpu_dump_state; 2233 cc->set_pc = arm_cpu_set_pc; 2234 cc->get_pc = arm_cpu_get_pc; 2235 cc->gdb_read_register = arm_cpu_gdb_read_register; 2236 cc->gdb_write_register = arm_cpu_gdb_write_register; 2237 #ifndef CONFIG_USER_ONLY 2238 cc->sysemu_ops = &arm_sysemu_ops; 2239 #endif 2240 cc->gdb_num_core_regs = 26; 2241 cc->gdb_core_xml_file = "arm-core.xml"; 2242 cc->gdb_arch_name = arm_gdb_arch_name; 2243 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2244 cc->gdb_stop_before_watchpoint = true; 2245 cc->disas_set_info = arm_disas_set_info; 2246 2247 #ifdef CONFIG_TCG 2248 cc->tcg_ops = &arm_tcg_ops; 2249 #endif /* CONFIG_TCG */ 2250 } 2251 2252 static void arm_cpu_instance_init(Object *obj) 2253 { 2254 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2255 2256 acc->info->initfn(obj); 2257 arm_cpu_post_init(obj); 2258 } 2259 2260 static void cpu_register_class_init(ObjectClass *oc, void *data) 2261 { 2262 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2263 2264 acc->info = data; 2265 } 2266 2267 void arm_cpu_register(const ARMCPUInfo *info) 2268 { 2269 TypeInfo type_info = { 2270 .parent = TYPE_ARM_CPU, 2271 .instance_size = sizeof(ARMCPU), 2272 .instance_align = __alignof__(ARMCPU), 2273 .instance_init = arm_cpu_instance_init, 2274 .class_size = sizeof(ARMCPUClass), 2275 .class_init = info->class_init ?: cpu_register_class_init, 2276 .class_data = (void *)info, 2277 }; 2278 2279 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2280 type_register(&type_info); 2281 g_free((void *)type_info.name); 2282 } 2283 2284 static const TypeInfo arm_cpu_type_info = { 2285 .name = TYPE_ARM_CPU, 2286 .parent = TYPE_CPU, 2287 .instance_size = sizeof(ARMCPU), 2288 .instance_align = __alignof__(ARMCPU), 2289 .instance_init = arm_cpu_initfn, 2290 .instance_finalize = arm_cpu_finalizefn, 2291 .abstract = true, 2292 .class_size = sizeof(ARMCPUClass), 2293 .class_init = arm_cpu_class_init, 2294 }; 2295 2296 static void arm_cpu_register_types(void) 2297 { 2298 type_register_static(&arm_cpu_type_info); 2299 } 2300 2301 type_init(arm_cpu_register_types) 2302