boot.h (b11728dc3ae67ddedf34b7a4f318170e7092803c) boot.h (55c136599f512a86e3fec9f77b6b5a30a6b34cca)
1/*
2 * QEMU RISC-V Boot Helper
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,

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30bool riscv_is_32bit(RISCVHartArrayState *harts);
31
32char *riscv_plic_hart_config_string(int hart_count);
33
34target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
35 target_ulong firmware_end_addr);
36target_ulong riscv_find_and_load_firmware(MachineState *machine,
37 const char *default_machine_firmware,
1/*
2 * QEMU RISC-V Boot Helper
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,

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30bool riscv_is_32bit(RISCVHartArrayState *harts);
31
32char *riscv_plic_hart_config_string(int hart_count);
33
34target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
35 target_ulong firmware_end_addr);
36target_ulong riscv_find_and_load_firmware(MachineState *machine,
37 const char *default_machine_firmware,
38 hwaddr firmware_load_addr,
38 hwaddr *firmware_load_addr,
39 symbol_fn_t sym_cb);
40const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
41char *riscv_find_firmware(const char *firmware_filename,
42 const char *default_machine_firmware);
43target_ulong riscv_load_firmware(const char *firmware_filename,
39 symbol_fn_t sym_cb);
40const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
41char *riscv_find_firmware(const char *firmware_filename,
42 const char *default_machine_firmware);
43target_ulong riscv_load_firmware(const char *firmware_filename,
44 hwaddr firmware_load_addr,
44 hwaddr *firmware_load_addr,
45 symbol_fn_t sym_cb);
46target_ulong riscv_load_kernel(MachineState *machine,
47 RISCVHartArrayState *harts,
48 target_ulong firmware_end_addr,
49 bool load_initrd,
50 symbol_fn_t sym_cb);
51uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
52 MachineState *ms);

--- 14 unchanged lines hidden --- 		45 symbol_fn_t sym_cb);
46target_ulong riscv_load_kernel(MachineState *machine,
47 RISCVHartArrayState *harts,
48 target_ulong firmware_end_addr,
49 bool load_initrd,
50 symbol_fn_t sym_cb);
51uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
52 MachineState *ms);

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