npcm7xx.h (fc11115f74b4355b38eeebc118e347cd74f35845) npcm7xx.h (a9d3d7b17e5a3c246ecf4e420d2d4bb089a8d7c3)
1/*
2 * Nuvoton NPCM7xx SoC family.
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or

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13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 */
16#ifndef NPCM7XX_H
17#define NPCM7XX_H
18
19#include "hw/boards.h"
20#include "hw/adc/npcm7xx_adc.h"
1/*
2 * Nuvoton NPCM7xx SoC family.
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or

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13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 */
16#ifndef NPCM7XX_H
17#define NPCM7XX_H
18
19#include "hw/boards.h"
20#include "hw/adc/npcm7xx_adc.h"
21#include "hw/core/split-irq.h"
21#include "hw/cpu/a9mpcore.h"
22#include "hw/gpio/npcm7xx_gpio.h"
23#include "hw/i2c/npcm7xx_smbus.h"
24#include "hw/mem/npcm7xx_mc.h"
25#include "hw/misc/npcm7xx_clk.h"
26#include "hw/misc/npcm7xx_gcr.h"
27#include "hw/misc/npcm7xx_mft.h"
28#include "hw/misc/npcm7xx_pwm.h"

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43
44/* Magic addresses for setting up direct kernel booting and SMP boot stubs. */
45#define NPCM7XX_LOADER_START (0x00000000) /* Start of SDRAM */
46#define NPCM7XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */
47#define NPCM7XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */
48#define NPCM7XX_GIC_CPU_IF_ADDR (0xf03fe100) /* GIC within A9 */
49#define NPCM7XX_BOARD_SETUP_ADDR (0xffff1000) /* Boot ROM */
50
22#include "hw/cpu/a9mpcore.h"
23#include "hw/gpio/npcm7xx_gpio.h"
24#include "hw/i2c/npcm7xx_smbus.h"
25#include "hw/mem/npcm7xx_mc.h"
26#include "hw/misc/npcm7xx_clk.h"
27#include "hw/misc/npcm7xx_gcr.h"
28#include "hw/misc/npcm7xx_mft.h"
29#include "hw/misc/npcm7xx_pwm.h"

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44
45/* Magic addresses for setting up direct kernel booting and SMP boot stubs. */
46#define NPCM7XX_LOADER_START (0x00000000) /* Start of SDRAM */
47#define NPCM7XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */
48#define NPCM7XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */
49#define NPCM7XX_GIC_CPU_IF_ADDR (0xf03fe100) /* GIC within A9 */
50#define NPCM7XX_BOARD_SETUP_ADDR (0xffff1000) /* Boot ROM */
51
52#define NPCM7XX_NR_PWM_MODULES 2
53
51typedef struct NPCM7xxMachine {
52 MachineState parent;
54typedef struct NPCM7xxMachine {
55 MachineState parent;
56 /*
57 * PWM fan splitter. each splitter connects to one PWM output and
58 * multiple MFT inputs.
59 */
60 SplitIRQ fan_splitter[NPCM7XX_NR_PWM_MODULES *
61 NPCM7XX_PWM_PER_MODULE];
53} NPCM7xxMachine;
54
55#define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
56#define NPCM7XX_MACHINE(obj) \
57 OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE)
58
59typedef struct NPCM7xxMachineClass {
60 MachineClass parent;

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77 MemoryRegion irom;
78 MemoryRegion ram3;
79 MemoryRegion *dram;
80
81 NPCM7xxGCRState gcr;
82 NPCM7xxCLKState clk;
83 NPCM7xxTimerCtrlState tim[3];
84 NPCM7xxADCState adc;
62} NPCM7xxMachine;
63
64#define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
65#define NPCM7XX_MACHINE(obj) \
66 OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE)
67
68typedef struct NPCM7xxMachineClass {
69 MachineClass parent;

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86 MemoryRegion irom;
87 MemoryRegion ram3;
88 MemoryRegion *dram;
89
90 NPCM7xxGCRState gcr;
91 NPCM7xxCLKState clk;
92 NPCM7xxTimerCtrlState tim[3];
93 NPCM7xxADCState adc;
85 NPCM7xxPWMState pwm[2];
94 NPCM7xxPWMState pwm[NPCM7XX_NR_PWM_MODULES];
86 NPCM7xxMFTState mft[8];
87 NPCM7xxOTPState key_storage;
88 NPCM7xxOTPState fuse_array;
89 NPCM7xxMCState mc;
90 NPCM7xxRNGState rng;
91 NPCM7xxGPIOState gpio[8];
92 NPCM7xxSMBusState smbus[16];
93 EHCISysBusState ehci;

--- 37 unchanged lines hidden --- 		95 NPCM7xxMFTState mft[8];
96 NPCM7xxOTPState key_storage;
97 NPCM7xxOTPState fuse_array;
98 NPCM7xxMCState mc;
99 NPCM7xxRNGState rng;
100 NPCM7xxGPIOState gpio[8];
101 NPCM7xxSMBusState smbus[16];
102 EHCISysBusState ehci;

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