spike.c (9bca0edb282de0007a4f068d9d20f3e3c3aadef7) spike.c (2a8756ed7d64f8fed6ad50fb062f7118e47c856c)
1/*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *

--- 101 unchanged lines hidden (view full) ---

110 qemu_fdt_add_subnode(fdt, nodename);
111 qemu_fdt_setprop_cells(fdt, nodename, "reg",
112 memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base,
113 mem_size >> 32, mem_size);
114 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
115 g_free(nodename);
116
117 qemu_fdt_add_subnode(fdt, "/cpus");
1/*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *

--- 101 unchanged lines hidden (view full) ---

110 qemu_fdt_add_subnode(fdt, nodename);
111 qemu_fdt_setprop_cells(fdt, nodename, "reg",
112 memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base,
113 mem_size >> 32, mem_size);
114 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
115 g_free(nodename);
116
117 qemu_fdt_add_subnode(fdt, "/cpus");
118 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000);
118 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
119 SIFIVE_CLINT_TIMEBASE_FREQ);
119 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
120 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
121
122 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
123 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
124 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
125 char *isa = riscv_isa_string(&s->soc.harts[cpu]);
126 qemu_fdt_add_subnode(fdt, nodename);
120 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
121 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
122
123 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
124 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
125 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
126 char *isa = riscv_isa_string(&s->soc.harts[cpu]);
127 qemu_fdt_add_subnode(fdt, nodename);
127 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000);
128 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
129 SPIKE_CLOCK_FREQ);
128 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
129 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
130 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
131 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
132 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
133 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
134 qemu_fdt_add_subnode(fdt, intc);
135 qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);

--- 241 unchanged lines hidden --- 		130 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
131 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
132 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
133 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
134 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
135 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
136 qemu_fdt_add_subnode(fdt, intc);
137 qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);

--- 241 unchanged lines hidden ---