sifive_u.c (2308092b2b78e6e083092bd3599cec6a0769319e) sifive_u.c (647a70a10f257bdeba33ff5f1bcb2b26518a9f4c)
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 *
7 * Provides a board compatible with the SiFive Freedom U SDK:
8 *

--- 303 unchanged lines hidden (view full) ---

312 SIFIVE_U_PLIC_PRIORITY_BASE,
313 SIFIVE_U_PLIC_PENDING_BASE,
314 SIFIVE_U_PLIC_ENABLE_BASE,
315 SIFIVE_U_PLIC_ENABLE_STRIDE,
316 SIFIVE_U_PLIC_CONTEXT_BASE,
317 SIFIVE_U_PLIC_CONTEXT_STRIDE,
318 memmap[SIFIVE_U_PLIC].size);
319 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 *
7 * Provides a board compatible with the SiFive Freedom U SDK:
8 *

--- 303 unchanged lines hidden (view full) ---

312 SIFIVE_U_PLIC_PRIORITY_BASE,
313 SIFIVE_U_PLIC_PENDING_BASE,
314 SIFIVE_U_PLIC_ENABLE_BASE,
315 SIFIVE_U_PLIC_ENABLE_STRIDE,
316 SIFIVE_U_PLIC_CONTEXT_BASE,
317 SIFIVE_U_PLIC_CONTEXT_STRIDE,
318 memmap[SIFIVE_U_PLIC].size);
319 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
320 serial_hd(0), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART0_IRQ]);
320 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
321 /* sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
321 /* sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
322 serial_hd(1), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART1_IRQ]); */
322 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic),
323 SIFIVE_U_UART1_IRQ)); */
323 sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
324 memmap[SIFIVE_U_CLINT].size, smp_cpus,
325 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
326}
327
328static void riscv_sifive_u_machine_init(MachineClass *mc)
329{
330 mc->desc = "RISC-V Board compatible with SiFive U SDK";

--- 29 unchanged lines hidden --- 		324 sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
325 memmap[SIFIVE_U_CLINT].size, smp_cpus,
326 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
327}
328
329static void riscv_sifive_u_machine_init(MachineClass *mc)
330{
331 mc->desc = "RISC-V Board compatible with SiFive U SDK";

--- 29 unchanged lines hidden ---