1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * 7 * Provides a board compatible with the SiFive Freedom U SDK: 8 * 9 * 0) UART 10 * 1) CLINT (Core Level Interruptor) 11 * 2) PLIC (Platform Level Interrupt Controller) 12 * 13 * This board currently uses a hardcoded devicetree that indicates one hart. 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms and conditions of the GNU General Public License, 17 * version 2 or later, as published by the Free Software Foundation. 18 * 19 * This program is distributed in the hope it will be useful, but WITHOUT 20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 22 * more details. 23 * 24 * You should have received a copy of the GNU General Public License along with 25 * this program. If not, see <http://www.gnu.org/licenses/>. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/log.h" 30 #include "qemu/error-report.h" 31 #include "qapi/error.h" 32 #include "hw/hw.h" 33 #include "hw/boards.h" 34 #include "hw/loader.h" 35 #include "hw/sysbus.h" 36 #include "hw/char/serial.h" 37 #include "target/riscv/cpu.h" 38 #include "hw/riscv/riscv_hart.h" 39 #include "hw/riscv/sifive_plic.h" 40 #include "hw/riscv/sifive_clint.h" 41 #include "hw/riscv/sifive_uart.h" 42 #include "hw/riscv/sifive_prci.h" 43 #include "hw/riscv/sifive_u.h" 44 #include "chardev/char.h" 45 #include "sysemu/arch_init.h" 46 #include "sysemu/device_tree.h" 47 #include "exec/address-spaces.h" 48 #include "elf.h" 49 50 #include <libfdt.h> 51 52 static const struct MemmapEntry { 53 hwaddr base; 54 hwaddr size; 55 } sifive_u_memmap[] = { 56 [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, 57 [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, 58 [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, 59 [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, 60 [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, 61 [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, 62 [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, 63 }; 64 65 static uint64_t load_kernel(const char *kernel_filename) 66 { 67 uint64_t kernel_entry, kernel_high; 68 69 if (load_elf(kernel_filename, NULL, NULL, 70 &kernel_entry, NULL, &kernel_high, 71 0, EM_RISCV, 1, 0) < 0) { 72 error_report("qemu: could not load kernel '%s'", kernel_filename); 73 exit(1); 74 } 75 return kernel_entry; 76 } 77 78 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 79 uint64_t mem_size, const char *cmdline) 80 { 81 void *fdt; 82 int cpu; 83 uint32_t *cells; 84 char *nodename; 85 uint32_t plic_phandle; 86 87 fdt = s->fdt = create_device_tree(&s->fdt_size); 88 if (!fdt) { 89 error_report("create_device_tree() failed"); 90 exit(1); 91 } 92 93 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); 94 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); 95 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 96 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 97 98 qemu_fdt_add_subnode(fdt, "/soc"); 99 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 100 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "ucbbar,spike-bare-soc"); 101 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 102 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 103 104 nodename = g_strdup_printf("/memory@%lx", 105 (long)memmap[SIFIVE_U_DRAM].base); 106 qemu_fdt_add_subnode(fdt, nodename); 107 qemu_fdt_setprop_cells(fdt, nodename, "reg", 108 memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base, 109 mem_size >> 32, mem_size); 110 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 111 g_free(nodename); 112 113 qemu_fdt_add_subnode(fdt, "/cpus"); 114 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 115 SIFIVE_CLINT_TIMEBASE_FREQ); 116 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 117 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 118 119 for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) { 120 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 121 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 122 char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]); 123 qemu_fdt_add_subnode(fdt, nodename); 124 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 125 SIFIVE_U_CLOCK_FREQ); 126 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 127 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 128 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 129 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 130 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 131 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 132 qemu_fdt_add_subnode(fdt, intc); 133 qemu_fdt_setprop_cell(fdt, intc, "phandle", 1); 134 qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1); 135 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 136 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 137 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 138 g_free(isa); 139 g_free(intc); 140 g_free(nodename); 141 } 142 143 cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); 144 for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { 145 nodename = 146 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 147 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 148 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 149 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 150 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 151 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 152 g_free(nodename); 153 } 154 nodename = g_strdup_printf("/soc/clint@%lx", 155 (long)memmap[SIFIVE_U_CLINT].base); 156 qemu_fdt_add_subnode(fdt, nodename); 157 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 158 qemu_fdt_setprop_cells(fdt, nodename, "reg", 159 0x0, memmap[SIFIVE_U_CLINT].base, 160 0x0, memmap[SIFIVE_U_CLINT].size); 161 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 162 cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); 163 g_free(cells); 164 g_free(nodename); 165 166 cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); 167 for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { 168 nodename = 169 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 170 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 171 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 172 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 173 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 174 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 175 g_free(nodename); 176 } 177 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 178 (long)memmap[SIFIVE_U_PLIC].base); 179 qemu_fdt_add_subnode(fdt, nodename); 180 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 181 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 182 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 183 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 184 cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); 185 qemu_fdt_setprop_cells(fdt, nodename, "reg", 186 0x0, memmap[SIFIVE_U_PLIC].base, 187 0x0, memmap[SIFIVE_U_PLIC].size); 188 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 189 qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); 190 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 4); 191 qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2); 192 qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2); 193 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 194 g_free(cells); 195 g_free(nodename); 196 197 nodename = g_strdup_printf("/uart@%lx", 198 (long)memmap[SIFIVE_U_UART0].base); 199 qemu_fdt_add_subnode(fdt, nodename); 200 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 201 qemu_fdt_setprop_cells(fdt, nodename, "reg", 202 0x0, memmap[SIFIVE_U_UART0].base, 203 0x0, memmap[SIFIVE_U_UART0].size); 204 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); 205 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1); 206 207 qemu_fdt_add_subnode(fdt, "/chosen"); 208 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 209 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 210 g_free(nodename); 211 } 212 213 static void riscv_sifive_u_init(MachineState *machine) 214 { 215 const struct MemmapEntry *memmap = sifive_u_memmap; 216 217 SiFiveUState *s = g_new0(SiFiveUState, 1); 218 MemoryRegion *system_memory = get_system_memory(); 219 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 220 int i; 221 222 /* Initialize SoC */ 223 object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_U_SOC); 224 object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), 225 &error_abort); 226 object_property_set_bool(OBJECT(&s->soc), true, "realized", 227 &error_abort); 228 229 /* register RAM */ 230 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", 231 machine->ram_size, &error_fatal); 232 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, 233 main_mem); 234 235 /* create device tree */ 236 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 237 238 if (machine->kernel_filename) { 239 load_kernel(machine->kernel_filename); 240 } 241 242 /* reset vector */ 243 uint32_t reset_vec[8] = { 244 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 245 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 246 0xf1402573, /* csrr a0, mhartid */ 247 #if defined(TARGET_RISCV32) 248 0x0182a283, /* lw t0, 24(t0) */ 249 #elif defined(TARGET_RISCV64) 250 0x0182b283, /* ld t0, 24(t0) */ 251 #endif 252 0x00028067, /* jr t0 */ 253 0x00000000, 254 memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */ 255 0x00000000, 256 /* dtb: */ 257 }; 258 259 /* copy in the reset vector in little_endian byte order */ 260 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 261 reset_vec[i] = cpu_to_le32(reset_vec[i]); 262 } 263 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 264 memmap[SIFIVE_U_MROM].base, &address_space_memory); 265 266 /* copy in the device tree */ 267 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > 268 memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { 269 error_report("not enough space to store device-tree"); 270 exit(1); 271 } 272 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); 273 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), 274 memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), 275 &address_space_memory); 276 } 277 278 static void riscv_sifive_u_soc_init(Object *obj) 279 { 280 SiFiveUSoCState *s = RISCV_U_SOC(obj); 281 282 object_initialize(&s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY); 283 object_property_add_child(obj, "cpus", OBJECT(&s->cpus), 284 &error_abort); 285 object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type", 286 &error_abort); 287 object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts", 288 &error_abort); 289 } 290 291 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) 292 { 293 SiFiveUSoCState *s = RISCV_U_SOC(dev); 294 const struct MemmapEntry *memmap = sifive_u_memmap; 295 MemoryRegion *system_memory = get_system_memory(); 296 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 297 298 object_property_set_bool(OBJECT(&s->cpus), true, "realized", 299 &error_abort); 300 301 /* boot rom */ 302 memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", 303 memmap[SIFIVE_U_MROM].size, &error_fatal); 304 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, 305 mask_rom); 306 307 /* MMIO */ 308 s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, 309 (char *)SIFIVE_U_PLIC_HART_CONFIG, 310 SIFIVE_U_PLIC_NUM_SOURCES, 311 SIFIVE_U_PLIC_NUM_PRIORITIES, 312 SIFIVE_U_PLIC_PRIORITY_BASE, 313 SIFIVE_U_PLIC_PENDING_BASE, 314 SIFIVE_U_PLIC_ENABLE_BASE, 315 SIFIVE_U_PLIC_ENABLE_STRIDE, 316 SIFIVE_U_PLIC_CONTEXT_BASE, 317 SIFIVE_U_PLIC_CONTEXT_STRIDE, 318 memmap[SIFIVE_U_PLIC].size); 319 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, 320 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 321 /* sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, 322 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), 323 SIFIVE_U_UART1_IRQ)); */ 324 sifive_clint_create(memmap[SIFIVE_U_CLINT].base, 325 memmap[SIFIVE_U_CLINT].size, smp_cpus, 326 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 327 } 328 329 static void riscv_sifive_u_machine_init(MachineClass *mc) 330 { 331 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 332 mc->init = riscv_sifive_u_init; 333 mc->max_cpus = 1; 334 } 335 336 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) 337 338 static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) 339 { 340 DeviceClass *dc = DEVICE_CLASS(oc); 341 342 dc->realize = riscv_sifive_u_soc_realize; 343 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 344 dc->user_creatable = false; 345 } 346 347 static const TypeInfo riscv_sifive_u_soc_type_info = { 348 .name = TYPE_RISCV_U_SOC, 349 .parent = TYPE_DEVICE, 350 .instance_size = sizeof(SiFiveUSoCState), 351 .instance_init = riscv_sifive_u_soc_init, 352 .class_init = riscv_sifive_u_soc_class_init, 353 }; 354 355 static void riscv_sifive_u_soc_register_types(void) 356 { 357 type_register_static(&riscv_sifive_u_soc_type_info); 358 } 359 360 type_init(riscv_sifive_u_soc_register_types) 361