meson.build (70eb9f9cd1c0b519b31df8ab08ee2198b0e16176) meson.build (b609b7e3199912e16ef3b0447823f21fed73597e)
1riscv_ss = ss.source_set()
2riscv_ss.add(files('boot.c'), fdt)
3riscv_ss.add(files('numa.c'))
4riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
5riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
6riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
7riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
1riscv_ss = ss.source_set()
2riscv_ss.add(files('boot.c'), fdt)
3riscv_ss.add(files('numa.c'))
4riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
5riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
6riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
7riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
8riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
9riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
10riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
11riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
12riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
13
14hw_arch += {'riscv': riscv_ss}
8riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
9riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
10riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
11riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
12
13hw_arch += {'riscv': riscv_ss}