pnv_lpc.c (035b21977ce1791a630c5cbf46e482e54552e05b) pnv_lpc.c (19f703477314a5db09ffc3c0f6be9c45645f8302)
1/*
2 * QEMU PowerPC PowerNV LPC controller
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

--- 224 unchanged lines hidden (view full) ---

233 *
234 * TODO: rework to use address_space_stq() and address_space_ldq()
235 * instead.
236 */
237static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
238 int sz)
239{
240 /* XXX Handle access size limits and FW read caching here */
1/*
2 * QEMU PowerPC PowerNV LPC controller
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

--- 224 unchanged lines hidden (view full) ---

233 *
234 * TODO: rework to use address_space_stq() and address_space_ldq()
235 * instead.
236 */
237static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
238 int sz)
239{
240 /* XXX Handle access size limits and FW read caching here */
241 return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
242 data, sz, false);
241 return !address_space_read(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
242 data, sz);
243}
244
245static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
246 int sz)
247{
248 /* XXX Handle access size limits here */
243}
244
245static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
246 int sz)
247{
248 /* XXX Handle access size limits here */
249 return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
250 data, sz, true);
249 return !address_space_write(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
250 data, sz);
251}
252
253#define ECCB_CTL_READ PPC_BIT(15)
254#define ECCB_CTL_SZ_LSH (63 - 7)
255#define ECCB_CTL_SZ_MASK PPC_BITMASK(4, 7)
256#define ECCB_CTL_ADDR_MASK PPC_BITMASK(32, 63)
257
258#define ECCB_STAT_OP_DONE PPC_BIT(52)

--- 611 unchanged lines hidden --- 		251}
252
253#define ECCB_CTL_READ PPC_BIT(15)
254#define ECCB_CTL_SZ_LSH (63 - 7)
255#define ECCB_CTL_SZ_MASK PPC_BITMASK(4, 7)
256#define ECCB_CTL_ADDR_MASK PPC_BITMASK(32, 63)
257
258#define ECCB_STAT_OP_DONE PPC_BIT(52)

--- 611 unchanged lines hidden ---