vmxnet3.c (55daf493f7659b512e668f61ce4561dc60a27302) | vmxnet3.c (aac8f89dba870bb263d05bb84c3d64e0204be092) |
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1/* 2 * QEMU VMWARE VMXNET3 paravirtual NIC 3 * 4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) 5 * 6 * Developed by Daynix Computing LTD (http://www.daynix.com) 7 * 8 * Authors: --- 837 unchanged lines hidden (view full) --- 846 const void *pkt_data, 847 size_t pkt_len) 848{ 849 struct virtio_net_hdr *vhdr; 850 bool isip4, isip6, istcp, isudp; 851 uint8_t *data; 852 int len; 853 | 1/* 2 * QEMU VMWARE VMXNET3 paravirtual NIC 3 * 4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) 5 * 6 * Developed by Daynix Computing LTD (http://www.daynix.com) 7 * 8 * Authors: --- 837 unchanged lines hidden (view full) --- 846 const void *pkt_data, 847 size_t pkt_len) 848{ 849 struct virtio_net_hdr *vhdr; 850 bool isip4, isip6, istcp, isudp; 851 uint8_t *data; 852 int len; 853 |
854 if (!net_rx_pkt_has_virt_hdr(pkt)) { 855 return; 856 } 857 | |
858 vhdr = net_rx_pkt_get_vhdr(pkt); 859 if (!VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 860 return; 861 } 862 863 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 864 if (!(isip4 || isip6) || !(istcp || isudp)) { 865 return; --- 27 unchanged lines hidden (view full) --- 893 struct virtio_net_hdr *vhdr; 894 uint8_t offload_type; 895 896 if (net_rx_pkt_is_vlan_stripped(pkt)) { 897 rxcd->ts = 1; 898 rxcd->tci = net_rx_pkt_get_vlan_tag(pkt); 899 } 900 | 854 vhdr = net_rx_pkt_get_vhdr(pkt); 855 if (!VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 856 return; 857 } 858 859 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 860 if (!(isip4 || isip6) || !(istcp || isudp)) { 861 return; --- 27 unchanged lines hidden (view full) --- 889 struct virtio_net_hdr *vhdr; 890 uint8_t offload_type; 891 892 if (net_rx_pkt_is_vlan_stripped(pkt)) { 893 rxcd->ts = 1; 894 rxcd->tci = net_rx_pkt_get_vlan_tag(pkt); 895 } 896 |
901 if (!net_rx_pkt_has_virt_hdr(pkt)) { 902 goto nocsum; 903 } 904 | |
905 vhdr = net_rx_pkt_get_vhdr(pkt); 906 /* 907 * Checksum is valid when lower level tell so or when lower level 908 * requires checksum offload telling that packet produced/bridged 909 * locally and did travel over network after last checksum calculation 910 * or production 911 */ 912 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) || --- 604 unchanged lines hidden (view full) --- 1517 VMXNET3_WRITE_TX_QUEUE_DESCR32(d, qdescr_pa, 1518 ctrl.txThreshold, 1519 VMXNET3_DEF_TX_THRESHOLD); 1520 } 1521 1522 /* Preallocate TX packet wrapper */ 1523 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags); 1524 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), s->max_tx_frags); | 897 vhdr = net_rx_pkt_get_vhdr(pkt); 898 /* 899 * Checksum is valid when lower level tell so or when lower level 900 * requires checksum offload telling that packet produced/bridged 901 * locally and did travel over network after last checksum calculation 902 * or production 903 */ 904 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) || --- 604 unchanged lines hidden (view full) --- 1509 VMXNET3_WRITE_TX_QUEUE_DESCR32(d, qdescr_pa, 1510 ctrl.txThreshold, 1511 VMXNET3_DEF_TX_THRESHOLD); 1512 } 1513 1514 /* Preallocate TX packet wrapper */ 1515 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags); 1516 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), s->max_tx_frags); |
1525 net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr); | 1517 net_rx_pkt_init(&s->rx_pkt); |
1526 1527 /* Read rings memory locations for RX queues */ 1528 for (i = 0; i < s->rxq_num; i++) { 1529 int j; 1530 hwaddr qd_pa = 1531 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) + 1532 i * sizeof(struct Vmxnet3_RxQueueDesc); 1533 --- 863 unchanged lines hidden (view full) --- 2397 } 2398}; 2399 2400static int vmxnet3_post_load(void *opaque, int version_id) 2401{ 2402 VMXNET3State *s = opaque; 2403 2404 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), s->max_tx_frags); | 1518 1519 /* Read rings memory locations for RX queues */ 1520 for (i = 0; i < s->rxq_num; i++) { 1521 int j; 1522 hwaddr qd_pa = 1523 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) + 1524 i * sizeof(struct Vmxnet3_RxQueueDesc); 1525 --- 863 unchanged lines hidden (view full) --- 2389 } 2390}; 2391 2392static int vmxnet3_post_load(void *opaque, int version_id) 2393{ 2394 VMXNET3State *s = opaque; 2395 2396 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), s->max_tx_frags); |
2405 net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr); | 2397 net_rx_pkt_init(&s->rx_pkt); |
2406 2407 if (s->msix_used) { 2408 vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS); 2409 } 2410 2411 if (!vmxnet3_validate_queues(s)) { 2412 return -1; 2413 } --- 131 unchanged lines hidden --- | 2398 2399 if (s->msix_used) { 2400 vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS); 2401 } 2402 2403 if (!vmxnet3_validate_queues(s)) { 2404 return -1; 2405 } --- 131 unchanged lines hidden --- |