1 /* 2 * QEMU VMWARE VMXNET3 paravirtual NIC 3 * 4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) 5 * 6 * Developed by Daynix Computing LTD (http://www.daynix.com) 7 * 8 * Authors: 9 * Dmitry Fleytman <dmitry@daynix.com> 10 * Tamir Shomer <tamirs@daynix.com> 11 * Yan Vugenfirer <yan@daynix.com> 12 * 13 * This work is licensed under the terms of the GNU GPL, version 2. 14 * See the COPYING file in the top-level directory. 15 * 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/hw.h" 20 #include "hw/pci/pci.h" 21 #include "hw/qdev-properties.h" 22 #include "net/tap.h" 23 #include "net/checksum.h" 24 #include "sysemu/sysemu.h" 25 #include "qemu/bswap.h" 26 #include "qemu/log.h" 27 #include "qemu/module.h" 28 #include "hw/pci/msix.h" 29 #include "hw/pci/msi.h" 30 #include "migration/register.h" 31 #include "migration/vmstate.h" 32 33 #include "vmxnet3.h" 34 #include "vmxnet3_defs.h" 35 #include "vmxnet_debug.h" 36 #include "vmware_utils.h" 37 #include "net_tx_pkt.h" 38 #include "net_rx_pkt.h" 39 #include "qom/object.h" 40 41 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1 42 #define VMXNET3_MSIX_BAR_SIZE 0x2000 43 #define MIN_BUF_SIZE 60 44 45 /* Compatibility flags for migration */ 46 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0 47 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \ 48 (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT) 49 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1 50 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \ 51 (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT) 52 53 #define VMXNET3_EXP_EP_OFFSET (0x48) 54 #define VMXNET3_MSI_OFFSET(s) \ 55 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84) 56 #define VMXNET3_MSIX_OFFSET(s) \ 57 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c) 58 #define VMXNET3_DSN_OFFSET (0x100) 59 60 #define VMXNET3_BAR0_IDX (0) 61 #define VMXNET3_BAR1_IDX (1) 62 #define VMXNET3_MSIX_BAR_IDX (2) 63 64 #define VMXNET3_OFF_MSIX_TABLE (0x000) 65 #define VMXNET3_OFF_MSIX_PBA(s) \ 66 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000) 67 68 /* Link speed in Mbps should be shifted by 16 */ 69 #define VMXNET3_LINK_SPEED (1000 << 16) 70 71 /* Link status: 1 - up, 0 - down. */ 72 #define VMXNET3_LINK_STATUS_UP 0x1 73 74 /* Least significant bit should be set for revision and version */ 75 #define VMXNET3_UPT_REVISION 0x1 76 #define VMXNET3_DEVICE_REVISION 0x1 77 78 /* Number of interrupt vectors for non-MSIx modes */ 79 #define VMXNET3_MAX_NMSIX_INTRS (1) 80 81 /* Macros for rings descriptors access */ 82 #define VMXNET3_READ_TX_QUEUE_DESCR8(_d, dpa, field) \ 83 (vmw_shmem_ld8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 84 85 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(_d, dpa, field, value) \ 86 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value))) 87 88 #define VMXNET3_READ_TX_QUEUE_DESCR32(_d, dpa, field) \ 89 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 90 91 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(_d, dpa, field, value) \ 92 (vmw_shmem_st32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value)) 93 94 #define VMXNET3_READ_TX_QUEUE_DESCR64(_d, dpa, field) \ 95 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 96 97 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(_d, dpa, field, value) \ 98 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value)) 99 100 #define VMXNET3_READ_RX_QUEUE_DESCR64(_d, dpa, field) \ 101 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field))) 102 103 #define VMXNET3_READ_RX_QUEUE_DESCR32(_d, dpa, field) \ 104 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field))) 105 106 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(_d, dpa, field, value) \ 107 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value)) 108 109 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(_d, dpa, field, value) \ 110 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value)) 111 112 /* Macros for guest driver shared area access */ 113 #define VMXNET3_READ_DRV_SHARED64(_d, shpa, field) \ 114 (vmw_shmem_ld64(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 115 116 #define VMXNET3_READ_DRV_SHARED32(_d, shpa, field) \ 117 (vmw_shmem_ld32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 118 119 #define VMXNET3_WRITE_DRV_SHARED32(_d, shpa, field, val) \ 120 (vmw_shmem_st32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), val)) 121 122 #define VMXNET3_READ_DRV_SHARED16(_d, shpa, field) \ 123 (vmw_shmem_ld16(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 124 125 #define VMXNET3_READ_DRV_SHARED8(_d, shpa, field) \ 126 (vmw_shmem_ld8(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 127 128 #define VMXNET3_READ_DRV_SHARED(_d, shpa, field, b, l) \ 129 (vmw_shmem_read(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l)) 130 131 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag)) 132 133 struct VMXNET3Class { 134 PCIDeviceClass parent_class; 135 DeviceRealize parent_dc_realize; 136 }; 137 typedef struct VMXNET3Class VMXNET3Class; 138 139 DECLARE_CLASS_CHECKERS(VMXNET3Class, VMXNET3_DEVICE, 140 TYPE_VMXNET3) 141 142 static inline void vmxnet3_ring_init(PCIDevice *d, 143 Vmxnet3Ring *ring, 144 hwaddr pa, 145 uint32_t size, 146 uint32_t cell_size, 147 bool zero_region) 148 { 149 ring->pa = pa; 150 ring->size = size; 151 ring->cell_size = cell_size; 152 ring->gen = VMXNET3_INIT_GEN; 153 ring->next = 0; 154 155 if (zero_region) { 156 vmw_shmem_set(d, pa, 0, size * cell_size); 157 } 158 } 159 160 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \ 161 macro("%s#%d: base %" PRIx64 " size %u cell_size %u gen %d next %u", \ 162 (ring_name), (ridx), \ 163 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next) 164 165 static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring) 166 { 167 if (++ring->next >= ring->size) { 168 ring->next = 0; 169 ring->gen ^= 1; 170 } 171 } 172 173 static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring) 174 { 175 if (ring->next-- == 0) { 176 ring->next = ring->size - 1; 177 ring->gen ^= 1; 178 } 179 } 180 181 static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring) 182 { 183 return ring->pa + ring->next * ring->cell_size; 184 } 185 186 static inline void vmxnet3_ring_read_curr_cell(PCIDevice *d, Vmxnet3Ring *ring, 187 void *buff) 188 { 189 vmw_shmem_read(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size); 190 } 191 192 static inline void vmxnet3_ring_write_curr_cell(PCIDevice *d, Vmxnet3Ring *ring, 193 void *buff) 194 { 195 vmw_shmem_write(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size); 196 } 197 198 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring) 199 { 200 return ring->next; 201 } 202 203 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring) 204 { 205 return ring->gen; 206 } 207 208 /* Debug trace-related functions */ 209 static inline void 210 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr) 211 { 212 VMW_PKPRN("TX DESCR: " 213 "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, " 214 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, " 215 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d", 216 descr->addr, descr->len, descr->gen, descr->rsvd, 217 descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om, 218 descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci); 219 } 220 221 static inline void 222 vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr) 223 { 224 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, " 225 "csum_start: %d, csum_offset: %d", 226 vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size, 227 vhdr->csum_start, vhdr->csum_offset); 228 } 229 230 static inline void 231 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr) 232 { 233 VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, " 234 "dtype: %d, ext1: %d, btype: %d", 235 descr->addr, descr->len, descr->gen, 236 descr->rsvd, descr->dtype, descr->ext1, descr->btype); 237 } 238 239 /* Interrupt management */ 240 241 /* 242 * This function returns sign whether interrupt line is in asserted state 243 * This depends on the type of interrupt used. For INTX interrupt line will 244 * be asserted until explicit deassertion, for MSI(X) interrupt line will 245 * be deasserted automatically due to notification semantics of the MSI(X) 246 * interrupts 247 */ 248 static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx) 249 { 250 PCIDevice *d = PCI_DEVICE(s); 251 252 if (s->msix_used && msix_enabled(d)) { 253 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx); 254 msix_notify(d, int_idx); 255 return false; 256 } 257 if (msi_enabled(d)) { 258 VMW_IRPRN("Sending MSI notification for vector %u", int_idx); 259 msi_notify(d, int_idx); 260 return false; 261 } 262 263 VMW_IRPRN("Asserting line for interrupt %u", int_idx); 264 pci_irq_assert(d); 265 return true; 266 } 267 268 static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx) 269 { 270 PCIDevice *d = PCI_DEVICE(s); 271 272 /* 273 * This function should never be called for MSI(X) interrupts 274 * because deassertion never required for message interrupts 275 */ 276 assert(!s->msix_used || !msix_enabled(d)); 277 /* 278 * This function should never be called for MSI(X) interrupts 279 * because deassertion never required for message interrupts 280 */ 281 assert(!msi_enabled(d)); 282 283 VMW_IRPRN("Deasserting line for interrupt %u", lidx); 284 pci_irq_deassert(d); 285 } 286 287 static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx) 288 { 289 if (!s->interrupt_states[lidx].is_pending && 290 s->interrupt_states[lidx].is_asserted) { 291 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx); 292 _vmxnet3_deassert_interrupt_line(s, lidx); 293 s->interrupt_states[lidx].is_asserted = false; 294 return; 295 } 296 297 if (s->interrupt_states[lidx].is_pending && 298 !s->interrupt_states[lidx].is_masked && 299 !s->interrupt_states[lidx].is_asserted) { 300 VMW_IRPRN("New interrupt line state for index %d is UP", lidx); 301 s->interrupt_states[lidx].is_asserted = 302 _vmxnet3_assert_interrupt_line(s, lidx); 303 s->interrupt_states[lidx].is_pending = false; 304 return; 305 } 306 } 307 308 static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx) 309 { 310 PCIDevice *d = PCI_DEVICE(s); 311 s->interrupt_states[lidx].is_pending = true; 312 vmxnet3_update_interrupt_line_state(s, lidx); 313 314 if (s->msix_used && msix_enabled(d) && s->auto_int_masking) { 315 goto do_automask; 316 } 317 318 if (msi_enabled(d) && s->auto_int_masking) { 319 goto do_automask; 320 } 321 322 return; 323 324 do_automask: 325 s->interrupt_states[lidx].is_masked = true; 326 vmxnet3_update_interrupt_line_state(s, lidx); 327 } 328 329 static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx) 330 { 331 return s->interrupt_states[lidx].is_asserted; 332 } 333 334 static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx) 335 { 336 s->interrupt_states[int_idx].is_pending = false; 337 if (s->auto_int_masking) { 338 s->interrupt_states[int_idx].is_masked = true; 339 } 340 vmxnet3_update_interrupt_line_state(s, int_idx); 341 } 342 343 static void 344 vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked) 345 { 346 s->interrupt_states[lidx].is_masked = is_masked; 347 vmxnet3_update_interrupt_line_state(s, lidx); 348 } 349 350 static bool vmxnet3_verify_driver_magic(PCIDevice *d, hwaddr dshmem) 351 { 352 return (VMXNET3_READ_DRV_SHARED32(d, dshmem, magic) == VMXNET3_REV1_MAGIC); 353 } 354 355 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF) 356 #define VMXNET3_MAKE_BYTE(byte_num, val) \ 357 (((uint32_t)((val) & 0xFF)) << (byte_num)*8) 358 359 static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l) 360 { 361 s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0); 362 s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1); 363 s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2); 364 s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3); 365 s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0); 366 s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1); 367 368 VMW_CFPRN("Variable MAC: " MAC_FMT, MAC_ARG(s->conf.macaddr.a)); 369 370 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 371 } 372 373 static uint64_t vmxnet3_get_mac_low(MACAddr *addr) 374 { 375 return VMXNET3_MAKE_BYTE(0, addr->a[0]) | 376 VMXNET3_MAKE_BYTE(1, addr->a[1]) | 377 VMXNET3_MAKE_BYTE(2, addr->a[2]) | 378 VMXNET3_MAKE_BYTE(3, addr->a[3]); 379 } 380 381 static uint64_t vmxnet3_get_mac_high(MACAddr *addr) 382 { 383 return VMXNET3_MAKE_BYTE(0, addr->a[4]) | 384 VMXNET3_MAKE_BYTE(1, addr->a[5]); 385 } 386 387 static void 388 vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx) 389 { 390 vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring); 391 } 392 393 static inline void 394 vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx) 395 { 396 vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]); 397 } 398 399 static inline void 400 vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx) 401 { 402 vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring); 403 } 404 405 static void 406 vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx) 407 { 408 vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring); 409 } 410 411 static void 412 vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx) 413 { 414 vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring); 415 } 416 417 static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32_t tx_ridx) 418 { 419 struct Vmxnet3_TxCompDesc txcq_descr; 420 PCIDevice *d = PCI_DEVICE(s); 421 422 VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring); 423 424 memset(&txcq_descr, 0, sizeof(txcq_descr)); 425 txcq_descr.txdIdx = tx_ridx; 426 txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring); 427 txcq_descr.val1 = cpu_to_le32(txcq_descr.val1); 428 txcq_descr.val2 = cpu_to_le32(txcq_descr.val2); 429 vmxnet3_ring_write_curr_cell(d, &s->txq_descr[qidx].comp_ring, &txcq_descr); 430 431 /* Flush changes in TX descriptor before changing the counter value */ 432 smp_wmb(); 433 434 vmxnet3_inc_tx_completion_counter(s, qidx); 435 vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx); 436 } 437 438 static bool 439 vmxnet3_setup_tx_offloads(VMXNET3State *s) 440 { 441 switch (s->offload_mode) { 442 case VMXNET3_OM_NONE: 443 return net_tx_pkt_build_vheader(s->tx_pkt, false, false, 0); 444 445 case VMXNET3_OM_CSUM: 446 VMW_PKPRN("L4 CSO requested\n"); 447 return net_tx_pkt_build_vheader(s->tx_pkt, false, true, 0); 448 449 case VMXNET3_OM_TSO: 450 VMW_PKPRN("GSO offload requested."); 451 if (!net_tx_pkt_build_vheader(s->tx_pkt, true, true, 452 s->cso_or_gso_size)) { 453 return false; 454 } 455 net_tx_pkt_update_ip_checksums(s->tx_pkt); 456 break; 457 458 default: 459 g_assert_not_reached(); 460 return false; 461 } 462 463 return true; 464 } 465 466 static void 467 vmxnet3_tx_retrieve_metadata(VMXNET3State *s, 468 const struct Vmxnet3_TxDesc *txd) 469 { 470 s->offload_mode = txd->om; 471 s->cso_or_gso_size = txd->msscof; 472 s->tci = txd->tci; 473 s->needs_vlan = txd->ti; 474 } 475 476 typedef enum { 477 VMXNET3_PKT_STATUS_OK, 478 VMXNET3_PKT_STATUS_ERROR, 479 VMXNET3_PKT_STATUS_DISCARD,/* only for tx */ 480 VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */ 481 } Vmxnet3PktStatus; 482 483 static void 484 vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx, 485 Vmxnet3PktStatus status) 486 { 487 size_t tot_len = net_tx_pkt_get_total_len(s->tx_pkt); 488 struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats; 489 490 switch (status) { 491 case VMXNET3_PKT_STATUS_OK: 492 switch (net_tx_pkt_get_packet_type(s->tx_pkt)) { 493 case ETH_PKT_BCAST: 494 stats->bcastPktsTxOK++; 495 stats->bcastBytesTxOK += tot_len; 496 break; 497 case ETH_PKT_MCAST: 498 stats->mcastPktsTxOK++; 499 stats->mcastBytesTxOK += tot_len; 500 break; 501 case ETH_PKT_UCAST: 502 stats->ucastPktsTxOK++; 503 stats->ucastBytesTxOK += tot_len; 504 break; 505 default: 506 g_assert_not_reached(); 507 } 508 509 if (s->offload_mode == VMXNET3_OM_TSO) { 510 /* 511 * According to VMWARE headers this statistic is a number 512 * of packets after segmentation but since we don't have 513 * this information in QEMU model, the best we can do is to 514 * provide number of non-segmented packets 515 */ 516 stats->TSOPktsTxOK++; 517 stats->TSOBytesTxOK += tot_len; 518 } 519 break; 520 521 case VMXNET3_PKT_STATUS_DISCARD: 522 stats->pktsTxDiscard++; 523 break; 524 525 case VMXNET3_PKT_STATUS_ERROR: 526 stats->pktsTxError++; 527 break; 528 529 default: 530 g_assert_not_reached(); 531 } 532 } 533 534 static void 535 vmxnet3_on_rx_done_update_stats(VMXNET3State *s, 536 int qidx, 537 Vmxnet3PktStatus status) 538 { 539 struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats; 540 size_t tot_len = net_rx_pkt_get_total_len(s->rx_pkt); 541 542 switch (status) { 543 case VMXNET3_PKT_STATUS_OUT_OF_BUF: 544 stats->pktsRxOutOfBuf++; 545 break; 546 547 case VMXNET3_PKT_STATUS_ERROR: 548 stats->pktsRxError++; 549 break; 550 case VMXNET3_PKT_STATUS_OK: 551 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) { 552 case ETH_PKT_BCAST: 553 stats->bcastPktsRxOK++; 554 stats->bcastBytesRxOK += tot_len; 555 break; 556 case ETH_PKT_MCAST: 557 stats->mcastPktsRxOK++; 558 stats->mcastBytesRxOK += tot_len; 559 break; 560 case ETH_PKT_UCAST: 561 stats->ucastPktsRxOK++; 562 stats->ucastBytesRxOK += tot_len; 563 break; 564 default: 565 g_assert_not_reached(); 566 } 567 568 if (tot_len > s->mtu) { 569 stats->LROPktsRxOK++; 570 stats->LROBytesRxOK += tot_len; 571 } 572 break; 573 default: 574 g_assert_not_reached(); 575 } 576 } 577 578 static inline void 579 vmxnet3_ring_read_curr_txdesc(PCIDevice *pcidev, Vmxnet3Ring *ring, 580 struct Vmxnet3_TxDesc *txd) 581 { 582 vmxnet3_ring_read_curr_cell(pcidev, ring, txd); 583 txd->addr = le64_to_cpu(txd->addr); 584 txd->val1 = le32_to_cpu(txd->val1); 585 txd->val2 = le32_to_cpu(txd->val2); 586 } 587 588 static inline bool 589 vmxnet3_pop_next_tx_descr(VMXNET3State *s, 590 int qidx, 591 struct Vmxnet3_TxDesc *txd, 592 uint32_t *descr_idx) 593 { 594 Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring; 595 PCIDevice *d = PCI_DEVICE(s); 596 597 vmxnet3_ring_read_curr_txdesc(d, ring, txd); 598 if (txd->gen == vmxnet3_ring_curr_gen(ring)) { 599 /* Only read after generation field verification */ 600 smp_rmb(); 601 /* Re-read to be sure we got the latest version */ 602 vmxnet3_ring_read_curr_txdesc(d, ring, txd); 603 VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring); 604 *descr_idx = vmxnet3_ring_curr_cell_idx(ring); 605 vmxnet3_inc_tx_consumption_counter(s, qidx); 606 return true; 607 } 608 609 return false; 610 } 611 612 static bool 613 vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx) 614 { 615 Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK; 616 617 if (!vmxnet3_setup_tx_offloads(s)) { 618 status = VMXNET3_PKT_STATUS_ERROR; 619 goto func_exit; 620 } 621 622 /* debug prints */ 623 vmxnet3_dump_virt_hdr(net_tx_pkt_get_vhdr(s->tx_pkt)); 624 net_tx_pkt_dump(s->tx_pkt); 625 626 if (!net_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) { 627 status = VMXNET3_PKT_STATUS_DISCARD; 628 goto func_exit; 629 } 630 631 func_exit: 632 vmxnet3_on_tx_done_update_stats(s, qidx, status); 633 return (status == VMXNET3_PKT_STATUS_OK); 634 } 635 636 static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx) 637 { 638 struct Vmxnet3_TxDesc txd; 639 uint32_t txd_idx; 640 uint32_t data_len; 641 hwaddr data_pa; 642 643 for (;;) { 644 if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) { 645 break; 646 } 647 648 vmxnet3_dump_tx_descr(&txd); 649 650 if (!s->skip_current_tx_pkt) { 651 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE; 652 data_pa = txd.addr; 653 654 if (!net_tx_pkt_add_raw_fragment(s->tx_pkt, 655 data_pa, 656 data_len)) { 657 s->skip_current_tx_pkt = true; 658 } 659 } 660 661 if (s->tx_sop) { 662 vmxnet3_tx_retrieve_metadata(s, &txd); 663 s->tx_sop = false; 664 } 665 666 if (txd.eop) { 667 if (!s->skip_current_tx_pkt && net_tx_pkt_parse(s->tx_pkt)) { 668 if (s->needs_vlan) { 669 net_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci); 670 } 671 672 vmxnet3_send_packet(s, qidx); 673 } else { 674 vmxnet3_on_tx_done_update_stats(s, qidx, 675 VMXNET3_PKT_STATUS_ERROR); 676 } 677 678 vmxnet3_complete_packet(s, qidx, txd_idx); 679 s->tx_sop = true; 680 s->skip_current_tx_pkt = false; 681 net_tx_pkt_reset(s->tx_pkt); 682 } 683 } 684 } 685 686 static inline void 687 vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx, 688 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx) 689 { 690 PCIDevice *d = PCI_DEVICE(s); 691 692 Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx]; 693 *didx = vmxnet3_ring_curr_cell_idx(ring); 694 vmxnet3_ring_read_curr_cell(d, ring, dbuf); 695 dbuf->addr = le64_to_cpu(dbuf->addr); 696 dbuf->val1 = le32_to_cpu(dbuf->val1); 697 dbuf->ext1 = le32_to_cpu(dbuf->ext1); 698 } 699 700 static inline uint8_t 701 vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx) 702 { 703 return s->rxq_descr[qidx].rx_ring[ridx].gen; 704 } 705 706 static inline hwaddr 707 vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen) 708 { 709 uint8_t ring_gen; 710 struct Vmxnet3_RxCompDesc rxcd; 711 712 hwaddr daddr = 713 vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring); 714 715 pci_dma_read(PCI_DEVICE(s), 716 daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc)); 717 rxcd.val1 = le32_to_cpu(rxcd.val1); 718 rxcd.val2 = le32_to_cpu(rxcd.val2); 719 rxcd.val3 = le32_to_cpu(rxcd.val3); 720 ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring); 721 722 if (rxcd.gen != ring_gen) { 723 *descr_gen = ring_gen; 724 vmxnet3_inc_rx_completion_counter(s, qidx); 725 return daddr; 726 } 727 728 return 0; 729 } 730 731 static inline void 732 vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx) 733 { 734 vmxnet3_dec_rx_completion_counter(s, qidx); 735 } 736 737 #define RXQ_IDX (0) 738 #define RX_HEAD_BODY_RING (0) 739 #define RX_BODY_ONLY_RING (1) 740 741 static bool 742 vmxnet3_get_next_head_rx_descr(VMXNET3State *s, 743 struct Vmxnet3_RxDesc *descr_buf, 744 uint32_t *descr_idx, 745 uint32_t *ridx) 746 { 747 for (;;) { 748 uint32_t ring_gen; 749 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, 750 descr_buf, descr_idx); 751 752 /* If no more free descriptors - return */ 753 ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING); 754 if (descr_buf->gen != ring_gen) { 755 return false; 756 } 757 758 /* Only read after generation field verification */ 759 smp_rmb(); 760 /* Re-read to be sure we got the latest version */ 761 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, 762 descr_buf, descr_idx); 763 764 /* Mark current descriptor as used/skipped */ 765 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING); 766 767 /* If this is what we are looking for - return */ 768 if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) { 769 *ridx = RX_HEAD_BODY_RING; 770 return true; 771 } 772 } 773 } 774 775 static bool 776 vmxnet3_get_next_body_rx_descr(VMXNET3State *s, 777 struct Vmxnet3_RxDesc *d, 778 uint32_t *didx, 779 uint32_t *ridx) 780 { 781 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx); 782 783 /* Try to find corresponding descriptor in head/body ring */ 784 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) { 785 /* Only read after generation field verification */ 786 smp_rmb(); 787 /* Re-read to be sure we got the latest version */ 788 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx); 789 if (d->btype == VMXNET3_RXD_BTYPE_BODY) { 790 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING); 791 *ridx = RX_HEAD_BODY_RING; 792 return true; 793 } 794 } 795 796 /* 797 * If there is no free descriptors on head/body ring or next free 798 * descriptor is a head descriptor switch to body only ring 799 */ 800 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx); 801 802 /* If no more free descriptors - return */ 803 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) { 804 /* Only read after generation field verification */ 805 smp_rmb(); 806 /* Re-read to be sure we got the latest version */ 807 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx); 808 assert(d->btype == VMXNET3_RXD_BTYPE_BODY); 809 *ridx = RX_BODY_ONLY_RING; 810 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING); 811 return true; 812 } 813 814 return false; 815 } 816 817 static inline bool 818 vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head, 819 struct Vmxnet3_RxDesc *descr_buf, 820 uint32_t *descr_idx, 821 uint32_t *ridx) 822 { 823 if (is_head || !s->rx_packets_compound) { 824 return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx); 825 } else { 826 return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx); 827 } 828 } 829 830 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID), 831 * the implementation always passes an RxCompDesc with a "Checksum 832 * calculated and found correct" to the OS (cnc=0 and tuc=1, see 833 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior. 834 * 835 * Therefore, if packet has the NEEDS_CSUM set, we must calculate 836 * and place a fully computed checksum into the tcp/udp header. 837 * Otherwise, the OS driver will receive a checksum-correct indication 838 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field 839 * having just the pseudo header csum value. 840 * 841 * While this is not a problem if packet is destined for local delivery, 842 * in the case the host OS performs forwarding, it will forward an 843 * incorrectly checksummed packet. 844 */ 845 static void vmxnet3_rx_need_csum_calculate(struct NetRxPkt *pkt, 846 const void *pkt_data, 847 size_t pkt_len) 848 { 849 struct virtio_net_hdr *vhdr; 850 bool isip4, isip6, istcp, isudp; 851 uint8_t *data; 852 int len; 853 854 vhdr = net_rx_pkt_get_vhdr(pkt); 855 if (!VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 856 return; 857 } 858 859 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 860 if (!(isip4 || isip6) || !(istcp || isudp)) { 861 return; 862 } 863 864 vmxnet3_dump_virt_hdr(vhdr); 865 866 /* Validate packet len: csum_start + scum_offset + length of csum field */ 867 if (pkt_len < (vhdr->csum_start + vhdr->csum_offset + 2)) { 868 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, " 869 "cannot calculate checksum", 870 pkt_len, vhdr->csum_start, vhdr->csum_offset); 871 return; 872 } 873 874 data = (uint8_t *)pkt_data + vhdr->csum_start; 875 len = pkt_len - vhdr->csum_start; 876 /* Put the checksum obtained into the packet */ 877 stw_be_p(data + vhdr->csum_offset, 878 net_checksum_finish_nozero(net_checksum_add(len, data))); 879 880 vhdr->flags &= ~VIRTIO_NET_HDR_F_NEEDS_CSUM; 881 vhdr->flags |= VIRTIO_NET_HDR_F_DATA_VALID; 882 } 883 884 static void vmxnet3_rx_update_descr(struct NetRxPkt *pkt, 885 struct Vmxnet3_RxCompDesc *rxcd) 886 { 887 int csum_ok, is_gso; 888 bool isip4, isip6, istcp, isudp; 889 struct virtio_net_hdr *vhdr; 890 uint8_t offload_type; 891 892 if (net_rx_pkt_is_vlan_stripped(pkt)) { 893 rxcd->ts = 1; 894 rxcd->tci = net_rx_pkt_get_vlan_tag(pkt); 895 } 896 897 vhdr = net_rx_pkt_get_vhdr(pkt); 898 /* 899 * Checksum is valid when lower level tell so or when lower level 900 * requires checksum offload telling that packet produced/bridged 901 * locally and did travel over network after last checksum calculation 902 * or production 903 */ 904 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) || 905 VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM); 906 907 offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN; 908 is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0; 909 910 if (!csum_ok && !is_gso) { 911 goto nocsum; 912 } 913 914 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 915 if ((!istcp && !isudp) || (!isip4 && !isip6)) { 916 goto nocsum; 917 } 918 919 rxcd->cnc = 0; 920 rxcd->v4 = isip4 ? 1 : 0; 921 rxcd->v6 = isip6 ? 1 : 0; 922 rxcd->tcp = istcp ? 1 : 0; 923 rxcd->udp = isudp ? 1 : 0; 924 rxcd->fcs = rxcd->tuc = rxcd->ipc = 1; 925 return; 926 927 nocsum: 928 rxcd->cnc = 1; 929 return; 930 } 931 932 static void 933 vmxnet3_pci_dma_writev(PCIDevice *pci_dev, 934 const struct iovec *iov, 935 size_t start_iov_off, 936 hwaddr target_addr, 937 size_t bytes_to_copy) 938 { 939 size_t curr_off = 0; 940 size_t copied = 0; 941 942 while (bytes_to_copy) { 943 if (start_iov_off < (curr_off + iov->iov_len)) { 944 size_t chunk_len = 945 MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy); 946 947 pci_dma_write(pci_dev, target_addr + copied, 948 iov->iov_base + start_iov_off - curr_off, 949 chunk_len); 950 951 copied += chunk_len; 952 start_iov_off += chunk_len; 953 curr_off = start_iov_off; 954 bytes_to_copy -= chunk_len; 955 } else { 956 curr_off += iov->iov_len; 957 } 958 iov++; 959 } 960 } 961 962 static void 963 vmxnet3_pci_dma_write_rxcd(PCIDevice *pcidev, dma_addr_t pa, 964 struct Vmxnet3_RxCompDesc *rxcd) 965 { 966 rxcd->val1 = cpu_to_le32(rxcd->val1); 967 rxcd->val2 = cpu_to_le32(rxcd->val2); 968 rxcd->val3 = cpu_to_le32(rxcd->val3); 969 pci_dma_write(pcidev, pa, rxcd, sizeof(*rxcd)); 970 } 971 972 static bool 973 vmxnet3_indicate_packet(VMXNET3State *s) 974 { 975 struct Vmxnet3_RxDesc rxd; 976 PCIDevice *d = PCI_DEVICE(s); 977 bool is_head = true; 978 uint32_t rxd_idx; 979 uint32_t rx_ridx = 0; 980 981 struct Vmxnet3_RxCompDesc rxcd; 982 uint32_t new_rxcd_gen = VMXNET3_INIT_GEN; 983 hwaddr new_rxcd_pa = 0; 984 hwaddr ready_rxcd_pa = 0; 985 struct iovec *data = net_rx_pkt_get_iovec(s->rx_pkt); 986 size_t bytes_copied = 0; 987 size_t bytes_left = net_rx_pkt_get_total_len(s->rx_pkt); 988 uint16_t num_frags = 0; 989 size_t chunk_size; 990 991 net_rx_pkt_dump(s->rx_pkt); 992 993 while (bytes_left > 0) { 994 995 /* cannot add more frags to packet */ 996 if (num_frags == s->max_rx_frags) { 997 break; 998 } 999 1000 new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen); 1001 if (!new_rxcd_pa) { 1002 break; 1003 } 1004 1005 if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) { 1006 break; 1007 } 1008 1009 chunk_size = MIN(bytes_left, rxd.len); 1010 vmxnet3_pci_dma_writev(d, data, bytes_copied, rxd.addr, chunk_size); 1011 bytes_copied += chunk_size; 1012 bytes_left -= chunk_size; 1013 1014 vmxnet3_dump_rx_descr(&rxd); 1015 1016 if (ready_rxcd_pa != 0) { 1017 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd); 1018 } 1019 1020 memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc)); 1021 rxcd.rxdIdx = rxd_idx; 1022 rxcd.len = chunk_size; 1023 rxcd.sop = is_head; 1024 rxcd.gen = new_rxcd_gen; 1025 rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num; 1026 1027 if (bytes_left == 0) { 1028 vmxnet3_rx_update_descr(s->rx_pkt, &rxcd); 1029 } 1030 1031 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu " 1032 "sop %d csum_correct %lu", 1033 (unsigned long) rx_ridx, 1034 (unsigned long) rxcd.rxdIdx, 1035 (unsigned long) rxcd.len, 1036 (int) rxcd.sop, 1037 (unsigned long) rxcd.tuc); 1038 1039 is_head = false; 1040 ready_rxcd_pa = new_rxcd_pa; 1041 new_rxcd_pa = 0; 1042 num_frags++; 1043 } 1044 1045 if (ready_rxcd_pa != 0) { 1046 rxcd.eop = 1; 1047 rxcd.err = (bytes_left != 0); 1048 1049 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd); 1050 1051 /* Flush RX descriptor changes */ 1052 smp_wmb(); 1053 } 1054 1055 if (new_rxcd_pa != 0) { 1056 vmxnet3_revert_rxc_descr(s, RXQ_IDX); 1057 } 1058 1059 vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx); 1060 1061 if (bytes_left == 0) { 1062 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK); 1063 return true; 1064 } else if (num_frags == s->max_rx_frags) { 1065 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR); 1066 return false; 1067 } else { 1068 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, 1069 VMXNET3_PKT_STATUS_OUT_OF_BUF); 1070 return false; 1071 } 1072 } 1073 1074 static void 1075 vmxnet3_io_bar0_write(void *opaque, hwaddr addr, 1076 uint64_t val, unsigned size) 1077 { 1078 VMXNET3State *s = opaque; 1079 1080 if (!s->device_active) { 1081 return; 1082 } 1083 1084 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD, 1085 VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) { 1086 int tx_queue_idx = 1087 VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD, 1088 VMXNET3_REG_ALIGN); 1089 if (tx_queue_idx <= s->txq_num) { 1090 vmxnet3_process_tx_queue(s, tx_queue_idx); 1091 } else { 1092 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Illegal TX queue %d/%d\n", 1093 tx_queue_idx, s->txq_num); 1094 } 1095 return; 1096 } 1097 1098 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR, 1099 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) { 1100 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR, 1101 VMXNET3_REG_ALIGN); 1102 1103 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val); 1104 1105 vmxnet3_on_interrupt_mask_changed(s, l, val); 1106 return; 1107 } 1108 1109 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD, 1110 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) || 1111 VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2, 1112 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) { 1113 return; 1114 } 1115 1116 VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d", 1117 (uint64_t) addr, val, size); 1118 } 1119 1120 static uint64_t 1121 vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size) 1122 { 1123 VMXNET3State *s = opaque; 1124 1125 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR, 1126 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) { 1127 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR, 1128 VMXNET3_REG_ALIGN); 1129 return s->interrupt_states[l].is_masked; 1130 } 1131 1132 VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size); 1133 return 0; 1134 } 1135 1136 static void vmxnet3_reset_interrupt_states(VMXNET3State *s) 1137 { 1138 int i; 1139 for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) { 1140 s->interrupt_states[i].is_asserted = false; 1141 s->interrupt_states[i].is_pending = false; 1142 s->interrupt_states[i].is_masked = true; 1143 } 1144 } 1145 1146 static void vmxnet3_reset_mac(VMXNET3State *s) 1147 { 1148 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a)); 1149 VMW_CFPRN("MAC address set to: " MAC_FMT, MAC_ARG(s->conf.macaddr.a)); 1150 } 1151 1152 static void vmxnet3_deactivate_device(VMXNET3State *s) 1153 { 1154 if (s->device_active) { 1155 VMW_CBPRN("Deactivating vmxnet3..."); 1156 net_tx_pkt_reset(s->tx_pkt); 1157 net_tx_pkt_uninit(s->tx_pkt); 1158 net_rx_pkt_uninit(s->rx_pkt); 1159 s->device_active = false; 1160 } 1161 } 1162 1163 static void vmxnet3_reset(VMXNET3State *s) 1164 { 1165 VMW_CBPRN("Resetting vmxnet3..."); 1166 1167 vmxnet3_deactivate_device(s); 1168 vmxnet3_reset_interrupt_states(s); 1169 s->drv_shmem = 0; 1170 s->tx_sop = true; 1171 s->skip_current_tx_pkt = false; 1172 } 1173 1174 static void vmxnet3_update_rx_mode(VMXNET3State *s) 1175 { 1176 PCIDevice *d = PCI_DEVICE(s); 1177 1178 s->rx_mode = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, 1179 devRead.rxFilterConf.rxMode); 1180 VMW_CFPRN("RX mode: 0x%08X", s->rx_mode); 1181 } 1182 1183 static void vmxnet3_update_vlan_filters(VMXNET3State *s) 1184 { 1185 int i; 1186 PCIDevice *d = PCI_DEVICE(s); 1187 1188 /* Copy configuration from shared memory */ 1189 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem, 1190 devRead.rxFilterConf.vfTable, 1191 s->vlan_table, 1192 sizeof(s->vlan_table)); 1193 1194 /* Invert byte order when needed */ 1195 for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) { 1196 s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]); 1197 } 1198 1199 /* Dump configuration for debugging purposes */ 1200 VMW_CFPRN("Configured VLANs:"); 1201 for (i = 0; i < sizeof(s->vlan_table) * 8; i++) { 1202 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) { 1203 VMW_CFPRN("\tVLAN %d is present", i); 1204 } 1205 } 1206 } 1207 1208 static void vmxnet3_update_mcast_filters(VMXNET3State *s) 1209 { 1210 PCIDevice *d = PCI_DEVICE(s); 1211 1212 uint16_t list_bytes = 1213 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem, 1214 devRead.rxFilterConf.mfTableLen); 1215 1216 s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]); 1217 1218 s->mcast_list = g_realloc(s->mcast_list, list_bytes); 1219 if (!s->mcast_list) { 1220 if (s->mcast_list_len == 0) { 1221 VMW_CFPRN("Current multicast list is empty"); 1222 } else { 1223 VMW_ERPRN("Failed to allocate multicast list of %d elements", 1224 s->mcast_list_len); 1225 } 1226 s->mcast_list_len = 0; 1227 } else { 1228 int i; 1229 hwaddr mcast_list_pa = 1230 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, 1231 devRead.rxFilterConf.mfTablePA); 1232 1233 pci_dma_read(d, mcast_list_pa, s->mcast_list, list_bytes); 1234 1235 VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len); 1236 for (i = 0; i < s->mcast_list_len; i++) { 1237 VMW_CFPRN("\t" MAC_FMT, MAC_ARG(s->mcast_list[i].a)); 1238 } 1239 } 1240 } 1241 1242 static void vmxnet3_setup_rx_filtering(VMXNET3State *s) 1243 { 1244 vmxnet3_update_rx_mode(s); 1245 vmxnet3_update_vlan_filters(s); 1246 vmxnet3_update_mcast_filters(s); 1247 } 1248 1249 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s) 1250 { 1251 uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2); 1252 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode); 1253 return interrupt_mode; 1254 } 1255 1256 static void vmxnet3_fill_stats(VMXNET3State *s) 1257 { 1258 int i; 1259 PCIDevice *d = PCI_DEVICE(s); 1260 1261 if (!s->device_active) 1262 return; 1263 1264 for (i = 0; i < s->txq_num; i++) { 1265 pci_dma_write(d, 1266 s->txq_descr[i].tx_stats_pa, 1267 &s->txq_descr[i].txq_stats, 1268 sizeof(s->txq_descr[i].txq_stats)); 1269 } 1270 1271 for (i = 0; i < s->rxq_num; i++) { 1272 pci_dma_write(d, 1273 s->rxq_descr[i].rx_stats_pa, 1274 &s->rxq_descr[i].rxq_stats, 1275 sizeof(s->rxq_descr[i].rxq_stats)); 1276 } 1277 } 1278 1279 static void vmxnet3_adjust_by_guest_type(VMXNET3State *s) 1280 { 1281 struct Vmxnet3_GOSInfo gos; 1282 PCIDevice *d = PCI_DEVICE(s); 1283 1284 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem, devRead.misc.driverInfo.gos, 1285 &gos, sizeof(gos)); 1286 s->rx_packets_compound = 1287 (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true; 1288 1289 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound); 1290 } 1291 1292 static void 1293 vmxnet3_dump_conf_descr(const char *name, 1294 struct Vmxnet3_VariableLenConfDesc *pm_descr) 1295 { 1296 VMW_CFPRN("%s descriptor dump: Version %u, Length %u", 1297 name, pm_descr->confVer, pm_descr->confLen); 1298 1299 }; 1300 1301 static void vmxnet3_update_pm_state(VMXNET3State *s) 1302 { 1303 struct Vmxnet3_VariableLenConfDesc pm_descr; 1304 PCIDevice *d = PCI_DEVICE(s); 1305 1306 pm_descr.confLen = 1307 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confLen); 1308 pm_descr.confVer = 1309 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confVer); 1310 pm_descr.confPA = 1311 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.pmConfDesc.confPA); 1312 1313 vmxnet3_dump_conf_descr("PM State", &pm_descr); 1314 } 1315 1316 static void vmxnet3_update_features(VMXNET3State *s) 1317 { 1318 uint32_t guest_features; 1319 int rxcso_supported; 1320 PCIDevice *d = PCI_DEVICE(s); 1321 1322 guest_features = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, 1323 devRead.misc.uptFeatures); 1324 1325 rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM); 1326 s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN); 1327 s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO); 1328 1329 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d", 1330 s->lro_supported, rxcso_supported, 1331 s->rx_vlan_stripping); 1332 if (s->peer_has_vhdr) { 1333 qemu_set_offload(qemu_get_queue(s->nic)->peer, 1334 rxcso_supported, 1335 s->lro_supported, 1336 s->lro_supported, 1337 0, 1338 0); 1339 } 1340 } 1341 1342 static bool vmxnet3_verify_intx(VMXNET3State *s, int intx) 1343 { 1344 return s->msix_used || msi_enabled(PCI_DEVICE(s)) 1345 || intx == pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1; 1346 } 1347 1348 static void vmxnet3_validate_interrupt_idx(bool is_msix, int idx) 1349 { 1350 int max_ints = is_msix ? VMXNET3_MAX_INTRS : VMXNET3_MAX_NMSIX_INTRS; 1351 if (idx >= max_ints) { 1352 hw_error("Bad interrupt index: %d\n", idx); 1353 } 1354 } 1355 1356 static void vmxnet3_validate_interrupts(VMXNET3State *s) 1357 { 1358 int i; 1359 1360 VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx); 1361 vmxnet3_validate_interrupt_idx(s->msix_used, s->event_int_idx); 1362 1363 for (i = 0; i < s->txq_num; i++) { 1364 int idx = s->txq_descr[i].intr_idx; 1365 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx); 1366 vmxnet3_validate_interrupt_idx(s->msix_used, idx); 1367 } 1368 1369 for (i = 0; i < s->rxq_num; i++) { 1370 int idx = s->rxq_descr[i].intr_idx; 1371 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx); 1372 vmxnet3_validate_interrupt_idx(s->msix_used, idx); 1373 } 1374 } 1375 1376 static bool vmxnet3_validate_queues(VMXNET3State *s) 1377 { 1378 /* 1379 * txq_num and rxq_num are total number of queues 1380 * configured by guest. These numbers must not 1381 * exceed corresponding maximal values. 1382 */ 1383 1384 if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) { 1385 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Bad TX queues number: %d\n", 1386 s->txq_num); 1387 return false; 1388 } 1389 1390 if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) { 1391 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Bad RX queues number: %d\n", 1392 s->rxq_num); 1393 return false; 1394 } 1395 1396 return true; 1397 } 1398 1399 static void vmxnet3_activate_device(VMXNET3State *s) 1400 { 1401 int i; 1402 static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1; 1403 PCIDevice *d = PCI_DEVICE(s); 1404 hwaddr qdescr_table_pa; 1405 uint64_t pa; 1406 uint32_t size; 1407 1408 /* Verify configuration consistency */ 1409 if (!vmxnet3_verify_driver_magic(d, s->drv_shmem)) { 1410 VMW_ERPRN("Device configuration received from driver is invalid"); 1411 return; 1412 } 1413 1414 /* Verify if device is active */ 1415 if (s->device_active) { 1416 VMW_CFPRN("Vmxnet3 device is active"); 1417 return; 1418 } 1419 1420 s->txq_num = 1421 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numTxQueues); 1422 s->rxq_num = 1423 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numRxQueues); 1424 1425 VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num); 1426 if (!vmxnet3_validate_queues(s)) { 1427 return; 1428 } 1429 1430 vmxnet3_adjust_by_guest_type(s); 1431 vmxnet3_update_features(s); 1432 vmxnet3_update_pm_state(s); 1433 vmxnet3_setup_rx_filtering(s); 1434 /* Cache fields from shared memory */ 1435 s->mtu = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.misc.mtu); 1436 assert(VMXNET3_MIN_MTU <= s->mtu && s->mtu <= VMXNET3_MAX_MTU); 1437 VMW_CFPRN("MTU is %u", s->mtu); 1438 1439 s->max_rx_frags = 1440 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem, devRead.misc.maxNumRxSG); 1441 1442 if (s->max_rx_frags == 0) { 1443 s->max_rx_frags = 1; 1444 } 1445 1446 VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags); 1447 1448 s->event_int_idx = 1449 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.eventIntrIdx); 1450 assert(vmxnet3_verify_intx(s, s->event_int_idx)); 1451 VMW_CFPRN("Events interrupt line is %u", s->event_int_idx); 1452 1453 s->auto_int_masking = 1454 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.autoMask); 1455 VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking); 1456 1457 qdescr_table_pa = 1458 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.misc.queueDescPA); 1459 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa); 1460 1461 /* 1462 * Worst-case scenario is a packet that holds all TX rings space so 1463 * we calculate total size of all TX rings for max TX fragments number 1464 */ 1465 s->max_tx_frags = 0; 1466 1467 /* TX queues */ 1468 for (i = 0; i < s->txq_num; i++) { 1469 hwaddr qdescr_pa = 1470 qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc); 1471 1472 /* Read interrupt number for this TX queue */ 1473 s->txq_descr[i].intr_idx = 1474 VMXNET3_READ_TX_QUEUE_DESCR8(d, qdescr_pa, conf.intrIdx); 1475 assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx)); 1476 1477 VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx); 1478 1479 /* Read rings memory locations for TX queues */ 1480 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.txRingBasePA); 1481 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.txRingSize); 1482 if (size > VMXNET3_TX_RING_MAX_SIZE) { 1483 size = VMXNET3_TX_RING_MAX_SIZE; 1484 } 1485 1486 vmxnet3_ring_init(d, &s->txq_descr[i].tx_ring, pa, size, 1487 sizeof(struct Vmxnet3_TxDesc), false); 1488 VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring); 1489 1490 s->max_tx_frags += size; 1491 1492 /* TXC ring */ 1493 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.compRingBasePA); 1494 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.compRingSize); 1495 if (size > VMXNET3_TC_RING_MAX_SIZE) { 1496 size = VMXNET3_TC_RING_MAX_SIZE; 1497 } 1498 vmxnet3_ring_init(d, &s->txq_descr[i].comp_ring, pa, size, 1499 sizeof(struct Vmxnet3_TxCompDesc), true); 1500 VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring); 1501 1502 s->txq_descr[i].tx_stats_pa = 1503 qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats); 1504 1505 memset(&s->txq_descr[i].txq_stats, 0, 1506 sizeof(s->txq_descr[i].txq_stats)); 1507 1508 /* Fill device-managed parameters for queues */ 1509 VMXNET3_WRITE_TX_QUEUE_DESCR32(d, qdescr_pa, 1510 ctrl.txThreshold, 1511 VMXNET3_DEF_TX_THRESHOLD); 1512 } 1513 1514 /* Preallocate TX packet wrapper */ 1515 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags); 1516 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), s->max_tx_frags); 1517 net_rx_pkt_init(&s->rx_pkt); 1518 1519 /* Read rings memory locations for RX queues */ 1520 for (i = 0; i < s->rxq_num; i++) { 1521 int j; 1522 hwaddr qd_pa = 1523 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) + 1524 i * sizeof(struct Vmxnet3_RxQueueDesc); 1525 1526 /* Read interrupt number for this RX queue */ 1527 s->rxq_descr[i].intr_idx = 1528 VMXNET3_READ_TX_QUEUE_DESCR8(d, qd_pa, conf.intrIdx); 1529 assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx)); 1530 1531 VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx); 1532 1533 /* Read rings memory locations */ 1534 for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) { 1535 /* RX rings */ 1536 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.rxRingBasePA[j]); 1537 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.rxRingSize[j]); 1538 if (size > VMXNET3_RX_RING_MAX_SIZE) { 1539 size = VMXNET3_RX_RING_MAX_SIZE; 1540 } 1541 vmxnet3_ring_init(d, &s->rxq_descr[i].rx_ring[j], pa, size, 1542 sizeof(struct Vmxnet3_RxDesc), false); 1543 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d", 1544 i, j, pa, size); 1545 } 1546 1547 /* RXC ring */ 1548 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.compRingBasePA); 1549 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.compRingSize); 1550 if (size > VMXNET3_RC_RING_MAX_SIZE) { 1551 size = VMXNET3_RC_RING_MAX_SIZE; 1552 } 1553 vmxnet3_ring_init(d, &s->rxq_descr[i].comp_ring, pa, size, 1554 sizeof(struct Vmxnet3_RxCompDesc), true); 1555 VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size); 1556 1557 s->rxq_descr[i].rx_stats_pa = 1558 qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats); 1559 memset(&s->rxq_descr[i].rxq_stats, 0, 1560 sizeof(s->rxq_descr[i].rxq_stats)); 1561 } 1562 1563 vmxnet3_validate_interrupts(s); 1564 1565 /* Make sure everything is in place before device activation */ 1566 smp_wmb(); 1567 1568 vmxnet3_reset_mac(s); 1569 1570 s->device_active = true; 1571 } 1572 1573 static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd) 1574 { 1575 s->last_command = cmd; 1576 1577 switch (cmd) { 1578 case VMXNET3_CMD_GET_PERM_MAC_HI: 1579 VMW_CBPRN("Set: Get upper part of permanent MAC"); 1580 break; 1581 1582 case VMXNET3_CMD_GET_PERM_MAC_LO: 1583 VMW_CBPRN("Set: Get lower part of permanent MAC"); 1584 break; 1585 1586 case VMXNET3_CMD_GET_STATS: 1587 VMW_CBPRN("Set: Get device statistics"); 1588 vmxnet3_fill_stats(s); 1589 break; 1590 1591 case VMXNET3_CMD_ACTIVATE_DEV: 1592 VMW_CBPRN("Set: Activating vmxnet3 device"); 1593 vmxnet3_activate_device(s); 1594 break; 1595 1596 case VMXNET3_CMD_UPDATE_RX_MODE: 1597 VMW_CBPRN("Set: Update rx mode"); 1598 vmxnet3_update_rx_mode(s); 1599 break; 1600 1601 case VMXNET3_CMD_UPDATE_VLAN_FILTERS: 1602 VMW_CBPRN("Set: Update VLAN filters"); 1603 vmxnet3_update_vlan_filters(s); 1604 break; 1605 1606 case VMXNET3_CMD_UPDATE_MAC_FILTERS: 1607 VMW_CBPRN("Set: Update MAC filters"); 1608 vmxnet3_update_mcast_filters(s); 1609 break; 1610 1611 case VMXNET3_CMD_UPDATE_FEATURE: 1612 VMW_CBPRN("Set: Update features"); 1613 vmxnet3_update_features(s); 1614 break; 1615 1616 case VMXNET3_CMD_UPDATE_PMCFG: 1617 VMW_CBPRN("Set: Update power management config"); 1618 vmxnet3_update_pm_state(s); 1619 break; 1620 1621 case VMXNET3_CMD_GET_LINK: 1622 VMW_CBPRN("Set: Get link"); 1623 break; 1624 1625 case VMXNET3_CMD_RESET_DEV: 1626 VMW_CBPRN("Set: Reset device"); 1627 vmxnet3_reset(s); 1628 break; 1629 1630 case VMXNET3_CMD_QUIESCE_DEV: 1631 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device"); 1632 vmxnet3_deactivate_device(s); 1633 break; 1634 1635 case VMXNET3_CMD_GET_CONF_INTR: 1636 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration"); 1637 break; 1638 1639 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO: 1640 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - " 1641 "adaptive ring info flags"); 1642 break; 1643 1644 case VMXNET3_CMD_GET_DID_LO: 1645 VMW_CBPRN("Set: Get lower part of device ID"); 1646 break; 1647 1648 case VMXNET3_CMD_GET_DID_HI: 1649 VMW_CBPRN("Set: Get upper part of device ID"); 1650 break; 1651 1652 case VMXNET3_CMD_GET_DEV_EXTRA_INFO: 1653 VMW_CBPRN("Set: Get device extra info"); 1654 break; 1655 1656 default: 1657 VMW_CBPRN("Received unknown command: %" PRIx64, cmd); 1658 break; 1659 } 1660 } 1661 1662 static uint64_t vmxnet3_get_command_status(VMXNET3State *s) 1663 { 1664 uint64_t ret; 1665 1666 switch (s->last_command) { 1667 case VMXNET3_CMD_ACTIVATE_DEV: 1668 ret = (s->device_active) ? 0 : 1; 1669 VMW_CFPRN("Device active: %" PRIx64, ret); 1670 break; 1671 1672 case VMXNET3_CMD_RESET_DEV: 1673 case VMXNET3_CMD_QUIESCE_DEV: 1674 case VMXNET3_CMD_GET_QUEUE_STATUS: 1675 case VMXNET3_CMD_GET_DEV_EXTRA_INFO: 1676 ret = 0; 1677 break; 1678 1679 case VMXNET3_CMD_GET_LINK: 1680 ret = s->link_status_and_speed; 1681 VMW_CFPRN("Link and speed: %" PRIx64, ret); 1682 break; 1683 1684 case VMXNET3_CMD_GET_PERM_MAC_LO: 1685 ret = vmxnet3_get_mac_low(&s->perm_mac); 1686 break; 1687 1688 case VMXNET3_CMD_GET_PERM_MAC_HI: 1689 ret = vmxnet3_get_mac_high(&s->perm_mac); 1690 break; 1691 1692 case VMXNET3_CMD_GET_CONF_INTR: 1693 ret = vmxnet3_get_interrupt_config(s); 1694 break; 1695 1696 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO: 1697 ret = VMXNET3_DISABLE_ADAPTIVE_RING; 1698 break; 1699 1700 case VMXNET3_CMD_GET_DID_LO: 1701 ret = PCI_DEVICE_ID_VMWARE_VMXNET3; 1702 break; 1703 1704 case VMXNET3_CMD_GET_DID_HI: 1705 ret = VMXNET3_DEVICE_REVISION; 1706 break; 1707 1708 default: 1709 VMW_WRPRN("Received request for unknown command: %x", s->last_command); 1710 ret = 0; 1711 break; 1712 } 1713 1714 return ret; 1715 } 1716 1717 static void vmxnet3_set_events(VMXNET3State *s, uint32_t val) 1718 { 1719 uint32_t events; 1720 PCIDevice *d = PCI_DEVICE(s); 1721 1722 VMW_CBPRN("Setting events: 0x%x", val); 1723 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) | val; 1724 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events); 1725 } 1726 1727 static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val) 1728 { 1729 PCIDevice *d = PCI_DEVICE(s); 1730 uint32_t events; 1731 1732 VMW_CBPRN("Clearing events: 0x%x", val); 1733 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) & ~val; 1734 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events); 1735 } 1736 1737 static void 1738 vmxnet3_io_bar1_write(void *opaque, 1739 hwaddr addr, 1740 uint64_t val, 1741 unsigned size) 1742 { 1743 VMXNET3State *s = opaque; 1744 1745 switch (addr) { 1746 /* Vmxnet3 Revision Report Selection */ 1747 case VMXNET3_REG_VRRS: 1748 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d", 1749 val, size); 1750 break; 1751 1752 /* UPT Version Report Selection */ 1753 case VMXNET3_REG_UVRS: 1754 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d", 1755 val, size); 1756 break; 1757 1758 /* Driver Shared Address Low */ 1759 case VMXNET3_REG_DSAL: 1760 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d", 1761 val, size); 1762 /* 1763 * Guest driver will first write the low part of the shared 1764 * memory address. We save it to temp variable and set the 1765 * shared address only after we get the high part 1766 */ 1767 if (val == 0) { 1768 vmxnet3_deactivate_device(s); 1769 } 1770 s->temp_shared_guest_driver_memory = val; 1771 s->drv_shmem = 0; 1772 break; 1773 1774 /* Driver Shared Address High */ 1775 case VMXNET3_REG_DSAH: 1776 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d", 1777 val, size); 1778 /* 1779 * Set the shared memory between guest driver and device. 1780 * We already should have low address part. 1781 */ 1782 s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32); 1783 break; 1784 1785 /* Command */ 1786 case VMXNET3_REG_CMD: 1787 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d", 1788 val, size); 1789 vmxnet3_handle_command(s, val); 1790 break; 1791 1792 /* MAC Address Low */ 1793 case VMXNET3_REG_MACL: 1794 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d", 1795 val, size); 1796 s->temp_mac = val; 1797 break; 1798 1799 /* MAC Address High */ 1800 case VMXNET3_REG_MACH: 1801 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d", 1802 val, size); 1803 vmxnet3_set_variable_mac(s, val, s->temp_mac); 1804 break; 1805 1806 /* Interrupt Cause Register */ 1807 case VMXNET3_REG_ICR: 1808 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d", 1809 val, size); 1810 qemu_log_mask(LOG_GUEST_ERROR, 1811 "%s: write to read-only register VMXNET3_REG_ICR\n", 1812 TYPE_VMXNET3); 1813 break; 1814 1815 /* Event Cause Register */ 1816 case VMXNET3_REG_ECR: 1817 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d", 1818 val, size); 1819 vmxnet3_ack_events(s, val); 1820 break; 1821 1822 default: 1823 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d", 1824 addr, val, size); 1825 break; 1826 } 1827 } 1828 1829 static uint64_t 1830 vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size) 1831 { 1832 VMXNET3State *s = opaque; 1833 uint64_t ret = 0; 1834 1835 switch (addr) { 1836 /* Vmxnet3 Revision Report Selection */ 1837 case VMXNET3_REG_VRRS: 1838 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size); 1839 ret = VMXNET3_DEVICE_REVISION; 1840 break; 1841 1842 /* UPT Version Report Selection */ 1843 case VMXNET3_REG_UVRS: 1844 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size); 1845 ret = VMXNET3_UPT_REVISION; 1846 break; 1847 1848 /* Command */ 1849 case VMXNET3_REG_CMD: 1850 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size); 1851 ret = vmxnet3_get_command_status(s); 1852 break; 1853 1854 /* MAC Address Low */ 1855 case VMXNET3_REG_MACL: 1856 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size); 1857 ret = vmxnet3_get_mac_low(&s->conf.macaddr); 1858 break; 1859 1860 /* MAC Address High */ 1861 case VMXNET3_REG_MACH: 1862 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size); 1863 ret = vmxnet3_get_mac_high(&s->conf.macaddr); 1864 break; 1865 1866 /* 1867 * Interrupt Cause Register 1868 * Used for legacy interrupts only so interrupt index always 0 1869 */ 1870 case VMXNET3_REG_ICR: 1871 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size); 1872 if (vmxnet3_interrupt_asserted(s, 0)) { 1873 vmxnet3_clear_interrupt(s, 0); 1874 ret = true; 1875 } else { 1876 ret = false; 1877 } 1878 break; 1879 1880 default: 1881 VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size); 1882 break; 1883 } 1884 1885 return ret; 1886 } 1887 1888 static int 1889 vmxnet3_can_receive(NetClientState *nc) 1890 { 1891 VMXNET3State *s = qemu_get_nic_opaque(nc); 1892 return s->device_active && 1893 VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP); 1894 } 1895 1896 static inline bool 1897 vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data) 1898 { 1899 uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK; 1900 if (IS_SPECIAL_VLAN_ID(vlan_tag)) { 1901 return true; 1902 } 1903 1904 return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag); 1905 } 1906 1907 static bool 1908 vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac) 1909 { 1910 int i; 1911 for (i = 0; i < s->mcast_list_len; i++) { 1912 if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) { 1913 return true; 1914 } 1915 } 1916 return false; 1917 } 1918 1919 static bool 1920 vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data, 1921 size_t size) 1922 { 1923 struct eth_header *ehdr = PKT_GET_ETH_HDR(data); 1924 1925 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) { 1926 return true; 1927 } 1928 1929 if (!vmxnet3_is_registered_vlan(s, data)) { 1930 return false; 1931 } 1932 1933 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) { 1934 case ETH_PKT_UCAST: 1935 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) { 1936 return false; 1937 } 1938 if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) { 1939 return false; 1940 } 1941 break; 1942 1943 case ETH_PKT_BCAST: 1944 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) { 1945 return false; 1946 } 1947 break; 1948 1949 case ETH_PKT_MCAST: 1950 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) { 1951 return true; 1952 } 1953 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) { 1954 return false; 1955 } 1956 if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) { 1957 return false; 1958 } 1959 break; 1960 1961 default: 1962 g_assert_not_reached(); 1963 } 1964 1965 return true; 1966 } 1967 1968 static ssize_t 1969 vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size) 1970 { 1971 VMXNET3State *s = qemu_get_nic_opaque(nc); 1972 size_t bytes_indicated; 1973 uint8_t min_buf[MIN_BUF_SIZE]; 1974 1975 if (!vmxnet3_can_receive(nc)) { 1976 VMW_PKPRN("Cannot receive now"); 1977 return -1; 1978 } 1979 1980 if (s->peer_has_vhdr) { 1981 net_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf); 1982 buf += sizeof(struct virtio_net_hdr); 1983 size -= sizeof(struct virtio_net_hdr); 1984 } 1985 1986 /* Pad to minimum Ethernet frame length */ 1987 if (size < sizeof(min_buf)) { 1988 memcpy(min_buf, buf, size); 1989 memset(&min_buf[size], 0, sizeof(min_buf) - size); 1990 buf = min_buf; 1991 size = sizeof(min_buf); 1992 } 1993 1994 net_rx_pkt_set_packet_type(s->rx_pkt, 1995 get_eth_packet_type(PKT_GET_ETH_HDR(buf))); 1996 1997 if (vmxnet3_rx_filter_may_indicate(s, buf, size)) { 1998 net_rx_pkt_set_protocols(s->rx_pkt, buf, size); 1999 vmxnet3_rx_need_csum_calculate(s->rx_pkt, buf, size); 2000 net_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping); 2001 bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1; 2002 if (bytes_indicated < size) { 2003 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated, size); 2004 } 2005 } else { 2006 VMW_PKPRN("Packet dropped by RX filter"); 2007 bytes_indicated = size; 2008 } 2009 2010 assert(size > 0); 2011 assert(bytes_indicated != 0); 2012 return bytes_indicated; 2013 } 2014 2015 static void vmxnet3_set_link_status(NetClientState *nc) 2016 { 2017 VMXNET3State *s = qemu_get_nic_opaque(nc); 2018 2019 if (nc->link_down) { 2020 s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP; 2021 } else { 2022 s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP; 2023 } 2024 2025 vmxnet3_set_events(s, VMXNET3_ECR_LINK); 2026 vmxnet3_trigger_interrupt(s, s->event_int_idx); 2027 } 2028 2029 static NetClientInfo net_vmxnet3_info = { 2030 .type = NET_CLIENT_DRIVER_NIC, 2031 .size = sizeof(NICState), 2032 .receive = vmxnet3_receive, 2033 .link_status_changed = vmxnet3_set_link_status, 2034 }; 2035 2036 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s) 2037 { 2038 NetClientState *nc = qemu_get_queue(s->nic); 2039 2040 if (qemu_has_vnet_hdr(nc->peer)) { 2041 return true; 2042 } 2043 2044 return false; 2045 } 2046 2047 static void vmxnet3_net_uninit(VMXNET3State *s) 2048 { 2049 g_free(s->mcast_list); 2050 vmxnet3_deactivate_device(s); 2051 qemu_del_nic(s->nic); 2052 } 2053 2054 static void vmxnet3_net_init(VMXNET3State *s) 2055 { 2056 DeviceState *d = DEVICE(s); 2057 2058 VMW_CBPRN("vmxnet3_net_init called..."); 2059 2060 qemu_macaddr_default_if_unset(&s->conf.macaddr); 2061 2062 /* Windows guest will query the address that was set on init */ 2063 memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a)); 2064 2065 s->mcast_list = NULL; 2066 s->mcast_list_len = 0; 2067 2068 s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP; 2069 2070 VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a)); 2071 2072 s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf, 2073 object_get_typename(OBJECT(s)), 2074 d->id, s); 2075 2076 s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s); 2077 s->tx_sop = true; 2078 s->skip_current_tx_pkt = false; 2079 s->tx_pkt = NULL; 2080 s->rx_pkt = NULL; 2081 s->rx_vlan_stripping = false; 2082 s->lro_supported = false; 2083 2084 if (s->peer_has_vhdr) { 2085 qemu_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer, 2086 sizeof(struct virtio_net_hdr)); 2087 2088 qemu_using_vnet_hdr(qemu_get_queue(s->nic)->peer, 1); 2089 } 2090 2091 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 2092 } 2093 2094 static void 2095 vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors) 2096 { 2097 PCIDevice *d = PCI_DEVICE(s); 2098 int i; 2099 for (i = 0; i < num_vectors; i++) { 2100 msix_vector_unuse(d, i); 2101 } 2102 } 2103 2104 static void 2105 vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors) 2106 { 2107 PCIDevice *d = PCI_DEVICE(s); 2108 int i; 2109 for (i = 0; i < num_vectors; i++) { 2110 msix_vector_use(d, i); 2111 } 2112 } 2113 2114 static bool 2115 vmxnet3_init_msix(VMXNET3State *s) 2116 { 2117 PCIDevice *d = PCI_DEVICE(s); 2118 int res = msix_init(d, VMXNET3_MAX_INTRS, 2119 &s->msix_bar, 2120 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE, 2121 &s->msix_bar, 2122 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA(s), 2123 VMXNET3_MSIX_OFFSET(s), NULL); 2124 2125 if (0 > res) { 2126 VMW_WRPRN("Failed to initialize MSI-X, error %d", res); 2127 s->msix_used = false; 2128 } else { 2129 vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS); 2130 s->msix_used = true; 2131 } 2132 return s->msix_used; 2133 } 2134 2135 static void 2136 vmxnet3_cleanup_msix(VMXNET3State *s) 2137 { 2138 PCIDevice *d = PCI_DEVICE(s); 2139 2140 if (s->msix_used) { 2141 vmxnet3_unuse_msix_vectors(s, VMXNET3_MAX_INTRS); 2142 msix_uninit(d, &s->msix_bar, &s->msix_bar); 2143 } 2144 } 2145 2146 static void 2147 vmxnet3_cleanup_msi(VMXNET3State *s) 2148 { 2149 PCIDevice *d = PCI_DEVICE(s); 2150 2151 msi_uninit(d); 2152 } 2153 2154 static const MemoryRegionOps b0_ops = { 2155 .read = vmxnet3_io_bar0_read, 2156 .write = vmxnet3_io_bar0_write, 2157 .endianness = DEVICE_LITTLE_ENDIAN, 2158 .impl = { 2159 .min_access_size = 4, 2160 .max_access_size = 4, 2161 }, 2162 }; 2163 2164 static const MemoryRegionOps b1_ops = { 2165 .read = vmxnet3_io_bar1_read, 2166 .write = vmxnet3_io_bar1_write, 2167 .endianness = DEVICE_LITTLE_ENDIAN, 2168 .impl = { 2169 .min_access_size = 4, 2170 .max_access_size = 4, 2171 }, 2172 }; 2173 2174 static uint64_t vmxnet3_device_serial_num(VMXNET3State *s) 2175 { 2176 uint64_t dsn_payload; 2177 uint8_t *dsnp = (uint8_t *)&dsn_payload; 2178 2179 dsnp[0] = 0xfe; 2180 dsnp[1] = s->conf.macaddr.a[3]; 2181 dsnp[2] = s->conf.macaddr.a[4]; 2182 dsnp[3] = s->conf.macaddr.a[5]; 2183 dsnp[4] = s->conf.macaddr.a[0]; 2184 dsnp[5] = s->conf.macaddr.a[1]; 2185 dsnp[6] = s->conf.macaddr.a[2]; 2186 dsnp[7] = 0xff; 2187 return dsn_payload; 2188 } 2189 2190 2191 #define VMXNET3_USE_64BIT (true) 2192 #define VMXNET3_PER_VECTOR_MASK (false) 2193 2194 static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp) 2195 { 2196 VMXNET3State *s = VMXNET3(pci_dev); 2197 int ret; 2198 2199 VMW_CBPRN("Starting init..."); 2200 2201 memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s, 2202 "vmxnet3-b0", VMXNET3_PT_REG_SIZE); 2203 pci_register_bar(pci_dev, VMXNET3_BAR0_IDX, 2204 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 2205 2206 memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s, 2207 "vmxnet3-b1", VMXNET3_VD_REG_SIZE); 2208 pci_register_bar(pci_dev, VMXNET3_BAR1_IDX, 2209 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1); 2210 2211 memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar", 2212 VMXNET3_MSIX_BAR_SIZE); 2213 pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX, 2214 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar); 2215 2216 vmxnet3_reset_interrupt_states(s); 2217 2218 /* Interrupt pin A */ 2219 pci_dev->config[PCI_INTERRUPT_PIN] = 0x01; 2220 2221 ret = msi_init(pci_dev, VMXNET3_MSI_OFFSET(s), VMXNET3_MAX_NMSIX_INTRS, 2222 VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK, NULL); 2223 /* Any error other than -ENOTSUP(board's MSI support is broken) 2224 * is a programming error. Fall back to INTx silently on -ENOTSUP */ 2225 assert(!ret || ret == -ENOTSUP); 2226 2227 if (!vmxnet3_init_msix(s)) { 2228 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent."); 2229 } 2230 2231 vmxnet3_net_init(s); 2232 2233 if (pci_is_express(pci_dev)) { 2234 if (pci_bus_is_express(pci_get_bus(pci_dev))) { 2235 pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET); 2236 } 2237 2238 pcie_dev_ser_num_init(pci_dev, VMXNET3_DSN_OFFSET, 2239 vmxnet3_device_serial_num(s)); 2240 } 2241 } 2242 2243 static void vmxnet3_instance_init(Object *obj) 2244 { 2245 VMXNET3State *s = VMXNET3(obj); 2246 device_add_bootindex_property(obj, &s->conf.bootindex, 2247 "bootindex", "/ethernet-phy@0", 2248 DEVICE(obj)); 2249 } 2250 2251 static void vmxnet3_pci_uninit(PCIDevice *pci_dev) 2252 { 2253 VMXNET3State *s = VMXNET3(pci_dev); 2254 2255 VMW_CBPRN("Starting uninit..."); 2256 2257 vmxnet3_net_uninit(s); 2258 2259 vmxnet3_cleanup_msix(s); 2260 2261 vmxnet3_cleanup_msi(s); 2262 } 2263 2264 static void vmxnet3_qdev_reset(DeviceState *dev) 2265 { 2266 PCIDevice *d = PCI_DEVICE(dev); 2267 VMXNET3State *s = VMXNET3(d); 2268 2269 VMW_CBPRN("Starting QDEV reset..."); 2270 vmxnet3_reset(s); 2271 } 2272 2273 static bool vmxnet3_mc_list_needed(void *opaque) 2274 { 2275 return true; 2276 } 2277 2278 static int vmxnet3_mcast_list_pre_load(void *opaque) 2279 { 2280 VMXNET3State *s = opaque; 2281 2282 s->mcast_list = g_malloc(s->mcast_list_buff_size); 2283 2284 return 0; 2285 } 2286 2287 2288 static int vmxnet3_pre_save(void *opaque) 2289 { 2290 VMXNET3State *s = opaque; 2291 2292 s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr); 2293 2294 return 0; 2295 } 2296 2297 static const VMStateDescription vmxstate_vmxnet3_mcast_list = { 2298 .name = "vmxnet3/mcast_list", 2299 .version_id = 1, 2300 .minimum_version_id = 1, 2301 .pre_load = vmxnet3_mcast_list_pre_load, 2302 .needed = vmxnet3_mc_list_needed, 2303 .fields = (VMStateField[]) { 2304 VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL, 2305 mcast_list_buff_size), 2306 VMSTATE_END_OF_LIST() 2307 } 2308 }; 2309 2310 static const VMStateDescription vmstate_vmxnet3_ring = { 2311 .name = "vmxnet3-ring", 2312 .version_id = 0, 2313 .fields = (VMStateField[]) { 2314 VMSTATE_UINT64(pa, Vmxnet3Ring), 2315 VMSTATE_UINT32(size, Vmxnet3Ring), 2316 VMSTATE_UINT32(cell_size, Vmxnet3Ring), 2317 VMSTATE_UINT32(next, Vmxnet3Ring), 2318 VMSTATE_UINT8(gen, Vmxnet3Ring), 2319 VMSTATE_END_OF_LIST() 2320 } 2321 }; 2322 2323 static const VMStateDescription vmstate_vmxnet3_tx_stats = { 2324 .name = "vmxnet3-tx-stats", 2325 .version_id = 0, 2326 .fields = (VMStateField[]) { 2327 VMSTATE_UINT64(TSOPktsTxOK, struct UPT1_TxStats), 2328 VMSTATE_UINT64(TSOBytesTxOK, struct UPT1_TxStats), 2329 VMSTATE_UINT64(ucastPktsTxOK, struct UPT1_TxStats), 2330 VMSTATE_UINT64(ucastBytesTxOK, struct UPT1_TxStats), 2331 VMSTATE_UINT64(mcastPktsTxOK, struct UPT1_TxStats), 2332 VMSTATE_UINT64(mcastBytesTxOK, struct UPT1_TxStats), 2333 VMSTATE_UINT64(bcastPktsTxOK, struct UPT1_TxStats), 2334 VMSTATE_UINT64(bcastBytesTxOK, struct UPT1_TxStats), 2335 VMSTATE_UINT64(pktsTxError, struct UPT1_TxStats), 2336 VMSTATE_UINT64(pktsTxDiscard, struct UPT1_TxStats), 2337 VMSTATE_END_OF_LIST() 2338 } 2339 }; 2340 2341 static const VMStateDescription vmstate_vmxnet3_txq_descr = { 2342 .name = "vmxnet3-txq-descr", 2343 .version_id = 0, 2344 .fields = (VMStateField[]) { 2345 VMSTATE_STRUCT(tx_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring, 2346 Vmxnet3Ring), 2347 VMSTATE_STRUCT(comp_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring, 2348 Vmxnet3Ring), 2349 VMSTATE_UINT8(intr_idx, Vmxnet3TxqDescr), 2350 VMSTATE_UINT64(tx_stats_pa, Vmxnet3TxqDescr), 2351 VMSTATE_STRUCT(txq_stats, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_tx_stats, 2352 struct UPT1_TxStats), 2353 VMSTATE_END_OF_LIST() 2354 } 2355 }; 2356 2357 static const VMStateDescription vmstate_vmxnet3_rx_stats = { 2358 .name = "vmxnet3-rx-stats", 2359 .version_id = 0, 2360 .fields = (VMStateField[]) { 2361 VMSTATE_UINT64(LROPktsRxOK, struct UPT1_RxStats), 2362 VMSTATE_UINT64(LROBytesRxOK, struct UPT1_RxStats), 2363 VMSTATE_UINT64(ucastPktsRxOK, struct UPT1_RxStats), 2364 VMSTATE_UINT64(ucastBytesRxOK, struct UPT1_RxStats), 2365 VMSTATE_UINT64(mcastPktsRxOK, struct UPT1_RxStats), 2366 VMSTATE_UINT64(mcastBytesRxOK, struct UPT1_RxStats), 2367 VMSTATE_UINT64(bcastPktsRxOK, struct UPT1_RxStats), 2368 VMSTATE_UINT64(bcastBytesRxOK, struct UPT1_RxStats), 2369 VMSTATE_UINT64(pktsRxOutOfBuf, struct UPT1_RxStats), 2370 VMSTATE_UINT64(pktsRxError, struct UPT1_RxStats), 2371 VMSTATE_END_OF_LIST() 2372 } 2373 }; 2374 2375 static const VMStateDescription vmstate_vmxnet3_rxq_descr = { 2376 .name = "vmxnet3-rxq-descr", 2377 .version_id = 0, 2378 .fields = (VMStateField[]) { 2379 VMSTATE_STRUCT_ARRAY(rx_ring, Vmxnet3RxqDescr, 2380 VMXNET3_RX_RINGS_PER_QUEUE, 0, 2381 vmstate_vmxnet3_ring, Vmxnet3Ring), 2382 VMSTATE_STRUCT(comp_ring, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_ring, 2383 Vmxnet3Ring), 2384 VMSTATE_UINT8(intr_idx, Vmxnet3RxqDescr), 2385 VMSTATE_UINT64(rx_stats_pa, Vmxnet3RxqDescr), 2386 VMSTATE_STRUCT(rxq_stats, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_rx_stats, 2387 struct UPT1_RxStats), 2388 VMSTATE_END_OF_LIST() 2389 } 2390 }; 2391 2392 static int vmxnet3_post_load(void *opaque, int version_id) 2393 { 2394 VMXNET3State *s = opaque; 2395 2396 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), s->max_tx_frags); 2397 net_rx_pkt_init(&s->rx_pkt); 2398 2399 if (s->msix_used) { 2400 vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS); 2401 } 2402 2403 if (!vmxnet3_validate_queues(s)) { 2404 return -1; 2405 } 2406 vmxnet3_validate_interrupts(s); 2407 2408 return 0; 2409 } 2410 2411 static const VMStateDescription vmstate_vmxnet3_int_state = { 2412 .name = "vmxnet3-int-state", 2413 .version_id = 0, 2414 .fields = (VMStateField[]) { 2415 VMSTATE_BOOL(is_masked, Vmxnet3IntState), 2416 VMSTATE_BOOL(is_pending, Vmxnet3IntState), 2417 VMSTATE_BOOL(is_asserted, Vmxnet3IntState), 2418 VMSTATE_END_OF_LIST() 2419 } 2420 }; 2421 2422 static const VMStateDescription vmstate_vmxnet3 = { 2423 .name = "vmxnet3", 2424 .version_id = 1, 2425 .minimum_version_id = 1, 2426 .pre_save = vmxnet3_pre_save, 2427 .post_load = vmxnet3_post_load, 2428 .fields = (VMStateField[]) { 2429 VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State), 2430 VMSTATE_MSIX(parent_obj, VMXNET3State), 2431 VMSTATE_BOOL(rx_packets_compound, VMXNET3State), 2432 VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State), 2433 VMSTATE_BOOL(lro_supported, VMXNET3State), 2434 VMSTATE_UINT32(rx_mode, VMXNET3State), 2435 VMSTATE_UINT32(mcast_list_len, VMXNET3State), 2436 VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State), 2437 VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE), 2438 VMSTATE_UINT32(mtu, VMXNET3State), 2439 VMSTATE_UINT16(max_rx_frags, VMXNET3State), 2440 VMSTATE_UINT32(max_tx_frags, VMXNET3State), 2441 VMSTATE_UINT8(event_int_idx, VMXNET3State), 2442 VMSTATE_BOOL(auto_int_masking, VMXNET3State), 2443 VMSTATE_UINT8(txq_num, VMXNET3State), 2444 VMSTATE_UINT8(rxq_num, VMXNET3State), 2445 VMSTATE_UINT32(device_active, VMXNET3State), 2446 VMSTATE_UINT32(last_command, VMXNET3State), 2447 VMSTATE_UINT32(link_status_and_speed, VMXNET3State), 2448 VMSTATE_UINT32(temp_mac, VMXNET3State), 2449 VMSTATE_UINT64(drv_shmem, VMXNET3State), 2450 VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State), 2451 2452 VMSTATE_STRUCT_ARRAY(txq_descr, VMXNET3State, 2453 VMXNET3_DEVICE_MAX_TX_QUEUES, 0, vmstate_vmxnet3_txq_descr, 2454 Vmxnet3TxqDescr), 2455 VMSTATE_STRUCT_ARRAY(rxq_descr, VMXNET3State, 2456 VMXNET3_DEVICE_MAX_RX_QUEUES, 0, vmstate_vmxnet3_rxq_descr, 2457 Vmxnet3RxqDescr), 2458 VMSTATE_STRUCT_ARRAY(interrupt_states, VMXNET3State, 2459 VMXNET3_MAX_INTRS, 0, vmstate_vmxnet3_int_state, 2460 Vmxnet3IntState), 2461 2462 VMSTATE_END_OF_LIST() 2463 }, 2464 .subsections = (const VMStateDescription*[]) { 2465 &vmxstate_vmxnet3_mcast_list, 2466 NULL 2467 } 2468 }; 2469 2470 static Property vmxnet3_properties[] = { 2471 DEFINE_NIC_PROPERTIES(VMXNET3State, conf), 2472 DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State, compat_flags, 2473 VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false), 2474 DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags, 2475 VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false), 2476 DEFINE_PROP_END_OF_LIST(), 2477 }; 2478 2479 static void vmxnet3_realize(DeviceState *qdev, Error **errp) 2480 { 2481 VMXNET3Class *vc = VMXNET3_DEVICE_GET_CLASS(qdev); 2482 PCIDevice *pci_dev = PCI_DEVICE(qdev); 2483 VMXNET3State *s = VMXNET3(qdev); 2484 2485 if (!(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE)) { 2486 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2487 } 2488 2489 vc->parent_dc_realize(qdev, errp); 2490 } 2491 2492 static void vmxnet3_class_init(ObjectClass *class, void *data) 2493 { 2494 DeviceClass *dc = DEVICE_CLASS(class); 2495 PCIDeviceClass *c = PCI_DEVICE_CLASS(class); 2496 VMXNET3Class *vc = VMXNET3_DEVICE_CLASS(class); 2497 2498 c->realize = vmxnet3_pci_realize; 2499 c->exit = vmxnet3_pci_uninit; 2500 c->vendor_id = PCI_VENDOR_ID_VMWARE; 2501 c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3; 2502 c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION; 2503 c->romfile = "efi-vmxnet3.rom"; 2504 c->class_id = PCI_CLASS_NETWORK_ETHERNET; 2505 c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; 2506 c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3; 2507 device_class_set_parent_realize(dc, vmxnet3_realize, 2508 &vc->parent_dc_realize); 2509 dc->desc = "VMWare Paravirtualized Ethernet v3"; 2510 dc->reset = vmxnet3_qdev_reset; 2511 dc->vmsd = &vmstate_vmxnet3; 2512 device_class_set_props(dc, vmxnet3_properties); 2513 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 2514 } 2515 2516 static const TypeInfo vmxnet3_info = { 2517 .name = TYPE_VMXNET3, 2518 .parent = TYPE_PCI_DEVICE, 2519 .class_size = sizeof(VMXNET3Class), 2520 .instance_size = sizeof(VMXNET3State), 2521 .class_init = vmxnet3_class_init, 2522 .instance_init = vmxnet3_instance_init, 2523 .interfaces = (InterfaceInfo[]) { 2524 { INTERFACE_PCIE_DEVICE }, 2525 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 2526 { } 2527 }, 2528 }; 2529 2530 static void vmxnet3_register_types(void) 2531 { 2532 VMW_CBPRN("vmxnet3_register_types called..."); 2533 type_register_static(&vmxnet3_info); 2534 } 2535 2536 type_init(vmxnet3_register_types) 2537