xive2.c (0aa2612a01f233a4a25fb89e8362baf6cf896be6) xive2.c (95d729e2bc5b46d40e71971043e03d9cc9503e9a)
1/*
2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10)
3 *
4 * Copyright (c) 2019-2022, IBM Corporation..
5 *
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */

--- 145 unchanged lines hidden (view full) ---

154 qgen ^= 1;
155 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen);
156
157 /* TODO(PowerNV): reset GF bit on a cache watch operation */
158 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen);
159 }
160 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex);
161}
1/*
2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10)
3 *
4 * Copyright (c) 2019-2022, IBM Corporation..
5 *
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */

--- 145 unchanged lines hidden (view full) ---

154 qgen ^= 1;
155 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen);
156
157 /* TODO(PowerNV): reset GF bit on a cache watch operation */
158 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen);
159 }
160 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex);
161}
162
162/*
163/*
164 * XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode
165 */
166
167static void xive2_os_cam_decode(uint32_t cam, uint8_t *nvp_blk,
168 uint32_t *nvp_idx, bool *vo)
169{
170 *nvp_blk = xive2_nvp_blk(cam);
171 *nvp_idx = xive2_nvp_idx(cam);
172 *vo = !!(cam & TM2_QW1W2_VO);
173}
174
175uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
176 hwaddr offset, unsigned size)
177{
178 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
179 uint32_t qw1w2_new;
180 uint32_t cam = be32_to_cpu(qw1w2);
181 uint8_t nvp_blk;
182 uint32_t nvp_idx;
183 bool vo;
184
185 xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo);
186
187 if (!vo) {
188 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n",
189 nvp_blk, nvp_idx);
190 }
191
192 /* Invalidate CAM line */
193 qw1w2_new = xive_set_field32(TM2_QW1W2_VO, qw1w2, 0);
194 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4);
195
196 return qw1w2;
197}
198
199static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx,
200 uint8_t nvp_blk, uint32_t nvp_idx)
201{
202 Xive2Nvp nvp;
203 uint8_t ipb;
204 uint8_t cppr = 0;
205
206 /*
207 * Grab the associated thread interrupt context registers in the
208 * associated NVP
209 */
210 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
211 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
212 nvp_blk, nvp_idx);
213 return;
214 }
215
216 if (!xive2_nvp_is_valid(&nvp)) {
217 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
218 nvp_blk, nvp_idx);
219 return;
220 }
221
222 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2);
223 if (ipb) {
224 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0);
225 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
226 }
227
228 /* An IPB or CPPR change can trigger a resend */
229 if (ipb || cppr) {
230 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb);
231 }
232}
233
234/*
235 * Updating the OS CAM line can trigger a resend of interrupt
236 */
237void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
238 hwaddr offset, uint64_t value, unsigned size)
239{
240 uint32_t cam = value;
241 uint32_t qw1w2 = cpu_to_be32(cam);
242 uint8_t nvp_blk;
243 uint32_t nvp_idx;
244 bool vo;
245
246 xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo);
247
248 /* First update the thead context */
249 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
250
251 /* Check the interrupt pending bits */
252 if (vo) {
253 xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx);
254 }
255}
256
257/*
163 * XIVE Router (aka. Virtualization Controller or IVRE)
164 */
165
166int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
167 Xive2Eas *eas)
168{
169 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
170

--- 629 unchanged lines hidden --- 		258 * XIVE Router (aka. Virtualization Controller or IVRE)
259 */
260
261int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
262 Xive2Eas *eas)
263{
264 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
265

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