1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation.. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "hw/qdev-properties.h" 18 #include "monitor/monitor.h" 19 #include "hw/ppc/xive.h" 20 #include "hw/ppc/xive2.h" 21 #include "hw/ppc/xive2_regs.h" 22 23 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, Monitor *mon) 24 { 25 if (!xive2_eas_is_valid(eas)) { 26 return; 27 } 28 29 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 30 lisn, xive2_eas_is_masked(eas) ? "M" : " ", 31 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 32 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 33 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 34 } 35 36 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, 37 Monitor *mon) 38 { 39 uint64_t qaddr_base = xive2_end_qaddr(end); 40 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 41 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 42 uint32_t qentries = 1 << (qsize + 10); 43 int i; 44 45 /* 46 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 47 */ 48 monitor_printf(mon, " [ "); 49 qindex = (qindex - (width - 1)) & (qentries - 1); 50 for (i = 0; i < width; i++) { 51 uint64_t qaddr = qaddr_base + (qindex << 2); 52 uint32_t qdata = -1; 53 54 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 55 sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 56 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 57 HWADDR_PRIx "\n", qaddr); 58 return; 59 } 60 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 61 be32_to_cpu(qdata)); 62 qindex = (qindex + 1) & (qentries - 1); 63 } 64 monitor_printf(mon, "]"); 65 } 66 67 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon) 68 { 69 uint64_t qaddr_base = xive2_end_qaddr(end); 70 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 71 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 72 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 73 uint32_t qentries = 1 << (qsize + 10); 74 75 uint32_t nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6); 76 uint32_t nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6); 77 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7); 78 uint8_t pq; 79 80 if (!xive2_end_is_valid(end)) { 81 return; 82 } 83 84 pq = xive_get_field32(END2_W1_ESn, end->w1); 85 86 monitor_printf(mon, 87 " %08x %c%c %c%c%c%c%c%c%c%c%c%c prio:%d nvp:%02x/%04x", 88 end_idx, 89 pq & XIVE_ESB_VAL_P ? 'P' : '-', 90 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 91 xive2_end_is_valid(end) ? 'v' : '-', 92 xive2_end_is_enqueue(end) ? 'q' : '-', 93 xive2_end_is_notify(end) ? 'n' : '-', 94 xive2_end_is_backlog(end) ? 'b' : '-', 95 xive2_end_is_escalate(end) ? 'e' : '-', 96 xive2_end_is_escalate_end(end) ? 'N' : '-', 97 xive2_end_is_uncond_escalation(end) ? 'u' : '-', 98 xive2_end_is_silent_escalation(end) ? 's' : '-', 99 xive2_end_is_firmware1(end) ? 'f' : '-', 100 xive2_end_is_firmware2(end) ? 'F' : '-', 101 priority, nvp_blk, nvp_idx); 102 103 if (qaddr_base) { 104 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 105 qaddr_base, qindex, qentries, qgen); 106 xive2_end_queue_pic_print_info(end, 6, mon); 107 } 108 monitor_printf(mon, "\n"); 109 } 110 111 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx, 112 Monitor *mon) 113 { 114 Xive2Eas *eas = (Xive2Eas *) &end->w4; 115 uint8_t pq; 116 117 if (!xive2_end_is_escalate(end)) { 118 return; 119 } 120 121 pq = xive_get_field32(END2_W1_ESe, end->w1); 122 123 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 124 end_idx, 125 pq & XIVE_ESB_VAL_P ? 'P' : '-', 126 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 127 xive2_eas_is_valid(eas) ? 'v' : ' ', 128 xive2_eas_is_masked(eas) ? 'M' : ' ', 129 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 130 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 131 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 132 } 133 134 static void xive2_end_enqueue(Xive2End *end, uint32_t data) 135 { 136 uint64_t qaddr_base = xive2_end_qaddr(end); 137 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 138 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 139 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 140 141 uint64_t qaddr = qaddr_base + (qindex << 2); 142 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 143 uint32_t qentries = 1 << (qsize + 10); 144 145 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata), 146 MEMTXATTRS_UNSPECIFIED)) { 147 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 148 HWADDR_PRIx "\n", qaddr); 149 return; 150 } 151 152 qindex = (qindex + 1) & (qentries - 1); 153 if (qindex == 0) { 154 qgen ^= 1; 155 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); 156 157 /* TODO(PowerNV): reset GF bit on a cache watch operation */ 158 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen); 159 } 160 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); 161 } 162 /* 163 * XIVE Router (aka. Virtualization Controller or IVRE) 164 */ 165 166 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 167 Xive2Eas *eas) 168 { 169 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 170 171 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 172 } 173 174 static 175 int xive2_router_get_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 176 uint8_t *pq) 177 { 178 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 179 180 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); 181 } 182 183 static 184 int xive2_router_set_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 185 uint8_t *pq) 186 { 187 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 188 189 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); 190 } 191 192 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 193 Xive2End *end) 194 { 195 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 196 197 return xrc->get_end(xrtr, end_blk, end_idx, end); 198 } 199 200 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 201 Xive2End *end, uint8_t word_number) 202 { 203 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 204 205 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 206 } 207 208 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 209 Xive2Nvp *nvp) 210 { 211 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 212 213 return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp); 214 } 215 216 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 217 Xive2Nvp *nvp, uint8_t word_number) 218 { 219 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 220 221 return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number); 222 } 223 224 static int xive2_router_get_block_id(Xive2Router *xrtr) 225 { 226 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 227 228 return xrc->get_block_id(xrtr); 229 } 230 231 /* 232 * Encode the HW CAM line with 7bit or 8bit thread id. The thread id 233 * width and block id width is configurable at the IC level. 234 * 235 * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit) 236 * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit) 237 */ 238 static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 239 { 240 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 241 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 242 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 243 uint8_t blk = xive2_router_get_block_id(xrtr); 244 uint8_t tid_shift = 7; 245 uint8_t tid_mask = (1 << tid_shift) - 1; 246 247 return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); 248 } 249 250 /* 251 * The thread context register words are in big-endian format. 252 */ 253 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 254 uint8_t format, 255 uint8_t nvt_blk, uint32_t nvt_idx, 256 bool cam_ignore, uint32_t logic_serv) 257 { 258 uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx); 259 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 260 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 261 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 262 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 263 264 /* 265 * TODO (PowerNV): ignore mode. The low order bits of the NVT 266 * identifier are ignored in the "CAM" match. 267 */ 268 269 if (format == 0) { 270 if (cam_ignore == true) { 271 /* 272 * F=0 & i=1: Logical server notification (bits ignored at 273 * the end of the NVT identifier) 274 */ 275 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 276 nvt_blk, nvt_idx); 277 return -1; 278 } 279 280 /* F=0 & i=0: Specific NVT notification */ 281 282 /* PHYS ring */ 283 if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) && 284 cam == xive2_tctx_hw_cam_line(xptr, tctx)) { 285 return TM_QW3_HV_PHYS; 286 } 287 288 /* HV POOL ring */ 289 if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) && 290 cam == xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2)) { 291 return TM_QW2_HV_POOL; 292 } 293 294 /* OS ring */ 295 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 296 cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) { 297 return TM_QW1_OS; 298 } 299 } else { 300 /* F=1 : User level Event-Based Branch (EBB) notification */ 301 302 /* USER ring */ 303 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 304 (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) && 305 (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) && 306 (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) { 307 return TM_QW0_USER; 308 } 309 } 310 return -1; 311 } 312 313 static void xive2_router_realize(DeviceState *dev, Error **errp) 314 { 315 Xive2Router *xrtr = XIVE2_ROUTER(dev); 316 317 assert(xrtr->xfb); 318 } 319 320 /* 321 * Notification using the END ESe/ESn bit (Event State Buffer for 322 * escalation and notification). Profide futher coalescing in the 323 * Router. 324 */ 325 static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk, 326 uint32_t end_idx, Xive2End *end, 327 uint32_t end_esmask) 328 { 329 uint8_t pq = xive_get_field32(end_esmask, end->w1); 330 bool notify = xive_esb_trigger(&pq); 331 332 if (pq != xive_get_field32(end_esmask, end->w1)) { 333 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 334 xive2_router_write_end(xrtr, end_blk, end_idx, end, 1); 335 } 336 337 /* ESe/n[Q]=1 : end of notification */ 338 return notify; 339 } 340 341 /* 342 * An END trigger can come from an event trigger (IPI or HW) or from 343 * another chip. We don't model the PowerBus but the END trigger 344 * message has the same parameters than in the function below. 345 */ 346 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, 347 uint32_t end_idx, uint32_t end_data) 348 { 349 Xive2End end; 350 uint8_t priority; 351 uint8_t format; 352 bool found; 353 Xive2Nvp nvp; 354 uint8_t nvp_blk; 355 uint32_t nvp_idx; 356 357 /* END cache lookup */ 358 if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) { 359 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 360 end_idx); 361 return; 362 } 363 364 if (!xive2_end_is_valid(&end)) { 365 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 366 end_blk, end_idx); 367 return; 368 } 369 370 if (xive2_end_is_enqueue(&end)) { 371 xive2_end_enqueue(&end, end_data); 372 /* Enqueuing event data modifies the EQ toggle and index */ 373 xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1); 374 } 375 376 /* 377 * When the END is silent, we skip the notification part. 378 */ 379 if (xive2_end_is_silent_escalation(&end)) { 380 goto do_escalation; 381 } 382 383 /* 384 * The W7 format depends on the F bit in W6. It defines the type 385 * of the notification : 386 * 387 * F=0 : single or multiple NVP notification 388 * F=1 : User level Event-Based Branch (EBB) notification, no 389 * priority 390 */ 391 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6); 392 priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7); 393 394 /* The END is masked */ 395 if (format == 0 && priority == 0xff) { 396 return; 397 } 398 399 /* 400 * Check the END ESn (Event State Buffer for notification) for 401 * even futher coalescing in the Router 402 */ 403 if (!xive2_end_is_notify(&end)) { 404 /* ESn[Q]=1 : end of notification */ 405 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 406 &end, END2_W1_ESn)) { 407 return; 408 } 409 } 410 411 /* 412 * Follows IVPE notification 413 */ 414 nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6); 415 nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6); 416 417 /* NVP cache lookup */ 418 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 419 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n", 420 nvp_blk, nvp_idx); 421 return; 422 } 423 424 if (!xive2_nvp_is_valid(&nvp)) { 425 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n", 426 nvp_blk, nvp_idx); 427 return; 428 } 429 430 found = xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx, 431 xive_get_field32(END2_W6_IGNORE, end.w7), 432 priority, 433 xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7)); 434 435 /* TODO: Auto EOI. */ 436 437 if (found) { 438 return; 439 } 440 441 /* 442 * If no matching NVP is dispatched on a HW thread : 443 * - specific VP: update the NVP structure if backlog is activated 444 * - logical server : forward request to IVPE (not supported) 445 */ 446 if (xive2_end_is_backlog(&end)) { 447 uint8_t ipb; 448 449 if (format == 1) { 450 qemu_log_mask(LOG_GUEST_ERROR, 451 "XIVE: END %x/%x invalid config: F1 & backlog\n", 452 end_blk, end_idx); 453 return; 454 } 455 456 /* 457 * Record the IPB in the associated NVP structure for later 458 * use. The presenter will resend the interrupt when the vCPU 459 * is dispatched again on a HW thread. 460 */ 461 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) | 462 xive_priority_to_ipb(priority); 463 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); 464 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 465 466 /* 467 * On HW, follows a "Broadcast Backlog" to IVPEs 468 */ 469 } 470 471 do_escalation: 472 /* 473 * If activated, escalate notification using the ESe PQ bits and 474 * the EAS in w4-5 475 */ 476 if (!xive2_end_is_escalate(&end)) { 477 return; 478 } 479 480 /* 481 * Check the END ESe (Event State Buffer for escalation) for even 482 * futher coalescing in the Router 483 */ 484 if (!xive2_end_is_uncond_escalation(&end)) { 485 /* ESe[Q]=1 : end of escalation notification */ 486 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 487 &end, END2_W1_ESe)) { 488 return; 489 } 490 } 491 492 /* 493 * The END trigger becomes an Escalation trigger 494 */ 495 xive2_router_end_notify(xrtr, 496 xive_get_field32(END2_W4_END_BLOCK, end.w4), 497 xive_get_field32(END2_W4_ESC_END_INDEX, end.w4), 498 xive_get_field32(END2_W5_ESC_END_DATA, end.w5)); 499 } 500 501 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) 502 { 503 Xive2Router *xrtr = XIVE2_ROUTER(xn); 504 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 505 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 506 Xive2Eas eas; 507 508 /* EAS cache lookup */ 509 if (xive2_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 510 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 511 return; 512 } 513 514 if (!pq_checked) { 515 bool notify; 516 uint8_t pq; 517 518 /* PQ cache lookup */ 519 if (xive2_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) { 520 /* Set FIR */ 521 g_assert_not_reached(); 522 } 523 524 notify = xive_esb_trigger(&pq); 525 526 if (xive2_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) { 527 /* Set FIR */ 528 g_assert_not_reached(); 529 } 530 531 if (!notify) { 532 return; 533 } 534 } 535 536 if (!xive2_eas_is_valid(&eas)) { 537 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn); 538 return; 539 } 540 541 if (xive2_eas_is_masked(&eas)) { 542 /* Notification completed */ 543 return; 544 } 545 546 /* 547 * The event trigger becomes an END trigger 548 */ 549 xive2_router_end_notify(xrtr, 550 xive_get_field64(EAS2_END_BLOCK, eas.w), 551 xive_get_field64(EAS2_END_INDEX, eas.w), 552 xive_get_field64(EAS2_END_DATA, eas.w)); 553 } 554 555 static Property xive2_router_properties[] = { 556 DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb, 557 TYPE_XIVE_FABRIC, XiveFabric *), 558 DEFINE_PROP_END_OF_LIST(), 559 }; 560 561 static void xive2_router_class_init(ObjectClass *klass, void *data) 562 { 563 DeviceClass *dc = DEVICE_CLASS(klass); 564 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 565 566 dc->desc = "XIVE2 Router Engine"; 567 device_class_set_props(dc, xive2_router_properties); 568 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 569 dc->realize = xive2_router_realize; 570 xnc->notify = xive2_router_notify; 571 } 572 573 static const TypeInfo xive2_router_info = { 574 .name = TYPE_XIVE2_ROUTER, 575 .parent = TYPE_SYS_BUS_DEVICE, 576 .abstract = true, 577 .instance_size = sizeof(Xive2Router), 578 .class_size = sizeof(Xive2RouterClass), 579 .class_init = xive2_router_class_init, 580 .interfaces = (InterfaceInfo[]) { 581 { TYPE_XIVE_NOTIFIER }, 582 { TYPE_XIVE_PRESENTER }, 583 { } 584 } 585 }; 586 587 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 588 { 589 return !((addr >> shift) & 1); 590 } 591 592 static uint64_t xive2_end_source_read(void *opaque, hwaddr addr, unsigned size) 593 { 594 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 595 uint32_t offset = addr & 0xFFF; 596 uint8_t end_blk; 597 uint32_t end_idx; 598 Xive2End end; 599 uint32_t end_esmask; 600 uint8_t pq; 601 uint64_t ret; 602 603 /* 604 * The block id should be deduced from the load address on the END 605 * ESB MMIO but our model only supports a single block per XIVE chip. 606 */ 607 end_blk = xive2_router_get_block_id(xsrc->xrtr); 608 end_idx = addr >> (xsrc->esb_shift + 1); 609 610 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 611 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 612 end_idx); 613 return -1; 614 } 615 616 if (!xive2_end_is_valid(&end)) { 617 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 618 end_blk, end_idx); 619 return -1; 620 } 621 622 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 623 END2_W1_ESe; 624 pq = xive_get_field32(end_esmask, end.w1); 625 626 switch (offset) { 627 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 628 ret = xive_esb_eoi(&pq); 629 630 /* Forward the source event notification for routing ?? */ 631 break; 632 633 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 634 ret = pq; 635 break; 636 637 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 638 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 639 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 640 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 641 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 642 break; 643 default: 644 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 645 offset); 646 return -1; 647 } 648 649 if (pq != xive_get_field32(end_esmask, end.w1)) { 650 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 651 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 652 } 653 654 return ret; 655 } 656 657 static void xive2_end_source_write(void *opaque, hwaddr addr, 658 uint64_t value, unsigned size) 659 { 660 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 661 uint32_t offset = addr & 0xFFF; 662 uint8_t end_blk; 663 uint32_t end_idx; 664 Xive2End end; 665 uint32_t end_esmask; 666 uint8_t pq; 667 bool notify = false; 668 669 /* 670 * The block id should be deduced from the load address on the END 671 * ESB MMIO but our model only supports a single block per XIVE chip. 672 */ 673 end_blk = xive2_router_get_block_id(xsrc->xrtr); 674 end_idx = addr >> (xsrc->esb_shift + 1); 675 676 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 677 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 678 end_idx); 679 return; 680 } 681 682 if (!xive2_end_is_valid(&end)) { 683 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 684 end_blk, end_idx); 685 return; 686 } 687 688 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 689 END2_W1_ESe; 690 pq = xive_get_field32(end_esmask, end.w1); 691 692 switch (offset) { 693 case 0 ... 0x3FF: 694 notify = xive_esb_trigger(&pq); 695 break; 696 697 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 698 /* TODO: can we check StoreEOI availability from the router ? */ 699 notify = xive_esb_eoi(&pq); 700 break; 701 702 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF: 703 if (end_esmask == END2_W1_ESe) { 704 qemu_log_mask(LOG_GUEST_ERROR, 705 "XIVE: END %x/%x can not EQ inject on ESe\n", 706 end_blk, end_idx); 707 return; 708 } 709 notify = true; 710 break; 711 712 default: 713 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n", 714 offset); 715 return; 716 } 717 718 if (pq != xive_get_field32(end_esmask, end.w1)) { 719 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 720 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 721 } 722 723 /* TODO: Forward the source event notification for routing */ 724 if (notify) { 725 ; 726 } 727 } 728 729 static const MemoryRegionOps xive2_end_source_ops = { 730 .read = xive2_end_source_read, 731 .write = xive2_end_source_write, 732 .endianness = DEVICE_BIG_ENDIAN, 733 .valid = { 734 .min_access_size = 8, 735 .max_access_size = 8, 736 }, 737 .impl = { 738 .min_access_size = 8, 739 .max_access_size = 8, 740 }, 741 }; 742 743 static void xive2_end_source_realize(DeviceState *dev, Error **errp) 744 { 745 Xive2EndSource *xsrc = XIVE2_END_SOURCE(dev); 746 747 assert(xsrc->xrtr); 748 749 if (!xsrc->nr_ends) { 750 error_setg(errp, "Number of interrupt needs to be greater than 0"); 751 return; 752 } 753 754 if (xsrc->esb_shift != XIVE_ESB_4K && 755 xsrc->esb_shift != XIVE_ESB_64K) { 756 error_setg(errp, "Invalid ESB shift setting"); 757 return; 758 } 759 760 /* 761 * Each END is assigned an even/odd pair of MMIO pages, the even page 762 * manages the ESn field while the odd page manages the ESe field. 763 */ 764 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 765 &xive2_end_source_ops, xsrc, "xive.end", 766 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 767 } 768 769 static Property xive2_end_source_properties[] = { 770 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0), 771 DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K), 772 DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER, 773 Xive2Router *), 774 DEFINE_PROP_END_OF_LIST(), 775 }; 776 777 static void xive2_end_source_class_init(ObjectClass *klass, void *data) 778 { 779 DeviceClass *dc = DEVICE_CLASS(klass); 780 781 dc->desc = "XIVE END Source"; 782 device_class_set_props(dc, xive2_end_source_properties); 783 dc->realize = xive2_end_source_realize; 784 } 785 786 static const TypeInfo xive2_end_source_info = { 787 .name = TYPE_XIVE2_END_SOURCE, 788 .parent = TYPE_DEVICE, 789 .instance_size = sizeof(Xive2EndSource), 790 .class_init = xive2_end_source_class_init, 791 }; 792 793 static void xive2_register_types(void) 794 { 795 type_register_static(&xive2_router_info); 796 type_register_static(&xive2_end_source_info); 797 } 798 799 type_init(xive2_register_types) 800