| amd_iommu.c (d29a09ca68428b5708024ea2e9143de0a031081d) | amd_iommu.c (fb9f592623b0f9bb82a88d68d7921fb581918ef5) |
|---|---|
| 1/* 2 * QEMU emulation of AMD IOMMU (AMD-Vi) 3 * 4 * Copyright (C) 2011 Eduard - Gabriel Munteanu 5 * Copyright (C) 2015 David Kiarie, <davidkiarie4@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by --- 1116 unchanged lines hidden (view full) --- 1125 1126 msi_reset(&s->pci.dev); 1127 amdvi_init(s); 1128} 1129 1130static void amdvi_realize(DeviceState *dev, Error **err) 1131{ 1132 AMDVIState *s = AMD_IOMMU_DEVICE(dev); | 1/* 2 * QEMU emulation of AMD IOMMU (AMD-Vi) 3 * 4 * Copyright (C) 2011 Eduard - Gabriel Munteanu 5 * Copyright (C) 2015 David Kiarie, <davidkiarie4@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by --- 1116 unchanged lines hidden (view full) --- 1125 1126 msi_reset(&s->pci.dev); 1127 amdvi_init(s); 1128} 1129 1130static void amdvi_realize(DeviceState *dev, Error **err) 1131{ 1132 AMDVIState *s = AMD_IOMMU_DEVICE(dev); |
| 1133 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev); |
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| 1133 PCIBus *bus = PC_MACHINE(qdev_get_machine())->bus; 1134 s->iotlb = g_hash_table_new_full(amdvi_uint64_hash, 1135 amdvi_uint64_equal, g_free, g_free); 1136 1137 /* This device should take care of IOMMU PCI properties */ | 1134 PCIBus *bus = PC_MACHINE(qdev_get_machine())->bus; 1135 s->iotlb = g_hash_table_new_full(amdvi_uint64_hash, 1136 amdvi_uint64_equal, g_free, g_free); 1137 1138 /* This device should take care of IOMMU PCI properties */ |
| 1139 x86_iommu->type = TYPE_AMD; |
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| 1138 qdev_set_parent_bus(DEVICE(&s->pci), &bus->qbus); 1139 object_property_set_bool(OBJECT(&s->pci), true, "realized", err); 1140 s->capab_offset = pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0, 1141 AMDVI_CAPAB_SIZE); 1142 pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, AMDVI_CAPAB_REG_SIZE); 1143 pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0, AMDVI_CAPAB_REG_SIZE); 1144 1145 /* set up MMIO */ --- 55 unchanged lines hidden --- | 1140 qdev_set_parent_bus(DEVICE(&s->pci), &bus->qbus); 1141 object_property_set_bool(OBJECT(&s->pci), true, "realized", err); 1142 s->capab_offset = pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0, 1143 AMDVI_CAPAB_SIZE); 1144 pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, AMDVI_CAPAB_REG_SIZE); 1145 pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0, AMDVI_CAPAB_REG_SIZE); 1146 1147 /* set up MMIO */ --- 55 unchanged lines hidden --- |