1 /* 2 * QEMU emulation of AMD IOMMU (AMD-Vi) 3 * 4 * Copyright (C) 2011 Eduard - Gabriel Munteanu 5 * Copyright (C) 2015 David Kiarie, <davidkiarie4@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Cache implementation inspired by hw/i386/intel_iommu.c 21 */ 22 #include "qemu/osdep.h" 23 #include "hw/i386/amd_iommu.h" 24 #include "trace.h" 25 26 /* used AMD-Vi MMIO registers */ 27 const char *amdvi_mmio_low[] = { 28 "AMDVI_MMIO_DEVTAB_BASE", 29 "AMDVI_MMIO_CMDBUF_BASE", 30 "AMDVI_MMIO_EVTLOG_BASE", 31 "AMDVI_MMIO_CONTROL", 32 "AMDVI_MMIO_EXCL_BASE", 33 "AMDVI_MMIO_EXCL_LIMIT", 34 "AMDVI_MMIO_EXT_FEATURES", 35 "AMDVI_MMIO_PPR_BASE", 36 "UNHANDLED" 37 }; 38 const char *amdvi_mmio_high[] = { 39 "AMDVI_MMIO_COMMAND_HEAD", 40 "AMDVI_MMIO_COMMAND_TAIL", 41 "AMDVI_MMIO_EVTLOG_HEAD", 42 "AMDVI_MMIO_EVTLOG_TAIL", 43 "AMDVI_MMIO_STATUS", 44 "AMDVI_MMIO_PPR_HEAD", 45 "AMDVI_MMIO_PPR_TAIL", 46 "UNHANDLED" 47 }; 48 49 struct AMDVIAddressSpace { 50 uint8_t bus_num; /* bus number */ 51 uint8_t devfn; /* device function */ 52 AMDVIState *iommu_state; /* AMDVI - one per machine */ 53 MemoryRegion iommu; /* Device's address translation region */ 54 MemoryRegion iommu_ir; /* Device's interrupt remapping region */ 55 AddressSpace as; /* device's corresponding address space */ 56 }; 57 58 /* AMDVI cache entry */ 59 typedef struct AMDVIIOTLBEntry { 60 uint16_t domid; /* assigned domain id */ 61 uint16_t devid; /* device owning entry */ 62 uint64_t perms; /* access permissions */ 63 uint64_t translated_addr; /* translated address */ 64 uint64_t page_mask; /* physical page size */ 65 } AMDVIIOTLBEntry; 66 67 /* configure MMIO registers at startup/reset */ 68 static void amdvi_set_quad(AMDVIState *s, hwaddr addr, uint64_t val, 69 uint64_t romask, uint64_t w1cmask) 70 { 71 stq_le_p(&s->mmior[addr], val); 72 stq_le_p(&s->romask[addr], romask); 73 stq_le_p(&s->w1cmask[addr], w1cmask); 74 } 75 76 static uint16_t amdvi_readw(AMDVIState *s, hwaddr addr) 77 { 78 return lduw_le_p(&s->mmior[addr]); 79 } 80 81 static uint32_t amdvi_readl(AMDVIState *s, hwaddr addr) 82 { 83 return ldl_le_p(&s->mmior[addr]); 84 } 85 86 static uint64_t amdvi_readq(AMDVIState *s, hwaddr addr) 87 { 88 return ldq_le_p(&s->mmior[addr]); 89 } 90 91 /* internal write */ 92 static void amdvi_writeq_raw(AMDVIState *s, uint64_t val, hwaddr addr) 93 { 94 stq_le_p(&s->mmior[addr], val); 95 } 96 97 /* external write */ 98 static void amdvi_writew(AMDVIState *s, hwaddr addr, uint16_t val) 99 { 100 uint16_t romask = lduw_le_p(&s->romask[addr]); 101 uint16_t w1cmask = lduw_le_p(&s->w1cmask[addr]); 102 uint16_t oldval = lduw_le_p(&s->mmior[addr]); 103 stw_le_p(&s->mmior[addr], 104 ((oldval & romask) | (val & ~romask)) & ~(val & w1cmask)); 105 } 106 107 static void amdvi_writel(AMDVIState *s, hwaddr addr, uint32_t val) 108 { 109 uint32_t romask = ldl_le_p(&s->romask[addr]); 110 uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]); 111 uint32_t oldval = ldl_le_p(&s->mmior[addr]); 112 stl_le_p(&s->mmior[addr], 113 ((oldval & romask) | (val & ~romask)) & ~(val & w1cmask)); 114 } 115 116 static void amdvi_writeq(AMDVIState *s, hwaddr addr, uint64_t val) 117 { 118 uint64_t romask = ldq_le_p(&s->romask[addr]); 119 uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]); 120 uint32_t oldval = ldq_le_p(&s->mmior[addr]); 121 stq_le_p(&s->mmior[addr], 122 ((oldval & romask) | (val & ~romask)) & ~(val & w1cmask)); 123 } 124 125 /* OR a 64-bit register with a 64-bit value */ 126 static bool amdvi_test_mask(AMDVIState *s, hwaddr addr, uint64_t val) 127 { 128 return amdvi_readq(s, addr) | val; 129 } 130 131 /* OR a 64-bit register with a 64-bit value storing result in the register */ 132 static void amdvi_assign_orq(AMDVIState *s, hwaddr addr, uint64_t val) 133 { 134 amdvi_writeq_raw(s, addr, amdvi_readq(s, addr) | val); 135 } 136 137 /* AND a 64-bit register with a 64-bit value storing result in the register */ 138 static void amdvi_assign_andq(AMDVIState *s, hwaddr addr, uint64_t val) 139 { 140 amdvi_writeq_raw(s, addr, amdvi_readq(s, addr) & val); 141 } 142 143 static void amdvi_generate_msi_interrupt(AMDVIState *s) 144 { 145 MSIMessage msg; 146 MemTxAttrs attrs; 147 148 attrs.requester_id = pci_requester_id(&s->pci.dev); 149 150 if (msi_enabled(&s->pci.dev)) { 151 msg = msi_get_message(&s->pci.dev, 0); 152 address_space_stl_le(&address_space_memory, msg.address, msg.data, 153 attrs, NULL); 154 } 155 } 156 157 static void amdvi_log_event(AMDVIState *s, uint64_t *evt) 158 { 159 /* event logging not enabled */ 160 if (!s->evtlog_enabled || amdvi_test_mask(s, AMDVI_MMIO_STATUS, 161 AMDVI_MMIO_STATUS_EVT_OVF)) { 162 return; 163 } 164 165 /* event log buffer full */ 166 if (s->evtlog_tail >= s->evtlog_len) { 167 amdvi_assign_orq(s, AMDVI_MMIO_STATUS, AMDVI_MMIO_STATUS_EVT_OVF); 168 /* generate interrupt */ 169 amdvi_generate_msi_interrupt(s); 170 return; 171 } 172 173 if (dma_memory_write(&address_space_memory, s->evtlog + s->evtlog_tail, 174 &evt, AMDVI_EVENT_LEN)) { 175 trace_amdvi_evntlog_fail(s->evtlog, s->evtlog_tail); 176 } 177 178 s->evtlog_tail += AMDVI_EVENT_LEN; 179 amdvi_assign_orq(s, AMDVI_MMIO_STATUS, AMDVI_MMIO_STATUS_COMP_INT); 180 amdvi_generate_msi_interrupt(s); 181 } 182 183 static void amdvi_setevent_bits(uint64_t *buffer, uint64_t value, int start, 184 int length) 185 { 186 int index = start / 64, bitpos = start % 64; 187 uint64_t mask = ((1 << length) - 1) << bitpos; 188 buffer[index] &= ~mask; 189 buffer[index] |= (value << bitpos) & mask; 190 } 191 /* 192 * AMDVi event structure 193 * 0:15 -> DeviceID 194 * 55:63 -> event type + miscellaneous info 195 * 63:127 -> related address 196 */ 197 static void amdvi_encode_event(uint64_t *evt, uint16_t devid, uint64_t addr, 198 uint16_t info) 199 { 200 amdvi_setevent_bits(evt, devid, 0, 16); 201 amdvi_setevent_bits(evt, info, 55, 8); 202 amdvi_setevent_bits(evt, addr, 63, 64); 203 } 204 /* log an error encountered during a page walk 205 * 206 * @addr: virtual address in translation request 207 */ 208 static void amdvi_page_fault(AMDVIState *s, uint16_t devid, 209 hwaddr addr, uint16_t info) 210 { 211 uint64_t evt[4]; 212 213 info |= AMDVI_EVENT_IOPF_I | AMDVI_EVENT_IOPF; 214 amdvi_encode_event(evt, devid, addr, info); 215 amdvi_log_event(s, evt); 216 pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, 217 PCI_STATUS_SIG_TARGET_ABORT); 218 } 219 /* 220 * log a master abort accessing device table 221 * @devtab : address of device table entry 222 * @info : error flags 223 */ 224 static void amdvi_log_devtab_error(AMDVIState *s, uint16_t devid, 225 hwaddr devtab, uint16_t info) 226 { 227 uint64_t evt[4]; 228 229 info |= AMDVI_EVENT_DEV_TAB_HW_ERROR; 230 231 amdvi_encode_event(evt, devid, devtab, info); 232 amdvi_log_event(s, evt); 233 pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, 234 PCI_STATUS_SIG_TARGET_ABORT); 235 } 236 /* log an event trying to access command buffer 237 * @addr : address that couldn't be accessed 238 */ 239 static void amdvi_log_command_error(AMDVIState *s, hwaddr addr) 240 { 241 uint64_t evt[4], info = AMDVI_EVENT_COMMAND_HW_ERROR; 242 243 amdvi_encode_event(evt, 0, addr, info); 244 amdvi_log_event(s, evt); 245 pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, 246 PCI_STATUS_SIG_TARGET_ABORT); 247 } 248 /* log an illegal comand event 249 * @addr : address of illegal command 250 */ 251 static void amdvi_log_illegalcom_error(AMDVIState *s, uint16_t info, 252 hwaddr addr) 253 { 254 uint64_t evt[4]; 255 256 info |= AMDVI_EVENT_ILLEGAL_COMMAND_ERROR; 257 amdvi_encode_event(evt, 0, addr, info); 258 amdvi_log_event(s, evt); 259 } 260 /* log an error accessing device table 261 * 262 * @devid : device owning the table entry 263 * @devtab : address of device table entry 264 * @info : error flags 265 */ 266 static void amdvi_log_illegaldevtab_error(AMDVIState *s, uint16_t devid, 267 hwaddr addr, uint16_t info) 268 { 269 uint64_t evt[4]; 270 271 info |= AMDVI_EVENT_ILLEGAL_DEVTAB_ENTRY; 272 amdvi_encode_event(evt, devid, addr, info); 273 amdvi_log_event(s, evt); 274 } 275 /* log an error accessing a PTE entry 276 * @addr : address that couldn't be accessed 277 */ 278 static void amdvi_log_pagetab_error(AMDVIState *s, uint16_t devid, 279 hwaddr addr, uint16_t info) 280 { 281 uint64_t evt[4]; 282 283 info |= AMDVI_EVENT_PAGE_TAB_HW_ERROR; 284 amdvi_encode_event(evt, devid, addr, info); 285 amdvi_log_event(s, evt); 286 pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, 287 PCI_STATUS_SIG_TARGET_ABORT); 288 } 289 290 static gboolean amdvi_uint64_equal(gconstpointer v1, gconstpointer v2) 291 { 292 return *((const uint64_t *)v1) == *((const uint64_t *)v2); 293 } 294 295 static guint amdvi_uint64_hash(gconstpointer v) 296 { 297 return (guint)*(const uint64_t *)v; 298 } 299 300 static AMDVIIOTLBEntry *amdvi_iotlb_lookup(AMDVIState *s, hwaddr addr, 301 uint64_t devid) 302 { 303 uint64_t key = (addr >> AMDVI_PAGE_SHIFT_4K) | 304 ((uint64_t)(devid) << AMDVI_DEVID_SHIFT); 305 return g_hash_table_lookup(s->iotlb, &key); 306 } 307 308 static void amdvi_iotlb_reset(AMDVIState *s) 309 { 310 assert(s->iotlb); 311 trace_amdvi_iotlb_reset(); 312 g_hash_table_remove_all(s->iotlb); 313 } 314 315 static gboolean amdvi_iotlb_remove_by_devid(gpointer key, gpointer value, 316 gpointer user_data) 317 { 318 AMDVIIOTLBEntry *entry = (AMDVIIOTLBEntry *)value; 319 uint16_t devid = *(uint16_t *)user_data; 320 return entry->devid == devid; 321 } 322 323 static void amdvi_iotlb_remove_page(AMDVIState *s, hwaddr addr, 324 uint64_t devid) 325 { 326 uint64_t key = (addr >> AMDVI_PAGE_SHIFT_4K) | 327 ((uint64_t)(devid) << AMDVI_DEVID_SHIFT); 328 g_hash_table_remove(s->iotlb, &key); 329 } 330 331 static void amdvi_update_iotlb(AMDVIState *s, uint16_t devid, 332 uint64_t gpa, IOMMUTLBEntry to_cache, 333 uint16_t domid) 334 { 335 AMDVIIOTLBEntry *entry = g_malloc(sizeof(*entry)); 336 uint64_t *key = g_malloc(sizeof(key)); 337 uint64_t gfn = gpa >> AMDVI_PAGE_SHIFT_4K; 338 339 /* don't cache erroneous translations */ 340 if (to_cache.perm != IOMMU_NONE) { 341 trace_amdvi_cache_update(domid, PCI_BUS_NUM(devid), PCI_SLOT(devid), 342 PCI_FUNC(devid), gpa, to_cache.translated_addr); 343 344 if (g_hash_table_size(s->iotlb) >= AMDVI_IOTLB_MAX_SIZE) { 345 amdvi_iotlb_reset(s); 346 } 347 348 entry->domid = domid; 349 entry->perms = to_cache.perm; 350 entry->translated_addr = to_cache.translated_addr; 351 entry->page_mask = to_cache.addr_mask; 352 *key = gfn | ((uint64_t)(devid) << AMDVI_DEVID_SHIFT); 353 g_hash_table_replace(s->iotlb, key, entry); 354 } 355 } 356 357 static void amdvi_completion_wait(AMDVIState *s, uint64_t *cmd) 358 { 359 /* pad the last 3 bits */ 360 hwaddr addr = cpu_to_le64(extract64(cmd[0], 3, 49)) << 3; 361 uint64_t data = cpu_to_le64(cmd[1]); 362 363 if (extract64(cmd[0], 51, 8)) { 364 amdvi_log_illegalcom_error(s, extract64(cmd[0], 60, 4), 365 s->cmdbuf + s->cmdbuf_head); 366 } 367 if (extract64(cmd[0], 0, 1)) { 368 if (dma_memory_write(&address_space_memory, addr, &data, 369 AMDVI_COMPLETION_DATA_SIZE)) { 370 trace_amdvi_completion_wait_fail(addr); 371 } 372 } 373 /* set completion interrupt */ 374 if (extract64(cmd[0], 1, 1)) { 375 amdvi_test_mask(s, AMDVI_MMIO_STATUS, AMDVI_MMIO_STATUS_COMP_INT); 376 /* generate interrupt */ 377 amdvi_generate_msi_interrupt(s); 378 } 379 trace_amdvi_completion_wait(addr, data); 380 } 381 382 /* log error without aborting since linux seems to be using reserved bits */ 383 static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) 384 { 385 uint16_t devid = cpu_to_le16((uint16_t)extract64(cmd[0], 0, 16)); 386 387 /* This command should invalidate internal caches of which there isn't */ 388 if (extract64(cmd[0], 15, 16) || cmd[1]) { 389 amdvi_log_illegalcom_error(s, extract64(cmd[0], 60, 4), 390 s->cmdbuf + s->cmdbuf_head); 391 } 392 trace_amdvi_devtab_inval(PCI_BUS_NUM(devid), PCI_SLOT(devid), 393 PCI_FUNC(devid)); 394 } 395 396 static void amdvi_complete_ppr(AMDVIState *s, uint64_t *cmd) 397 { 398 if (extract64(cmd[0], 15, 16) || extract64(cmd[0], 19, 8) || 399 extract64(cmd[1], 0, 2) || extract64(cmd[1], 3, 29) 400 || extract64(cmd[1], 47, 16)) { 401 amdvi_log_illegalcom_error(s, extract64(cmd[0], 60, 4), 402 s->cmdbuf + s->cmdbuf_head); 403 } 404 trace_amdvi_ppr_exec(); 405 } 406 407 static void amdvi_inval_all(AMDVIState *s, uint64_t *cmd) 408 { 409 if (extract64(cmd[0], 0, 60) || cmd[1]) { 410 amdvi_log_illegalcom_error(s, extract64(cmd[0], 60, 4), 411 s->cmdbuf + s->cmdbuf_head); 412 } 413 414 amdvi_iotlb_reset(s); 415 trace_amdvi_all_inval(); 416 } 417 418 static gboolean amdvi_iotlb_remove_by_domid(gpointer key, gpointer value, 419 gpointer user_data) 420 { 421 AMDVIIOTLBEntry *entry = (AMDVIIOTLBEntry *)value; 422 uint16_t domid = *(uint16_t *)user_data; 423 return entry->domid == domid; 424 } 425 426 /* we don't have devid - we can't remove pages by address */ 427 static void amdvi_inval_pages(AMDVIState *s, uint64_t *cmd) 428 { 429 uint16_t domid = cpu_to_le16((uint16_t)extract64(cmd[0], 32, 16)); 430 431 if (extract64(cmd[0], 20, 12) || extract64(cmd[0], 16, 12) || 432 extract64(cmd[0], 3, 10)) { 433 amdvi_log_illegalcom_error(s, extract64(cmd[0], 60, 4), 434 s->cmdbuf + s->cmdbuf_head); 435 } 436 437 g_hash_table_foreach_remove(s->iotlb, amdvi_iotlb_remove_by_domid, 438 &domid); 439 trace_amdvi_pages_inval(domid); 440 } 441 442 static void amdvi_prefetch_pages(AMDVIState *s, uint64_t *cmd) 443 { 444 if (extract64(cmd[0], 16, 8) || extract64(cmd[0], 20, 8) || 445 extract64(cmd[1], 1, 1) || extract64(cmd[1], 3, 1) || 446 extract64(cmd[1], 5, 7)) { 447 amdvi_log_illegalcom_error(s, extract64(cmd[0], 60, 4), 448 s->cmdbuf + s->cmdbuf_head); 449 } 450 451 trace_amdvi_prefetch_pages(); 452 } 453 454 static void amdvi_inval_inttable(AMDVIState *s, uint64_t *cmd) 455 { 456 if (extract64(cmd[0], 16, 16) || cmd[1]) { 457 amdvi_log_illegalcom_error(s, extract64(cmd[0], 60, 4), 458 s->cmdbuf + s->cmdbuf_head); 459 return; 460 } 461 462 trace_amdvi_intr_inval(); 463 } 464 465 /* FIXME: Try to work with the specified size instead of all the pages 466 * when the S bit is on 467 */ 468 static void iommu_inval_iotlb(AMDVIState *s, uint64_t *cmd) 469 { 470 471 uint16_t devid = extract64(cmd[0], 0, 16); 472 if (extract64(cmd[1], 1, 1) || extract64(cmd[1], 3, 9)) { 473 amdvi_log_illegalcom_error(s, extract64(cmd[0], 60, 4), 474 s->cmdbuf + s->cmdbuf_head); 475 return; 476 } 477 478 if (extract64(cmd[1], 0, 1)) { 479 g_hash_table_foreach_remove(s->iotlb, amdvi_iotlb_remove_by_devid, 480 &devid); 481 } else { 482 amdvi_iotlb_remove_page(s, cpu_to_le64(extract64(cmd[1], 12, 52)) << 12, 483 cpu_to_le16(extract64(cmd[1], 0, 16))); 484 } 485 trace_amdvi_iotlb_inval(); 486 } 487 488 /* not honouring reserved bits is regarded as an illegal command */ 489 static void amdvi_cmdbuf_exec(AMDVIState *s) 490 { 491 uint64_t cmd[2]; 492 493 if (dma_memory_read(&address_space_memory, s->cmdbuf + s->cmdbuf_head, 494 cmd, AMDVI_COMMAND_SIZE)) { 495 trace_amdvi_command_read_fail(s->cmdbuf, s->cmdbuf_head); 496 amdvi_log_command_error(s, s->cmdbuf + s->cmdbuf_head); 497 return; 498 } 499 500 switch (extract64(cmd[0], 60, 4)) { 501 case AMDVI_CMD_COMPLETION_WAIT: 502 amdvi_completion_wait(s, cmd); 503 break; 504 case AMDVI_CMD_INVAL_DEVTAB_ENTRY: 505 amdvi_inval_devtab_entry(s, cmd); 506 break; 507 case AMDVI_CMD_INVAL_AMDVI_PAGES: 508 amdvi_inval_pages(s, cmd); 509 break; 510 case AMDVI_CMD_INVAL_IOTLB_PAGES: 511 iommu_inval_iotlb(s, cmd); 512 break; 513 case AMDVI_CMD_INVAL_INTR_TABLE: 514 amdvi_inval_inttable(s, cmd); 515 break; 516 case AMDVI_CMD_PREFETCH_AMDVI_PAGES: 517 amdvi_prefetch_pages(s, cmd); 518 break; 519 case AMDVI_CMD_COMPLETE_PPR_REQUEST: 520 amdvi_complete_ppr(s, cmd); 521 break; 522 case AMDVI_CMD_INVAL_AMDVI_ALL: 523 amdvi_inval_all(s, cmd); 524 break; 525 default: 526 trace_amdvi_unhandled_command(extract64(cmd[1], 60, 4)); 527 /* log illegal command */ 528 amdvi_log_illegalcom_error(s, extract64(cmd[1], 60, 4), 529 s->cmdbuf + s->cmdbuf_head); 530 } 531 } 532 533 static void amdvi_cmdbuf_run(AMDVIState *s) 534 { 535 if (!s->cmdbuf_enabled) { 536 trace_amdvi_command_error(amdvi_readq(s, AMDVI_MMIO_CONTROL)); 537 return; 538 } 539 540 /* check if there is work to do. */ 541 while (s->cmdbuf_head != s->cmdbuf_tail) { 542 trace_amdvi_command_exec(s->cmdbuf_head, s->cmdbuf_tail, s->cmdbuf); 543 amdvi_cmdbuf_exec(s); 544 s->cmdbuf_head += AMDVI_COMMAND_SIZE; 545 amdvi_writeq_raw(s, s->cmdbuf_head, AMDVI_MMIO_COMMAND_HEAD); 546 547 /* wrap head pointer */ 548 if (s->cmdbuf_head >= s->cmdbuf_len * AMDVI_COMMAND_SIZE) { 549 s->cmdbuf_head = 0; 550 } 551 } 552 } 553 554 static void amdvi_mmio_trace(hwaddr addr, unsigned size) 555 { 556 uint8_t index = (addr & ~0x2000) / 8; 557 558 if ((addr & 0x2000)) { 559 /* high table */ 560 index = index >= AMDVI_MMIO_REGS_HIGH ? AMDVI_MMIO_REGS_HIGH : index; 561 trace_amdvi_mmio_read(amdvi_mmio_high[index], addr, size, addr & ~0x07); 562 } else { 563 index = index >= AMDVI_MMIO_REGS_LOW ? AMDVI_MMIO_REGS_LOW : index; 564 trace_amdvi_mmio_read(amdvi_mmio_high[index], addr, size, addr & ~0x07); 565 } 566 } 567 568 static uint64_t amdvi_mmio_read(void *opaque, hwaddr addr, unsigned size) 569 { 570 AMDVIState *s = opaque; 571 572 uint64_t val = -1; 573 if (addr + size > AMDVI_MMIO_SIZE) { 574 trace_amdvi_mmio_read("error: addr outside region: max ", 575 (uint64_t)AMDVI_MMIO_SIZE, addr, size); 576 return (uint64_t)-1; 577 } 578 579 if (size == 2) { 580 val = amdvi_readw(s, addr); 581 } else if (size == 4) { 582 val = amdvi_readl(s, addr); 583 } else if (size == 8) { 584 val = amdvi_readq(s, addr); 585 } 586 amdvi_mmio_trace(addr, size); 587 588 return val; 589 } 590 591 static void amdvi_handle_control_write(AMDVIState *s) 592 { 593 unsigned long control = amdvi_readq(s, AMDVI_MMIO_CONTROL); 594 s->enabled = !!(control & AMDVI_MMIO_CONTROL_AMDVIEN); 595 596 s->ats_enabled = !!(control & AMDVI_MMIO_CONTROL_HTTUNEN); 597 s->evtlog_enabled = s->enabled && !!(control & 598 AMDVI_MMIO_CONTROL_EVENTLOGEN); 599 600 s->evtlog_intr = !!(control & AMDVI_MMIO_CONTROL_EVENTINTEN); 601 s->completion_wait_intr = !!(control & AMDVI_MMIO_CONTROL_COMWAITINTEN); 602 s->cmdbuf_enabled = s->enabled && !!(control & 603 AMDVI_MMIO_CONTROL_CMDBUFLEN); 604 605 /* update the flags depending on the control register */ 606 if (s->cmdbuf_enabled) { 607 amdvi_assign_orq(s, AMDVI_MMIO_STATUS, AMDVI_MMIO_STATUS_CMDBUF_RUN); 608 } else { 609 amdvi_assign_andq(s, AMDVI_MMIO_STATUS, ~AMDVI_MMIO_STATUS_CMDBUF_RUN); 610 } 611 if (s->evtlog_enabled) { 612 amdvi_assign_orq(s, AMDVI_MMIO_STATUS, AMDVI_MMIO_STATUS_EVT_RUN); 613 } else { 614 amdvi_assign_andq(s, AMDVI_MMIO_STATUS, ~AMDVI_MMIO_STATUS_EVT_RUN); 615 } 616 617 trace_amdvi_control_status(control); 618 amdvi_cmdbuf_run(s); 619 } 620 621 static inline void amdvi_handle_devtab_write(AMDVIState *s) 622 623 { 624 uint64_t val = amdvi_readq(s, AMDVI_MMIO_DEVICE_TABLE); 625 s->devtab = (val & AMDVI_MMIO_DEVTAB_BASE_MASK); 626 627 /* set device table length */ 628 s->devtab_len = ((val & AMDVI_MMIO_DEVTAB_SIZE_MASK) + 1 * 629 (AMDVI_MMIO_DEVTAB_SIZE_UNIT / 630 AMDVI_MMIO_DEVTAB_ENTRY_SIZE)); 631 } 632 633 static inline void amdvi_handle_cmdhead_write(AMDVIState *s) 634 { 635 s->cmdbuf_head = amdvi_readq(s, AMDVI_MMIO_COMMAND_HEAD) 636 & AMDVI_MMIO_CMDBUF_HEAD_MASK; 637 amdvi_cmdbuf_run(s); 638 } 639 640 static inline void amdvi_handle_cmdbase_write(AMDVIState *s) 641 { 642 s->cmdbuf = amdvi_readq(s, AMDVI_MMIO_COMMAND_BASE) 643 & AMDVI_MMIO_CMDBUF_BASE_MASK; 644 s->cmdbuf_len = 1UL << (amdvi_readq(s, AMDVI_MMIO_CMDBUF_SIZE_BYTE) 645 & AMDVI_MMIO_CMDBUF_SIZE_MASK); 646 s->cmdbuf_head = s->cmdbuf_tail = 0; 647 } 648 649 static inline void amdvi_handle_cmdtail_write(AMDVIState *s) 650 { 651 s->cmdbuf_tail = amdvi_readq(s, AMDVI_MMIO_COMMAND_TAIL) 652 & AMDVI_MMIO_CMDBUF_TAIL_MASK; 653 amdvi_cmdbuf_run(s); 654 } 655 656 static inline void amdvi_handle_excllim_write(AMDVIState *s) 657 { 658 uint64_t val = amdvi_readq(s, AMDVI_MMIO_EXCL_LIMIT); 659 s->excl_limit = (val & AMDVI_MMIO_EXCL_LIMIT_MASK) | 660 AMDVI_MMIO_EXCL_LIMIT_LOW; 661 } 662 663 static inline void amdvi_handle_evtbase_write(AMDVIState *s) 664 { 665 uint64_t val = amdvi_readq(s, AMDVI_MMIO_EVENT_BASE); 666 s->evtlog = val & AMDVI_MMIO_EVTLOG_BASE_MASK; 667 s->evtlog_len = 1UL << (amdvi_readq(s, AMDVI_MMIO_EVTLOG_SIZE_BYTE) 668 & AMDVI_MMIO_EVTLOG_SIZE_MASK); 669 } 670 671 static inline void amdvi_handle_evttail_write(AMDVIState *s) 672 { 673 uint64_t val = amdvi_readq(s, AMDVI_MMIO_EVENT_TAIL); 674 s->evtlog_tail = val & AMDVI_MMIO_EVTLOG_TAIL_MASK; 675 } 676 677 static inline void amdvi_handle_evthead_write(AMDVIState *s) 678 { 679 uint64_t val = amdvi_readq(s, AMDVI_MMIO_EVENT_HEAD); 680 s->evtlog_head = val & AMDVI_MMIO_EVTLOG_HEAD_MASK; 681 } 682 683 static inline void amdvi_handle_pprbase_write(AMDVIState *s) 684 { 685 uint64_t val = amdvi_readq(s, AMDVI_MMIO_PPR_BASE); 686 s->ppr_log = val & AMDVI_MMIO_PPRLOG_BASE_MASK; 687 s->pprlog_len = 1UL << (amdvi_readq(s, AMDVI_MMIO_PPRLOG_SIZE_BYTE) 688 & AMDVI_MMIO_PPRLOG_SIZE_MASK); 689 } 690 691 static inline void amdvi_handle_pprhead_write(AMDVIState *s) 692 { 693 uint64_t val = amdvi_readq(s, AMDVI_MMIO_PPR_HEAD); 694 s->pprlog_head = val & AMDVI_MMIO_PPRLOG_HEAD_MASK; 695 } 696 697 static inline void amdvi_handle_pprtail_write(AMDVIState *s) 698 { 699 uint64_t val = amdvi_readq(s, AMDVI_MMIO_PPR_TAIL); 700 s->pprlog_tail = val & AMDVI_MMIO_PPRLOG_TAIL_MASK; 701 } 702 703 /* FIXME: something might go wrong if System Software writes in chunks 704 * of one byte but linux writes in chunks of 4 bytes so currently it 705 * works correctly with linux but will definitely be busted if software 706 * reads/writes 8 bytes 707 */ 708 static void amdvi_mmio_reg_write(AMDVIState *s, unsigned size, uint64_t val, 709 hwaddr addr) 710 { 711 if (size == 2) { 712 amdvi_writew(s, addr, val); 713 } else if (size == 4) { 714 amdvi_writel(s, addr, val); 715 } else if (size == 8) { 716 amdvi_writeq(s, addr, val); 717 } 718 } 719 720 static void amdvi_mmio_write(void *opaque, hwaddr addr, uint64_t val, 721 unsigned size) 722 { 723 AMDVIState *s = opaque; 724 unsigned long offset = addr & 0x07; 725 726 if (addr + size > AMDVI_MMIO_SIZE) { 727 trace_amdvi_mmio_write("error: addr outside region: max ", 728 (uint64_t)AMDVI_MMIO_SIZE, size, val, offset); 729 return; 730 } 731 732 amdvi_mmio_trace(addr, size); 733 switch (addr & ~0x07) { 734 case AMDVI_MMIO_CONTROL: 735 amdvi_mmio_reg_write(s, size, val, addr); 736 amdvi_handle_control_write(s); 737 break; 738 case AMDVI_MMIO_DEVICE_TABLE: 739 amdvi_mmio_reg_write(s, size, val, addr); 740 /* set device table address 741 * This also suffers from inability to tell whether software 742 * is done writing 743 */ 744 if (offset || (size == 8)) { 745 amdvi_handle_devtab_write(s); 746 } 747 break; 748 case AMDVI_MMIO_COMMAND_HEAD: 749 amdvi_mmio_reg_write(s, size, val, addr); 750 amdvi_handle_cmdhead_write(s); 751 break; 752 case AMDVI_MMIO_COMMAND_BASE: 753 amdvi_mmio_reg_write(s, size, val, addr); 754 /* FIXME - make sure System Software has finished writing incase 755 * it writes in chucks less than 8 bytes in a robust way.As for 756 * now, this hacks works for the linux driver 757 */ 758 if (offset || (size == 8)) { 759 amdvi_handle_cmdbase_write(s); 760 } 761 break; 762 case AMDVI_MMIO_COMMAND_TAIL: 763 amdvi_mmio_reg_write(s, size, val, addr); 764 amdvi_handle_cmdtail_write(s); 765 break; 766 case AMDVI_MMIO_EVENT_BASE: 767 amdvi_mmio_reg_write(s, size, val, addr); 768 amdvi_handle_evtbase_write(s); 769 break; 770 case AMDVI_MMIO_EVENT_HEAD: 771 amdvi_mmio_reg_write(s, size, val, addr); 772 amdvi_handle_evthead_write(s); 773 break; 774 case AMDVI_MMIO_EVENT_TAIL: 775 amdvi_mmio_reg_write(s, size, val, addr); 776 amdvi_handle_evttail_write(s); 777 break; 778 case AMDVI_MMIO_EXCL_LIMIT: 779 amdvi_mmio_reg_write(s, size, val, addr); 780 amdvi_handle_excllim_write(s); 781 break; 782 /* PPR log base - unused for now */ 783 case AMDVI_MMIO_PPR_BASE: 784 amdvi_mmio_reg_write(s, size, val, addr); 785 amdvi_handle_pprbase_write(s); 786 break; 787 /* PPR log head - also unused for now */ 788 case AMDVI_MMIO_PPR_HEAD: 789 amdvi_mmio_reg_write(s, size, val, addr); 790 amdvi_handle_pprhead_write(s); 791 break; 792 /* PPR log tail - unused for now */ 793 case AMDVI_MMIO_PPR_TAIL: 794 amdvi_mmio_reg_write(s, size, val, addr); 795 amdvi_handle_pprtail_write(s); 796 break; 797 } 798 } 799 800 static inline uint64_t amdvi_get_perms(uint64_t entry) 801 { 802 return (entry & (AMDVI_DEV_PERM_READ | AMDVI_DEV_PERM_WRITE)) >> 803 AMDVI_DEV_PERM_SHIFT; 804 } 805 806 /* a valid entry should have V = 1 and reserved bits honoured */ 807 static bool amdvi_validate_dte(AMDVIState *s, uint16_t devid, 808 uint64_t *dte) 809 { 810 if ((dte[0] & AMDVI_DTE_LOWER_QUAD_RESERVED) 811 || (dte[1] & AMDVI_DTE_MIDDLE_QUAD_RESERVED) 812 || (dte[2] & AMDVI_DTE_UPPER_QUAD_RESERVED) || dte[3]) { 813 amdvi_log_illegaldevtab_error(s, devid, 814 s->devtab + 815 devid * AMDVI_DEVTAB_ENTRY_SIZE, 0); 816 return false; 817 } 818 819 return dte[0] & AMDVI_DEV_VALID; 820 } 821 822 /* get a device table entry given the devid */ 823 static bool amdvi_get_dte(AMDVIState *s, int devid, uint64_t *entry) 824 { 825 uint32_t offset = devid * AMDVI_DEVTAB_ENTRY_SIZE; 826 827 if (dma_memory_read(&address_space_memory, s->devtab + offset, entry, 828 AMDVI_DEVTAB_ENTRY_SIZE)) { 829 trace_amdvi_dte_get_fail(s->devtab, offset); 830 /* log error accessing dte */ 831 amdvi_log_devtab_error(s, devid, s->devtab + offset, 0); 832 return false; 833 } 834 835 *entry = le64_to_cpu(*entry); 836 if (!amdvi_validate_dte(s, devid, entry)) { 837 trace_amdvi_invalid_dte(entry[0]); 838 return false; 839 } 840 841 return true; 842 } 843 844 /* get pte translation mode */ 845 static inline uint8_t get_pte_translation_mode(uint64_t pte) 846 { 847 return (pte >> AMDVI_DEV_MODE_RSHIFT) & AMDVI_DEV_MODE_MASK; 848 } 849 850 static inline uint64_t pte_override_page_mask(uint64_t pte) 851 { 852 uint8_t page_mask = 12; 853 uint64_t addr = (pte & AMDVI_DEV_PT_ROOT_MASK) ^ AMDVI_DEV_PT_ROOT_MASK; 854 /* find the first zero bit */ 855 while (addr & 1) { 856 page_mask++; 857 addr = addr >> 1; 858 } 859 860 return ~((1ULL << page_mask) - 1); 861 } 862 863 static inline uint64_t pte_get_page_mask(uint64_t oldlevel) 864 { 865 return ~((1UL << ((oldlevel * 9) + 3)) - 1); 866 } 867 868 static inline uint64_t amdvi_get_pte_entry(AMDVIState *s, uint64_t pte_addr, 869 uint16_t devid) 870 { 871 uint64_t pte; 872 873 if (dma_memory_read(&address_space_memory, pte_addr, &pte, sizeof(pte))) { 874 trace_amdvi_get_pte_hwerror(pte_addr); 875 amdvi_log_pagetab_error(s, devid, pte_addr, 0); 876 pte = 0; 877 return pte; 878 } 879 880 pte = le64_to_cpu(pte); 881 return pte; 882 } 883 884 static void amdvi_page_walk(AMDVIAddressSpace *as, uint64_t *dte, 885 IOMMUTLBEntry *ret, unsigned perms, 886 hwaddr addr) 887 { 888 unsigned level, present, pte_perms, oldlevel; 889 uint64_t pte = dte[0], pte_addr, page_mask; 890 891 /* make sure the DTE has TV = 1 */ 892 if (pte & AMDVI_DEV_TRANSLATION_VALID) { 893 level = get_pte_translation_mode(pte); 894 if (level >= 7) { 895 trace_amdvi_mode_invalid(level, addr); 896 return; 897 } 898 if (level == 0) { 899 goto no_remap; 900 } 901 902 /* we are at the leaf page table or page table encodes a huge page */ 903 while (level > 0) { 904 pte_perms = amdvi_get_perms(pte); 905 present = pte & 1; 906 if (!present || perms != (perms & pte_perms)) { 907 amdvi_page_fault(as->iommu_state, as->devfn, addr, perms); 908 trace_amdvi_page_fault(addr); 909 return; 910 } 911 912 /* go to the next lower level */ 913 pte_addr = pte & AMDVI_DEV_PT_ROOT_MASK; 914 /* add offset and load pte */ 915 pte_addr += ((addr >> (3 + 9 * level)) & 0x1FF) << 3; 916 pte = amdvi_get_pte_entry(as->iommu_state, pte_addr, as->devfn); 917 if (!pte) { 918 return; 919 } 920 oldlevel = level; 921 level = get_pte_translation_mode(pte); 922 if (level == 0x7) { 923 break; 924 } 925 } 926 927 if (level == 0x7) { 928 page_mask = pte_override_page_mask(pte); 929 } else { 930 page_mask = pte_get_page_mask(oldlevel); 931 } 932 933 /* get access permissions from pte */ 934 ret->iova = addr & page_mask; 935 ret->translated_addr = (pte & AMDVI_DEV_PT_ROOT_MASK) & page_mask; 936 ret->addr_mask = ~page_mask; 937 ret->perm = amdvi_get_perms(pte); 938 return; 939 } 940 no_remap: 941 ret->iova = addr & AMDVI_PAGE_MASK_4K; 942 ret->translated_addr = addr & AMDVI_PAGE_MASK_4K; 943 ret->addr_mask = ~AMDVI_PAGE_MASK_4K; 944 ret->perm = amdvi_get_perms(pte); 945 } 946 947 static void amdvi_do_translate(AMDVIAddressSpace *as, hwaddr addr, 948 bool is_write, IOMMUTLBEntry *ret) 949 { 950 AMDVIState *s = as->iommu_state; 951 uint16_t devid = PCI_BUILD_BDF(as->bus_num, as->devfn); 952 AMDVIIOTLBEntry *iotlb_entry = amdvi_iotlb_lookup(s, addr, devid); 953 uint64_t entry[4]; 954 955 if (iotlb_entry) { 956 trace_amdvi_iotlb_hit(PCI_BUS_NUM(devid), PCI_SLOT(devid), 957 PCI_FUNC(devid), addr, iotlb_entry->translated_addr); 958 ret->iova = addr & ~iotlb_entry->page_mask; 959 ret->translated_addr = iotlb_entry->translated_addr; 960 ret->addr_mask = iotlb_entry->page_mask; 961 ret->perm = iotlb_entry->perms; 962 return; 963 } 964 965 /* devices with V = 0 are not translated */ 966 if (!amdvi_get_dte(s, devid, entry)) { 967 goto out; 968 } 969 970 amdvi_page_walk(as, entry, ret, 971 is_write ? AMDVI_PERM_WRITE : AMDVI_PERM_READ, addr); 972 973 amdvi_update_iotlb(s, devid, addr, *ret, 974 entry[1] & AMDVI_DEV_DOMID_ID_MASK); 975 return; 976 977 out: 978 ret->iova = addr & AMDVI_PAGE_MASK_4K; 979 ret->translated_addr = addr & AMDVI_PAGE_MASK_4K; 980 ret->addr_mask = ~AMDVI_PAGE_MASK_4K; 981 ret->perm = IOMMU_RW; 982 } 983 984 static inline bool amdvi_is_interrupt_addr(hwaddr addr) 985 { 986 return addr >= AMDVI_INT_ADDR_FIRST && addr <= AMDVI_INT_ADDR_LAST; 987 } 988 989 static IOMMUTLBEntry amdvi_translate(MemoryRegion *iommu, hwaddr addr, 990 bool is_write) 991 { 992 AMDVIAddressSpace *as = container_of(iommu, AMDVIAddressSpace, iommu); 993 AMDVIState *s = as->iommu_state; 994 IOMMUTLBEntry ret = { 995 .target_as = &address_space_memory, 996 .iova = addr, 997 .translated_addr = 0, 998 .addr_mask = ~(hwaddr)0, 999 .perm = IOMMU_NONE 1000 }; 1001 1002 if (!s->enabled) { 1003 /* AMDVI disabled - corresponds to iommu=off not 1004 * failure to provide any parameter 1005 */ 1006 ret.iova = addr & AMDVI_PAGE_MASK_4K; 1007 ret.translated_addr = addr & AMDVI_PAGE_MASK_4K; 1008 ret.addr_mask = ~AMDVI_PAGE_MASK_4K; 1009 ret.perm = IOMMU_RW; 1010 return ret; 1011 } else if (amdvi_is_interrupt_addr(addr)) { 1012 ret.iova = addr & AMDVI_PAGE_MASK_4K; 1013 ret.translated_addr = addr & AMDVI_PAGE_MASK_4K; 1014 ret.addr_mask = ~AMDVI_PAGE_MASK_4K; 1015 ret.perm = IOMMU_WO; 1016 return ret; 1017 } 1018 1019 amdvi_do_translate(as, addr, is_write, &ret); 1020 trace_amdvi_translation_result(as->bus_num, PCI_SLOT(as->devfn), 1021 PCI_FUNC(as->devfn), addr, ret.translated_addr); 1022 return ret; 1023 } 1024 1025 static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) 1026 { 1027 AMDVIState *s = opaque; 1028 AMDVIAddressSpace **iommu_as; 1029 int bus_num = pci_bus_num(bus); 1030 1031 iommu_as = s->address_spaces[bus_num]; 1032 1033 /* allocate memory during the first run */ 1034 if (!iommu_as) { 1035 iommu_as = g_malloc0(sizeof(AMDVIAddressSpace *) * PCI_DEVFN_MAX); 1036 s->address_spaces[bus_num] = iommu_as; 1037 } 1038 1039 /* set up AMD-Vi region */ 1040 if (!iommu_as[devfn]) { 1041 iommu_as[devfn] = g_malloc0(sizeof(AMDVIAddressSpace)); 1042 iommu_as[devfn]->bus_num = (uint8_t)bus_num; 1043 iommu_as[devfn]->devfn = (uint8_t)devfn; 1044 iommu_as[devfn]->iommu_state = s; 1045 1046 memory_region_init_iommu(&iommu_as[devfn]->iommu, OBJECT(s), 1047 &s->iommu_ops, "amd-iommu", UINT64_MAX); 1048 address_space_init(&iommu_as[devfn]->as, &iommu_as[devfn]->iommu, 1049 "amd-iommu"); 1050 } 1051 return &iommu_as[devfn]->as; 1052 } 1053 1054 static const MemoryRegionOps mmio_mem_ops = { 1055 .read = amdvi_mmio_read, 1056 .write = amdvi_mmio_write, 1057 .endianness = DEVICE_LITTLE_ENDIAN, 1058 .impl = { 1059 .min_access_size = 1, 1060 .max_access_size = 8, 1061 .unaligned = false, 1062 }, 1063 .valid = { 1064 .min_access_size = 1, 1065 .max_access_size = 8, 1066 } 1067 }; 1068 1069 static void amdvi_iommu_notify_started(MemoryRegion *iommu) 1070 { 1071 AMDVIAddressSpace *as = container_of(iommu, AMDVIAddressSpace, iommu); 1072 1073 hw_error("device %02x.%02x.%x requires iommu notifier which is not " 1074 "currently supported", as->bus_num, PCI_SLOT(as->devfn), 1075 PCI_FUNC(as->devfn)); 1076 } 1077 1078 static void amdvi_init(AMDVIState *s) 1079 { 1080 amdvi_iotlb_reset(s); 1081 1082 s->iommu_ops.translate = amdvi_translate; 1083 s->iommu_ops.notify_started = amdvi_iommu_notify_started; 1084 s->devtab_len = 0; 1085 s->cmdbuf_len = 0; 1086 s->cmdbuf_head = 0; 1087 s->cmdbuf_tail = 0; 1088 s->evtlog_head = 0; 1089 s->evtlog_tail = 0; 1090 s->excl_enabled = false; 1091 s->excl_allow = false; 1092 s->mmio_enabled = false; 1093 s->enabled = false; 1094 s->ats_enabled = false; 1095 s->cmdbuf_enabled = false; 1096 1097 /* reset MMIO */ 1098 memset(s->mmior, 0, AMDVI_MMIO_SIZE); 1099 amdvi_set_quad(s, AMDVI_MMIO_EXT_FEATURES, AMDVI_EXT_FEATURES, 1100 0xffffffffffffffef, 0); 1101 amdvi_set_quad(s, AMDVI_MMIO_STATUS, 0, 0x98, 0x67); 1102 1103 /* reset device ident */ 1104 pci_config_set_vendor_id(s->pci.dev.config, PCI_VENDOR_ID_AMD); 1105 pci_config_set_prog_interface(s->pci.dev.config, 00); 1106 pci_config_set_device_id(s->pci.dev.config, s->devid); 1107 pci_config_set_class(s->pci.dev.config, 0x0806); 1108 1109 /* reset AMDVI specific capabilities, all r/o */ 1110 pci_set_long(s->pci.dev.config + s->capab_offset, AMDVI_CAPAB_FEATURES); 1111 pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_BAR_LOW, 1112 s->mmio.addr & ~(0xffff0000)); 1113 pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_BAR_HIGH, 1114 (s->mmio.addr & ~(0xffff)) >> 16); 1115 pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_RANGE, 1116 0xff000000); 1117 pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_MISC, 0); 1118 pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_MISC, 1119 AMDVI_MAX_PH_ADDR | AMDVI_MAX_GVA_ADDR | AMDVI_MAX_VA_ADDR); 1120 } 1121 1122 static void amdvi_reset(DeviceState *dev) 1123 { 1124 AMDVIState *s = AMD_IOMMU_DEVICE(dev); 1125 1126 msi_reset(&s->pci.dev); 1127 amdvi_init(s); 1128 } 1129 1130 static void amdvi_realize(DeviceState *dev, Error **err) 1131 { 1132 AMDVIState *s = AMD_IOMMU_DEVICE(dev); 1133 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev); 1134 PCIBus *bus = PC_MACHINE(qdev_get_machine())->bus; 1135 s->iotlb = g_hash_table_new_full(amdvi_uint64_hash, 1136 amdvi_uint64_equal, g_free, g_free); 1137 1138 /* This device should take care of IOMMU PCI properties */ 1139 x86_iommu->type = TYPE_AMD; 1140 qdev_set_parent_bus(DEVICE(&s->pci), &bus->qbus); 1141 object_property_set_bool(OBJECT(&s->pci), true, "realized", err); 1142 s->capab_offset = pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0, 1143 AMDVI_CAPAB_SIZE); 1144 pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, AMDVI_CAPAB_REG_SIZE); 1145 pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0, AMDVI_CAPAB_REG_SIZE); 1146 1147 /* set up MMIO */ 1148 memory_region_init_io(&s->mmio, OBJECT(s), &mmio_mem_ops, s, "amdvi-mmio", 1149 AMDVI_MMIO_SIZE); 1150 1151 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio); 1152 sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, AMDVI_BASE_ADDR); 1153 pci_setup_iommu(bus, amdvi_host_dma_iommu, s); 1154 s->devid = object_property_get_int(OBJECT(&s->pci), "addr", err); 1155 msi_init(&s->pci.dev, 0, 1, true, false, err); 1156 amdvi_init(s); 1157 } 1158 1159 static const VMStateDescription vmstate_amdvi = { 1160 .name = "amd-iommu", 1161 .unmigratable = 1 1162 }; 1163 1164 static void amdvi_instance_init(Object *klass) 1165 { 1166 AMDVIState *s = AMD_IOMMU_DEVICE(klass); 1167 1168 object_initialize(&s->pci, sizeof(s->pci), TYPE_AMD_IOMMU_PCI); 1169 } 1170 1171 static void amdvi_class_init(ObjectClass *klass, void* data) 1172 { 1173 DeviceClass *dc = DEVICE_CLASS(klass); 1174 X86IOMMUClass *dc_class = X86_IOMMU_CLASS(klass); 1175 1176 dc->reset = amdvi_reset; 1177 dc->vmsd = &vmstate_amdvi; 1178 dc->hotpluggable = false; 1179 dc_class->realize = amdvi_realize; 1180 } 1181 1182 static const TypeInfo amdvi = { 1183 .name = TYPE_AMD_IOMMU_DEVICE, 1184 .parent = TYPE_X86_IOMMU_DEVICE, 1185 .instance_size = sizeof(AMDVIState), 1186 .instance_init = amdvi_instance_init, 1187 .class_init = amdvi_class_init 1188 }; 1189 1190 static const TypeInfo amdviPCI = { 1191 .name = "AMDVI-PCI", 1192 .parent = TYPE_PCI_DEVICE, 1193 .instance_size = sizeof(AMDVIPCIState), 1194 }; 1195 1196 static void amdviPCI_register_types(void) 1197 { 1198 type_register_static(&amdviPCI); 1199 type_register_static(&amdvi); 1200 } 1201 1202 type_init(amdviPCI_register_types); 1203