| acpi-build.c (0403b0f539f40a21da60409b825b4653b273ab39) | acpi-build.c (ff80dc7fa8045e2b2531888d965424d2b0e1d1b6) |
|---|---|
| 1/* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * --- 606 unchanged lines hidden (view full) --- 615 616 /* Reserve space for header */ 617 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader)); 618 619 scope = aml_scope("\\_SB.PCI0"); 620 /* build PCI0._CRS */ 621 crs = aml_resource_template(); 622 aml_append(crs, | 1/* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * --- 606 unchanged lines hidden (view full) --- 615 616 /* Reserve space for header */ 617 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader)); 618 619 scope = aml_scope("\\_SB.PCI0"); 620 /* build PCI0._CRS */ 621 crs = aml_resource_template(); 622 aml_append(crs, |
| 623 aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode, | 623 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, |
| 624 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100)); | 624 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100)); |
| 625 aml_append(crs, aml_io(aml_decode16, 0x0CF8, 0x0CF8, 0x01, 0x08)); | 625 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); |
| 626 627 aml_append(crs, | 626 627 aml_append(crs, |
| 628 aml_word_io(aml_min_fixed, aml_max_fixed, 629 aml_pos_decode, aml_entire_range, | 628 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 629 AML_POS_DECODE, AML_ENTIRE_RANGE, |
| 630 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 631 aml_append(crs, | 630 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 631 aml_append(crs, |
| 632 aml_word_io(aml_min_fixed, aml_max_fixed, 633 aml_pos_decode, aml_entire_range, | 632 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 633 AML_POS_DECODE, AML_ENTIRE_RANGE, |
| 634 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300)); 635 aml_append(crs, | 634 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300)); 635 aml_append(crs, |
| 636 aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, 637 aml_cacheable, aml_ReadWrite, | 636 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 637 AML_CACHEABLE, AML_READ_WRITE, |
| 638 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 639 aml_append(crs, | 638 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 639 aml_append(crs, |
| 640 aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, 641 aml_non_cacheable, aml_ReadWrite, | 640 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 641 AML_NON_CACHEABLE, AML_READ_WRITE, |
| 642 0, pci->w32.begin, pci->w32.end - 1, 0, 643 pci->w32.end - pci->w32.begin)); 644 if (pci->w64.begin) { 645 aml_append(crs, | 642 0, pci->w32.begin, pci->w32.end - 1, 0, 643 pci->w32.end - pci->w32.begin)); 644 if (pci->w64.begin) { 645 aml_append(crs, |
| 646 aml_qword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, 647 aml_cacheable, aml_ReadWrite, | 646 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 647 AML_CACHEABLE, AML_READ_WRITE, |
| 648 0, pci->w64.begin, pci->w64.end - 1, 0, 649 pci->w64.end - pci->w64.begin)); 650 } 651 aml_append(scope, aml_name_decl("_CRS", crs)); 652 653 /* reserve GPE0 block resources */ 654 dev = aml_device("GPE0"); 655 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 656 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 657 /* device present, functioning, decoding, not shown in UI */ 658 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 659 crs = aml_resource_template(); 660 aml_append(crs, | 648 0, pci->w64.begin, pci->w64.end - 1, 0, 649 pci->w64.end - pci->w64.begin)); 650 } 651 aml_append(scope, aml_name_decl("_CRS", crs)); 652 653 /* reserve GPE0 block resources */ 654 dev = aml_device("GPE0"); 655 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 656 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 657 /* device present, functioning, decoding, not shown in UI */ 658 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 659 crs = aml_resource_template(); 660 aml_append(crs, |
| 661 aml_io(aml_decode16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) | 661 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) |
| 662 ); 663 aml_append(dev, aml_name_decl("_CRS", crs)); 664 aml_append(scope, dev); 665 666 /* reserve PCIHP resources */ 667 if (pm->pcihp_io_len) { 668 dev = aml_device("PHPR"); 669 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 670 aml_append(dev, 671 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 672 /* device present, functioning, decoding, not shown in UI */ 673 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 674 crs = aml_resource_template(); 675 aml_append(crs, | 662 ); 663 aml_append(dev, aml_name_decl("_CRS", crs)); 664 aml_append(scope, dev); 665 666 /* reserve PCIHP resources */ 667 if (pm->pcihp_io_len) { 668 dev = aml_device("PHPR"); 669 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 670 aml_append(dev, 671 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 672 /* device present, functioning, decoding, not shown in UI */ 673 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 674 crs = aml_resource_template(); 675 aml_append(crs, |
| 676 aml_io(aml_decode16, pm->pcihp_io_base, pm->pcihp_io_base, 1, | 676 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, |
| 677 pm->pcihp_io_len) 678 ); 679 aml_append(dev, aml_name_decl("_CRS", crs)); 680 aml_append(scope, dev); 681 } 682 aml_append(ssdt, scope); 683 684 /* create S3_ / S4_ / S5_ packages if necessary */ --- 30 unchanged lines hidden (view full) --- 715 dev = aml_device("SMC"); 716 717 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 718 /* device present, functioning, decoding, not shown in UI */ 719 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 720 721 crs = aml_resource_template(); 722 aml_append(crs, | 677 pm->pcihp_io_len) 678 ); 679 aml_append(dev, aml_name_decl("_CRS", crs)); 680 aml_append(scope, dev); 681 } 682 aml_append(ssdt, scope); 683 684 /* create S3_ / S4_ / S5_ packages if necessary */ --- 30 unchanged lines hidden (view full) --- 715 dev = aml_device("SMC"); 716 717 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 718 /* device present, functioning, decoding, not shown in UI */ 719 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 720 721 crs = aml_resource_template(); 722 aml_append(crs, |
| 723 aml_io(aml_decode16, misc->applesmc_io_base, misc->applesmc_io_base, | 723 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, |
| 724 0x01, APPLESMC_MAX_DATA_LENGTH) 725 ); 726 aml_append(crs, aml_irq_no_flags(6)); 727 aml_append(dev, aml_name_decl("_CRS", crs)); 728 729 aml_append(scope, dev); 730 aml_append(ssdt, scope); 731 } 732 733 if (misc->pvpanic_port) { 734 scope = aml_scope("\\_SB.PCI0.ISA"); 735 736 dev = aml_device("PEVR"); 737 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 738 739 crs = aml_resource_template(); 740 aml_append(crs, | 724 0x01, APPLESMC_MAX_DATA_LENGTH) 725 ); 726 aml_append(crs, aml_irq_no_flags(6)); 727 aml_append(dev, aml_name_decl("_CRS", crs)); 728 729 aml_append(scope, dev); 730 aml_append(ssdt, scope); 731 } 732 733 if (misc->pvpanic_port) { 734 scope = aml_scope("\\_SB.PCI0.ISA"); 735 736 dev = aml_device("PEVR"); 737 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 738 739 crs = aml_resource_template(); 740 aml_append(crs, |
| 741 aml_io(aml_decode16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) | 741 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) |
| 742 ); 743 aml_append(dev, aml_name_decl("_CRS", crs)); 744 | 742 ); 743 aml_append(dev, aml_name_decl("_CRS", crs)); 744 |
| 745 aml_append(dev, aml_operation_region("PEOR", aml_system_io, | 745 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, |
| 746 misc->pvpanic_port, 1)); | 746 misc->pvpanic_port, 1)); |
| 747 field = aml_field("PEOR", aml_byte_acc, aml_preserve); | 747 field = aml_field("PEOR", AML_BYTE_ACC, AML_PRESERVE); |
| 748 aml_append(field, aml_named_field("PEPT", 8)); 749 aml_append(dev, field); 750 751 method = aml_method("RDPT", 0); 752 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 753 aml_append(method, aml_return(aml_local(0))); 754 aml_append(dev, method); 755 --- 12 unchanged lines hidden (view full) --- 768 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 769 aml_append(dev, 770 aml_name_decl("_UID", aml_string("CPU Hotplug resources")) 771 ); 772 /* device present, functioning, decoding, not shown in UI */ 773 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 774 crs = aml_resource_template(); 775 aml_append(crs, | 748 aml_append(field, aml_named_field("PEPT", 8)); 749 aml_append(dev, field); 750 751 method = aml_method("RDPT", 0); 752 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 753 aml_append(method, aml_return(aml_local(0))); 754 aml_append(dev, method); 755 --- 12 unchanged lines hidden (view full) --- 768 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 769 aml_append(dev, 770 aml_name_decl("_UID", aml_string("CPU Hotplug resources")) 771 ); 772 /* device present, functioning, decoding, not shown in UI */ 773 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 774 crs = aml_resource_template(); 775 aml_append(crs, |
| 776 aml_io(aml_decode16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, | 776 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, |
| 777 pm->cpu_hp_io_len) 778 ); 779 aml_append(dev, aml_name_decl("_CRS", crs)); 780 aml_append(sb_scope, dev); 781 /* declare CPU hotplug MMIO region and PRS field to access it */ 782 aml_append(sb_scope, aml_operation_region( | 777 pm->cpu_hp_io_len) 778 ); 779 aml_append(dev, aml_name_decl("_CRS", crs)); 780 aml_append(sb_scope, dev); 781 /* declare CPU hotplug MMIO region and PRS field to access it */ 782 aml_append(sb_scope, aml_operation_region( |
| 783 "PRST", aml_system_io, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); 784 field = aml_field("PRST", aml_byte_acc, aml_preserve); | 783 "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); 784 field = aml_field("PRST", AML_BYTE_ACC, AML_PRESERVE); |
| 785 aml_append(field, aml_named_field("PRS", 256)); 786 aml_append(sb_scope, field); 787 788 /* build Processor object for each processor */ 789 for (i = 0; i < acpi_cpus; i++) { 790 dev = aml_processor(i, 0, 0, "CP%.02X", i); 791 792 method = aml_method("_MAT", 0); --- 47 unchanged lines hidden (view full) --- 840 assert(nr_mem <= ACPI_MAX_RAM_SLOTS); 841 scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE)); 842 aml_append(scope, 843 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem)) 844 ); 845 846 crs = aml_resource_template(); 847 aml_append(crs, | 785 aml_append(field, aml_named_field("PRS", 256)); 786 aml_append(sb_scope, field); 787 788 /* build Processor object for each processor */ 789 for (i = 0; i < acpi_cpus; i++) { 790 dev = aml_processor(i, 0, 0, "CP%.02X", i); 791 792 method = aml_method("_MAT", 0); --- 47 unchanged lines hidden (view full) --- 840 assert(nr_mem <= ACPI_MAX_RAM_SLOTS); 841 scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE)); 842 aml_append(scope, 843 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem)) 844 ); 845 846 crs = aml_resource_template(); 847 aml_append(crs, |
| 848 aml_io(aml_decode16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0, | 848 aml_io(AML_DECODE16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0, |
| 849 pm->mem_hp_io_len) 850 ); 851 aml_append(scope, aml_name_decl("_CRS", crs)); 852 853 aml_append(scope, aml_operation_region( | 849 pm->mem_hp_io_len) 850 ); 851 aml_append(scope, aml_name_decl("_CRS", crs)); 852 853 aml_append(scope, aml_operation_region( |
| 854 stringify(MEMORY_HOTPLUG_IO_REGION), aml_system_io, | 854 stringify(MEMORY_HOTPLUG_IO_REGION), AML_SYSTEM_IO, |
| 855 pm->mem_hp_io_base, pm->mem_hp_io_len) 856 ); 857 | 855 pm->mem_hp_io_base, pm->mem_hp_io_len) 856 ); 857 |
| 858 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc, 859 aml_preserve); | 858 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, 859 AML_PRESERVE); |
| 860 aml_append(field, /* read only */ 861 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32)); 862 aml_append(field, /* read only */ 863 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32)); 864 aml_append(field, /* read only */ 865 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32)); 866 aml_append(field, /* read only */ 867 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32)); 868 aml_append(field, /* read only */ 869 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32)); 870 aml_append(scope, field); 871 | 860 aml_append(field, /* read only */ 861 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32)); 862 aml_append(field, /* read only */ 863 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32)); 864 aml_append(field, /* read only */ 865 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32)); 866 aml_append(field, /* read only */ 867 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32)); 868 aml_append(field, /* read only */ 869 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32)); 870 aml_append(scope, field); 871 |
| 872 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_byte_acc, 873 aml_write_as_zeros); | 872 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_BYTE_ACC, 873 AML_WRITE_AS_ZEROS); |
| 874 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); 875 aml_append(field, /* 1 if enabled, read only */ 876 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1)); 877 aml_append(field, 878 /*(read) 1 if has a insert event. (write) 1 to clear event */ 879 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1)); 880 aml_append(field, 881 /* (read) 1 if has a remove event. (write) 1 to clear event */ 882 aml_named_field(stringify(MEMORY_SLOT_REMOVE_EVENT), 1)); 883 aml_append(field, 884 /* initiates device eject, write only */ 885 aml_named_field(stringify(MEMORY_SLOT_EJECT), 1)); 886 aml_append(scope, field); 887 | 874 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); 875 aml_append(field, /* 1 if enabled, read only */ 876 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1)); 877 aml_append(field, 878 /*(read) 1 if has a insert event. (write) 1 to clear event */ 879 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1)); 880 aml_append(field, 881 /* (read) 1 if has a remove event. (write) 1 to clear event */ 882 aml_named_field(stringify(MEMORY_SLOT_REMOVE_EVENT), 1)); 883 aml_append(field, 884 /* initiates device eject, write only */ 885 aml_named_field(stringify(MEMORY_SLOT_EJECT), 1)); 886 aml_append(scope, field); 887 |
| 888 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc, 889 aml_preserve); | 888 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, 889 AML_PRESERVE); |
| 890 aml_append(field, /* DIMM selector, write only */ 891 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32)); 892 aml_append(field, /* _OST event code, write only */ 893 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32)); 894 aml_append(field, /* _OST status code, write only */ 895 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32)); 896 aml_append(scope, field); 897 --- 685 unchanged lines hidden --- | 890 aml_append(field, /* DIMM selector, write only */ 891 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32)); 892 aml_append(field, /* _OST event code, write only */ 893 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32)); 894 aml_append(field, /* _OST status code, write only */ 895 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32)); 896 aml_append(scope, field); 897 --- 685 unchanged lines hidden --- |