1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "acpi-build.h" 24 #include <stddef.h> 25 #include <glib.h> 26 #include "qemu-common.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/osdep.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "qom/cpu.h" 32 #include "hw/i386/pc.h" 33 #include "target-i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/acpi/memory_hotplug.h" 42 #include "sysemu/tpm.h" 43 #include "hw/acpi/tpm.h" 44 45 /* Supported chipsets: */ 46 #include "hw/acpi/piix4.h" 47 #include "hw/acpi/pcihp.h" 48 #include "hw/i386/ich9.h" 49 #include "hw/pci/pci_bus.h" 50 #include "hw/pci-host/q35.h" 51 #include "hw/i386/intel_iommu.h" 52 53 #include "hw/i386/q35-acpi-dsdt.hex" 54 #include "hw/i386/acpi-dsdt.hex" 55 56 #include "hw/acpi/aml-build.h" 57 58 #include "qapi/qmp/qint.h" 59 #include "qom/qom-qobject.h" 60 61 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 62 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 63 * a little bit, there should be plenty of free space since the DSDT 64 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 65 */ 66 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 67 #define ACPI_BUILD_ALIGN_SIZE 0x1000 68 69 #define ACPI_BUILD_TABLE_SIZE 0x20000 70 71 /* #define DEBUG_ACPI_BUILD */ 72 #ifdef DEBUG_ACPI_BUILD 73 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 74 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 75 #else 76 #define ACPI_BUILD_DPRINTF(fmt, ...) 77 #endif 78 79 typedef struct AcpiCpuInfo { 80 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT); 81 } AcpiCpuInfo; 82 83 typedef struct AcpiMcfgInfo { 84 uint64_t mcfg_base; 85 uint32_t mcfg_size; 86 } AcpiMcfgInfo; 87 88 typedef struct AcpiPmInfo { 89 bool s3_disabled; 90 bool s4_disabled; 91 bool pcihp_bridge_en; 92 uint8_t s4_val; 93 uint16_t sci_int; 94 uint8_t acpi_enable_cmd; 95 uint8_t acpi_disable_cmd; 96 uint32_t gpe0_blk; 97 uint32_t gpe0_blk_len; 98 uint32_t io_base; 99 uint16_t cpu_hp_io_base; 100 uint16_t cpu_hp_io_len; 101 uint16_t mem_hp_io_base; 102 uint16_t mem_hp_io_len; 103 uint16_t pcihp_io_base; 104 uint16_t pcihp_io_len; 105 } AcpiPmInfo; 106 107 typedef struct AcpiMiscInfo { 108 bool has_hpet; 109 bool has_tpm; 110 const unsigned char *dsdt_code; 111 unsigned dsdt_size; 112 uint16_t pvpanic_port; 113 uint16_t applesmc_io_base; 114 } AcpiMiscInfo; 115 116 typedef struct AcpiBuildPciBusHotplugState { 117 GArray *device_table; 118 GArray *notify_table; 119 struct AcpiBuildPciBusHotplugState *parent; 120 bool pcihp_bridge_en; 121 } AcpiBuildPciBusHotplugState; 122 123 static void acpi_get_dsdt(AcpiMiscInfo *info) 124 { 125 Object *piix = piix4_pm_find(); 126 Object *lpc = ich9_lpc_find(); 127 assert(!!piix != !!lpc); 128 129 if (piix) { 130 info->dsdt_code = AcpiDsdtAmlCode; 131 info->dsdt_size = sizeof AcpiDsdtAmlCode; 132 } 133 if (lpc) { 134 info->dsdt_code = Q35AcpiDsdtAmlCode; 135 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode; 136 } 137 } 138 139 static 140 int acpi_add_cpu_info(Object *o, void *opaque) 141 { 142 AcpiCpuInfo *cpu = opaque; 143 uint64_t apic_id; 144 145 if (object_dynamic_cast(o, TYPE_CPU)) { 146 apic_id = object_property_get_int(o, "apic-id", NULL); 147 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); 148 149 set_bit(apic_id, cpu->found_cpus); 150 } 151 152 object_child_foreach(o, acpi_add_cpu_info, opaque); 153 return 0; 154 } 155 156 static void acpi_get_cpu_info(AcpiCpuInfo *cpu) 157 { 158 Object *root = object_get_root(); 159 160 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus); 161 object_child_foreach(root, acpi_add_cpu_info, cpu); 162 } 163 164 static void acpi_get_pm_info(AcpiPmInfo *pm) 165 { 166 Object *piix = piix4_pm_find(); 167 Object *lpc = ich9_lpc_find(); 168 Object *obj = NULL; 169 QObject *o; 170 171 pm->pcihp_io_base = 0; 172 pm->pcihp_io_len = 0; 173 if (piix) { 174 obj = piix; 175 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 176 pm->pcihp_io_base = 177 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 178 pm->pcihp_io_len = 179 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 180 } 181 if (lpc) { 182 obj = lpc; 183 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 184 } 185 assert(obj); 186 187 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN; 188 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 189 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN; 190 191 /* Fill in optional s3/s4 related properties */ 192 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 193 if (o) { 194 pm->s3_disabled = qint_get_int(qobject_to_qint(o)); 195 } else { 196 pm->s3_disabled = false; 197 } 198 qobject_decref(o); 199 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 200 if (o) { 201 pm->s4_disabled = qint_get_int(qobject_to_qint(o)); 202 } else { 203 pm->s4_disabled = false; 204 } 205 qobject_decref(o); 206 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 207 if (o) { 208 pm->s4_val = qint_get_int(qobject_to_qint(o)); 209 } else { 210 pm->s4_val = false; 211 } 212 qobject_decref(o); 213 214 /* Fill in mandatory properties */ 215 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL); 216 217 pm->acpi_enable_cmd = object_property_get_int(obj, 218 ACPI_PM_PROP_ACPI_ENABLE_CMD, 219 NULL); 220 pm->acpi_disable_cmd = object_property_get_int(obj, 221 ACPI_PM_PROP_ACPI_DISABLE_CMD, 222 NULL); 223 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE, 224 NULL); 225 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK, 226 NULL); 227 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN, 228 NULL); 229 pm->pcihp_bridge_en = 230 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 231 NULL); 232 } 233 234 static void acpi_get_misc_info(AcpiMiscInfo *info) 235 { 236 info->has_hpet = hpet_find(); 237 info->has_tpm = tpm_find(); 238 info->pvpanic_port = pvpanic_port(); 239 info->applesmc_io_base = applesmc_port(); 240 } 241 242 static void acpi_get_pci_info(PcPciInfo *info) 243 { 244 Object *pci_host; 245 bool ambiguous; 246 247 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 248 g_assert(!ambiguous); 249 g_assert(pci_host); 250 251 info->w32.begin = object_property_get_int(pci_host, 252 PCI_HOST_PROP_PCI_HOLE_START, 253 NULL); 254 info->w32.end = object_property_get_int(pci_host, 255 PCI_HOST_PROP_PCI_HOLE_END, 256 NULL); 257 info->w64.begin = object_property_get_int(pci_host, 258 PCI_HOST_PROP_PCI_HOLE64_START, 259 NULL); 260 info->w64.end = object_property_get_int(pci_host, 261 PCI_HOST_PROP_PCI_HOLE64_END, 262 NULL); 263 } 264 265 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */ 266 267 static void acpi_align_size(GArray *blob, unsigned align) 268 { 269 /* Align size to multiple of given size. This reduces the chance 270 * we need to change size in the future (breaking cross version migration). 271 */ 272 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 273 } 274 275 /* FACS */ 276 static void 277 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) 278 { 279 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 280 memcpy(&facs->signature, "FACS", 4); 281 facs->length = cpu_to_le32(sizeof(*facs)); 282 } 283 284 /* Load chipset information in FADT */ 285 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm) 286 { 287 fadt->model = 1; 288 fadt->reserved1 = 0; 289 fadt->sci_int = cpu_to_le16(pm->sci_int); 290 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD); 291 fadt->acpi_enable = pm->acpi_enable_cmd; 292 fadt->acpi_disable = pm->acpi_disable_cmd; 293 /* EVT, CNT, TMR offset matches hw/acpi/core.c */ 294 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base); 295 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04); 296 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08); 297 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk); 298 /* EVT, CNT, TMR length matches hw/acpi/core.c */ 299 fadt->pm1_evt_len = 4; 300 fadt->pm1_cnt_len = 2; 301 fadt->pm_tmr_len = 4; 302 fadt->gpe0_blk_len = pm->gpe0_blk_len; 303 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */ 304 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */ 305 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) | 306 (1 << ACPI_FADT_F_PROC_C1) | 307 (1 << ACPI_FADT_F_SLP_BUTTON) | 308 (1 << ACPI_FADT_F_RTC_S4)); 309 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK); 310 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs 311 * For more than 8 CPUs, "Clustered Logical" mode has to be used 312 */ 313 if (max_cpus > 8) { 314 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); 315 } 316 } 317 318 319 /* FADT */ 320 static void 321 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm, 322 unsigned facs, unsigned dsdt) 323 { 324 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 325 326 fadt->firmware_ctrl = cpu_to_le32(facs); 327 /* FACS address to be filled by Guest linker */ 328 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 329 ACPI_BUILD_TABLE_FILE, 330 table_data, &fadt->firmware_ctrl, 331 sizeof fadt->firmware_ctrl); 332 333 fadt->dsdt = cpu_to_le32(dsdt); 334 /* DSDT address to be filled by Guest linker */ 335 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 336 ACPI_BUILD_TABLE_FILE, 337 table_data, &fadt->dsdt, 338 sizeof fadt->dsdt); 339 340 fadt_setup(fadt, pm); 341 342 build_header(linker, table_data, 343 (void *)fadt, "FACP", sizeof(*fadt), 1); 344 } 345 346 static void 347 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu, 348 PcGuestInfo *guest_info) 349 { 350 int madt_start = table_data->len; 351 352 AcpiMultipleApicTable *madt; 353 AcpiMadtIoApic *io_apic; 354 AcpiMadtIntsrcovr *intsrcovr; 355 AcpiMadtLocalNmi *local_nmi; 356 int i; 357 358 madt = acpi_data_push(table_data, sizeof *madt); 359 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 360 madt->flags = cpu_to_le32(1); 361 362 for (i = 0; i < guest_info->apic_id_limit; i++) { 363 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic); 364 apic->type = ACPI_APIC_PROCESSOR; 365 apic->length = sizeof(*apic); 366 apic->processor_id = i; 367 apic->local_apic_id = i; 368 if (test_bit(i, cpu->found_cpus)) { 369 apic->flags = cpu_to_le32(1); 370 } else { 371 apic->flags = cpu_to_le32(0); 372 } 373 } 374 io_apic = acpi_data_push(table_data, sizeof *io_apic); 375 io_apic->type = ACPI_APIC_IO; 376 io_apic->length = sizeof(*io_apic); 377 #define ACPI_BUILD_IOAPIC_ID 0x0 378 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 379 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 380 io_apic->interrupt = cpu_to_le32(0); 381 382 if (guest_info->apic_xrupt_override) { 383 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 384 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 385 intsrcovr->length = sizeof(*intsrcovr); 386 intsrcovr->source = 0; 387 intsrcovr->gsi = cpu_to_le32(2); 388 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 389 } 390 for (i = 1; i < 16; i++) { 391 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 392 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 393 /* No need for a INT source override structure. */ 394 continue; 395 } 396 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 397 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 398 intsrcovr->length = sizeof(*intsrcovr); 399 intsrcovr->source = i; 400 intsrcovr->gsi = cpu_to_le32(i); 401 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 402 } 403 404 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 405 local_nmi->type = ACPI_APIC_LOCAL_NMI; 406 local_nmi->length = sizeof(*local_nmi); 407 local_nmi->processor_id = 0xff; /* all processors */ 408 local_nmi->flags = cpu_to_le16(0); 409 local_nmi->lint = 1; /* ACPI_LINT1 */ 410 411 build_header(linker, table_data, 412 (void *)(table_data->data + madt_start), "APIC", 413 table_data->len - madt_start, 1); 414 } 415 416 #include "hw/i386/ssdt-tpm.hex" 417 418 /* Assign BSEL property to all buses. In the future, this can be changed 419 * to only assign to buses that support hotplug. 420 */ 421 static void *acpi_set_bsel(PCIBus *bus, void *opaque) 422 { 423 unsigned *bsel_alloc = opaque; 424 unsigned *bus_bsel; 425 426 if (qbus_is_hotpluggable(BUS(bus))) { 427 bus_bsel = g_malloc(sizeof *bus_bsel); 428 429 *bus_bsel = (*bsel_alloc)++; 430 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, 431 bus_bsel, NULL); 432 } 433 434 return bsel_alloc; 435 } 436 437 static void acpi_set_pci_info(void) 438 { 439 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ 440 unsigned bsel_alloc = 0; 441 442 if (bus) { 443 /* Scan all PCI buses. Set property to enable acpi based hotplug. */ 444 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); 445 } 446 } 447 448 static void build_append_pcihp_notify_entry(Aml *method, int slot) 449 { 450 Aml *if_ctx; 451 int32_t devfn = PCI_DEVFN(slot, 0); 452 453 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot))); 454 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 455 aml_append(method, if_ctx); 456 } 457 458 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 459 bool pcihp_bridge_en) 460 { 461 Aml *dev, *notify_method, *method; 462 QObject *bsel; 463 PCIBus *sec; 464 int i; 465 466 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 467 if (bsel) { 468 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 469 470 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 471 notify_method = aml_method("DVNT", 2); 472 } 473 474 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 475 DeviceClass *dc; 476 PCIDeviceClass *pc; 477 PCIDevice *pdev = bus->devices[i]; 478 int slot = PCI_SLOT(i); 479 bool hotplug_enabled_dev; 480 bool bridge_in_acpi; 481 482 if (!pdev) { 483 if (bsel) { /* add hotplug slots for non present devices */ 484 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 485 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 486 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 487 method = aml_method("_EJ0", 1); 488 aml_append(method, 489 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 490 ); 491 aml_append(dev, method); 492 aml_append(parent_scope, dev); 493 494 build_append_pcihp_notify_entry(notify_method, slot); 495 } 496 continue; 497 } 498 499 pc = PCI_DEVICE_GET_CLASS(pdev); 500 dc = DEVICE_GET_CLASS(pdev); 501 502 /* When hotplug for bridges is enabled, bridges are 503 * described in ACPI separately (see build_pci_bus_end). 504 * In this case they aren't themselves hot-pluggable. 505 * Hotplugged bridges *are* hot-pluggable. 506 */ 507 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 508 !DEVICE(pdev)->hotplugged; 509 510 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 511 512 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 513 continue; 514 } 515 516 /* start to compose PCI slot descriptor */ 517 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 518 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 519 520 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 521 /* add VGA specific AML methods */ 522 int s3d; 523 524 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 525 s3d = 3; 526 } else { 527 s3d = 0; 528 } 529 530 method = aml_method("_S1D", 0); 531 aml_append(method, aml_return(aml_int(0))); 532 aml_append(dev, method); 533 534 method = aml_method("_S2D", 0); 535 aml_append(method, aml_return(aml_int(0))); 536 aml_append(dev, method); 537 538 method = aml_method("_S3D", 0); 539 aml_append(method, aml_return(aml_int(s3d))); 540 aml_append(dev, method); 541 } else if (hotplug_enabled_dev) { 542 /* add _SUN/_EJ0 to make slot hotpluggable */ 543 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 544 545 method = aml_method("_EJ0", 1); 546 aml_append(method, 547 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 548 ); 549 aml_append(dev, method); 550 551 if (bsel) { 552 build_append_pcihp_notify_entry(notify_method, slot); 553 } 554 } else if (bridge_in_acpi) { 555 /* 556 * device is coldplugged bridge, 557 * add child device descriptions into its scope 558 */ 559 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 560 561 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 562 } 563 /* slot descriptor has been composed, add it into parent context */ 564 aml_append(parent_scope, dev); 565 } 566 567 if (bsel) { 568 aml_append(parent_scope, notify_method); 569 } 570 571 /* Append PCNT method to notify about events on local and child buses. 572 * Add unconditionally for root since DSDT expects it. 573 */ 574 method = aml_method("PCNT", 0); 575 576 /* If bus supports hotplug select it and notify about local events */ 577 if (bsel) { 578 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 579 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 580 aml_append(method, 581 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 582 ); 583 aml_append(method, 584 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 585 ); 586 } 587 588 /* Notify about child bus events in any case */ 589 if (pcihp_bridge_en) { 590 QLIST_FOREACH(sec, &bus->child, sibling) { 591 int32_t devfn = sec->parent_dev->devfn; 592 593 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 594 } 595 } 596 aml_append(parent_scope, method); 597 } 598 599 static void 600 build_ssdt(GArray *table_data, GArray *linker, 601 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, 602 PcPciInfo *pci, PcGuestInfo *guest_info) 603 { 604 MachineState *machine = MACHINE(qdev_get_machine()); 605 uint32_t nr_mem = machine->ram_slots; 606 unsigned acpi_cpus = guest_info->apic_id_limit; 607 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx; 608 int i; 609 610 ssdt = init_aml_allocator(); 611 /* The current AML generator can cover the APIC ID range [0..255], 612 * inclusive, for VCPU hotplug. */ 613 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); 614 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT); 615 616 /* Reserve space for header */ 617 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader)); 618 619 scope = aml_scope("\\_SB.PCI0"); 620 /* build PCI0._CRS */ 621 crs = aml_resource_template(); 622 aml_append(crs, 623 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 624 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100)); 625 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 626 627 aml_append(crs, 628 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 629 AML_POS_DECODE, AML_ENTIRE_RANGE, 630 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 631 aml_append(crs, 632 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 633 AML_POS_DECODE, AML_ENTIRE_RANGE, 634 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300)); 635 aml_append(crs, 636 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 637 AML_CACHEABLE, AML_READ_WRITE, 638 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 639 aml_append(crs, 640 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 641 AML_NON_CACHEABLE, AML_READ_WRITE, 642 0, pci->w32.begin, pci->w32.end - 1, 0, 643 pci->w32.end - pci->w32.begin)); 644 if (pci->w64.begin) { 645 aml_append(crs, 646 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 647 AML_CACHEABLE, AML_READ_WRITE, 648 0, pci->w64.begin, pci->w64.end - 1, 0, 649 pci->w64.end - pci->w64.begin)); 650 } 651 aml_append(scope, aml_name_decl("_CRS", crs)); 652 653 /* reserve GPE0 block resources */ 654 dev = aml_device("GPE0"); 655 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 656 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 657 /* device present, functioning, decoding, not shown in UI */ 658 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 659 crs = aml_resource_template(); 660 aml_append(crs, 661 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) 662 ); 663 aml_append(dev, aml_name_decl("_CRS", crs)); 664 aml_append(scope, dev); 665 666 /* reserve PCIHP resources */ 667 if (pm->pcihp_io_len) { 668 dev = aml_device("PHPR"); 669 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 670 aml_append(dev, 671 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 672 /* device present, functioning, decoding, not shown in UI */ 673 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 674 crs = aml_resource_template(); 675 aml_append(crs, 676 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 677 pm->pcihp_io_len) 678 ); 679 aml_append(dev, aml_name_decl("_CRS", crs)); 680 aml_append(scope, dev); 681 } 682 aml_append(ssdt, scope); 683 684 /* create S3_ / S4_ / S5_ packages if necessary */ 685 scope = aml_scope("\\"); 686 if (!pm->s3_disabled) { 687 pkg = aml_package(4); 688 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 689 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 690 aml_append(pkg, aml_int(0)); /* reserved */ 691 aml_append(pkg, aml_int(0)); /* reserved */ 692 aml_append(scope, aml_name_decl("_S3", pkg)); 693 } 694 695 if (!pm->s4_disabled) { 696 pkg = aml_package(4); 697 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 698 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 699 aml_append(pkg, aml_int(pm->s4_val)); 700 aml_append(pkg, aml_int(0)); /* reserved */ 701 aml_append(pkg, aml_int(0)); /* reserved */ 702 aml_append(scope, aml_name_decl("_S4", pkg)); 703 } 704 705 pkg = aml_package(4); 706 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 707 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 708 aml_append(pkg, aml_int(0)); /* reserved */ 709 aml_append(pkg, aml_int(0)); /* reserved */ 710 aml_append(scope, aml_name_decl("_S5", pkg)); 711 aml_append(ssdt, scope); 712 713 if (misc->applesmc_io_base) { 714 scope = aml_scope("\\_SB.PCI0.ISA"); 715 dev = aml_device("SMC"); 716 717 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 718 /* device present, functioning, decoding, not shown in UI */ 719 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 720 721 crs = aml_resource_template(); 722 aml_append(crs, 723 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 724 0x01, APPLESMC_MAX_DATA_LENGTH) 725 ); 726 aml_append(crs, aml_irq_no_flags(6)); 727 aml_append(dev, aml_name_decl("_CRS", crs)); 728 729 aml_append(scope, dev); 730 aml_append(ssdt, scope); 731 } 732 733 if (misc->pvpanic_port) { 734 scope = aml_scope("\\_SB.PCI0.ISA"); 735 736 dev = aml_device("PEVR"); 737 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 738 739 crs = aml_resource_template(); 740 aml_append(crs, 741 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 742 ); 743 aml_append(dev, aml_name_decl("_CRS", crs)); 744 745 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 746 misc->pvpanic_port, 1)); 747 field = aml_field("PEOR", AML_BYTE_ACC, AML_PRESERVE); 748 aml_append(field, aml_named_field("PEPT", 8)); 749 aml_append(dev, field); 750 751 method = aml_method("RDPT", 0); 752 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 753 aml_append(method, aml_return(aml_local(0))); 754 aml_append(dev, method); 755 756 method = aml_method("WRPT", 1); 757 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 758 aml_append(dev, method); 759 760 aml_append(scope, dev); 761 aml_append(ssdt, scope); 762 } 763 764 sb_scope = aml_scope("\\_SB"); 765 { 766 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ 767 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); 768 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 769 aml_append(dev, 770 aml_name_decl("_UID", aml_string("CPU Hotplug resources")) 771 ); 772 /* device present, functioning, decoding, not shown in UI */ 773 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 774 crs = aml_resource_template(); 775 aml_append(crs, 776 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, 777 pm->cpu_hp_io_len) 778 ); 779 aml_append(dev, aml_name_decl("_CRS", crs)); 780 aml_append(sb_scope, dev); 781 /* declare CPU hotplug MMIO region and PRS field to access it */ 782 aml_append(sb_scope, aml_operation_region( 783 "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); 784 field = aml_field("PRST", AML_BYTE_ACC, AML_PRESERVE); 785 aml_append(field, aml_named_field("PRS", 256)); 786 aml_append(sb_scope, field); 787 788 /* build Processor object for each processor */ 789 for (i = 0; i < acpi_cpus; i++) { 790 dev = aml_processor(i, 0, 0, "CP%.02X", i); 791 792 method = aml_method("_MAT", 0); 793 aml_append(method, aml_return(aml_call1("CPMA", aml_int(i)))); 794 aml_append(dev, method); 795 796 method = aml_method("_STA", 0); 797 aml_append(method, aml_return(aml_call1("CPST", aml_int(i)))); 798 aml_append(dev, method); 799 800 method = aml_method("_EJ0", 1); 801 aml_append(method, 802 aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0))) 803 ); 804 aml_append(dev, method); 805 806 aml_append(sb_scope, dev); 807 } 808 809 /* build this code: 810 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} 811 */ 812 /* Arg0 = Processor ID = APIC ID */ 813 method = aml_method("NTFY", 2); 814 for (i = 0; i < acpi_cpus; i++) { 815 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 816 aml_append(ifctx, 817 aml_notify(aml_name("CP%.02X", i), aml_arg(1)) 818 ); 819 aml_append(method, ifctx); 820 } 821 aml_append(sb_scope, method); 822 823 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" 824 * 825 * Note: The ability to create variable-sized packages was first 826 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages 827 * ith up to 255 elements. Windows guests up to win2k8 fail when 828 * VarPackageOp is used. 829 */ 830 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) : 831 aml_varpackage(acpi_cpus); 832 833 for (i = 0; i < acpi_cpus; i++) { 834 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00; 835 aml_append(pkg, aml_int(b)); 836 } 837 aml_append(sb_scope, aml_name_decl("CPON", pkg)); 838 839 /* build memory devices */ 840 assert(nr_mem <= ACPI_MAX_RAM_SLOTS); 841 scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE)); 842 aml_append(scope, 843 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem)) 844 ); 845 846 crs = aml_resource_template(); 847 aml_append(crs, 848 aml_io(AML_DECODE16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0, 849 pm->mem_hp_io_len) 850 ); 851 aml_append(scope, aml_name_decl("_CRS", crs)); 852 853 aml_append(scope, aml_operation_region( 854 stringify(MEMORY_HOTPLUG_IO_REGION), AML_SYSTEM_IO, 855 pm->mem_hp_io_base, pm->mem_hp_io_len) 856 ); 857 858 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, 859 AML_PRESERVE); 860 aml_append(field, /* read only */ 861 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32)); 862 aml_append(field, /* read only */ 863 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32)); 864 aml_append(field, /* read only */ 865 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32)); 866 aml_append(field, /* read only */ 867 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32)); 868 aml_append(field, /* read only */ 869 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32)); 870 aml_append(scope, field); 871 872 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_BYTE_ACC, 873 AML_WRITE_AS_ZEROS); 874 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); 875 aml_append(field, /* 1 if enabled, read only */ 876 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1)); 877 aml_append(field, 878 /*(read) 1 if has a insert event. (write) 1 to clear event */ 879 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1)); 880 aml_append(field, 881 /* (read) 1 if has a remove event. (write) 1 to clear event */ 882 aml_named_field(stringify(MEMORY_SLOT_REMOVE_EVENT), 1)); 883 aml_append(field, 884 /* initiates device eject, write only */ 885 aml_named_field(stringify(MEMORY_SLOT_EJECT), 1)); 886 aml_append(scope, field); 887 888 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, 889 AML_PRESERVE); 890 aml_append(field, /* DIMM selector, write only */ 891 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32)); 892 aml_append(field, /* _OST event code, write only */ 893 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32)); 894 aml_append(field, /* _OST status code, write only */ 895 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32)); 896 aml_append(scope, field); 897 898 aml_append(sb_scope, scope); 899 900 for (i = 0; i < nr_mem; i++) { 901 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "." 902 const char *s; 903 904 dev = aml_device("MP%02X", i); 905 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i))); 906 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80"))); 907 908 method = aml_method("_CRS", 0); 909 s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD); 910 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 911 aml_append(dev, method); 912 913 method = aml_method("_STA", 0); 914 s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD); 915 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 916 aml_append(dev, method); 917 918 method = aml_method("_PXM", 0); 919 s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD); 920 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 921 aml_append(dev, method); 922 923 method = aml_method("_OST", 3); 924 s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD); 925 aml_append(method, aml_return(aml_call4( 926 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2) 927 ))); 928 aml_append(dev, method); 929 930 method = aml_method("_EJ0", 1); 931 s = BASEPATH stringify(MEMORY_SLOT_EJECT_METHOD); 932 aml_append(method, aml_return(aml_call2( 933 s, aml_name("_UID"), aml_arg(0)))); 934 aml_append(dev, method); 935 936 aml_append(sb_scope, dev); 937 } 938 939 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) { 940 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... } 941 */ 942 method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2); 943 for (i = 0; i < nr_mem; i++) { 944 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 945 aml_append(ifctx, 946 aml_notify(aml_name("MP%.02X", i), aml_arg(1)) 947 ); 948 aml_append(method, ifctx); 949 } 950 aml_append(sb_scope, method); 951 952 { 953 Object *pci_host; 954 PCIBus *bus = NULL; 955 bool ambiguous; 956 957 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 958 if (!ambiguous && pci_host) { 959 bus = PCI_HOST_BRIDGE(pci_host)->bus; 960 } 961 962 if (bus) { 963 Aml *scope = aml_scope("PCI0"); 964 /* Scan all PCI buses. Generate tables to support hotplug. */ 965 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 966 aml_append(sb_scope, scope); 967 } 968 } 969 aml_append(ssdt, sb_scope); 970 } 971 972 /* copy AML table into ACPI tables blob and patch header there */ 973 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len); 974 build_header(linker, table_data, 975 (void *)(table_data->data + table_data->len - ssdt->buf->len), 976 "SSDT", ssdt->buf->len, 1); 977 free_aml_allocator(); 978 } 979 980 static void 981 build_hpet(GArray *table_data, GArray *linker) 982 { 983 Acpi20Hpet *hpet; 984 985 hpet = acpi_data_push(table_data, sizeof(*hpet)); 986 /* Note timer_block_id value must be kept in sync with value advertised by 987 * emulated hpet 988 */ 989 hpet->timer_block_id = cpu_to_le32(0x8086a201); 990 hpet->addr.address = cpu_to_le64(HPET_BASE); 991 build_header(linker, table_data, 992 (void *)hpet, "HPET", sizeof(*hpet), 1); 993 } 994 995 static void 996 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog) 997 { 998 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 999 uint64_t log_area_start_address = acpi_data_len(tcpalog); 1000 1001 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 1002 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 1003 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address); 1004 1005 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1, 1006 false /* high memory */); 1007 1008 /* log area start address to be filled by Guest linker */ 1009 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1010 ACPI_BUILD_TPMLOG_FILE, 1011 table_data, &tcpa->log_area_start_address, 1012 sizeof(tcpa->log_area_start_address)); 1013 1014 build_header(linker, table_data, 1015 (void *)tcpa, "TCPA", sizeof(*tcpa), 2); 1016 1017 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1018 } 1019 1020 static void 1021 build_tpm_ssdt(GArray *table_data, GArray *linker) 1022 { 1023 void *tpm_ptr; 1024 1025 tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm_aml)); 1026 memcpy(tpm_ptr, ssdt_tpm_aml, sizeof(ssdt_tpm_aml)); 1027 } 1028 1029 typedef enum { 1030 MEM_AFFINITY_NOFLAGS = 0, 1031 MEM_AFFINITY_ENABLED = (1 << 0), 1032 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1), 1033 MEM_AFFINITY_NON_VOLATILE = (1 << 2), 1034 } MemoryAffinityFlags; 1035 1036 static void 1037 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, 1038 uint64_t len, int node, MemoryAffinityFlags flags) 1039 { 1040 numamem->type = ACPI_SRAT_MEMORY; 1041 numamem->length = sizeof(*numamem); 1042 memset(numamem->proximity, 0, 4); 1043 numamem->proximity[0] = node; 1044 numamem->flags = cpu_to_le32(flags); 1045 numamem->base_addr = cpu_to_le64(base); 1046 numamem->range_length = cpu_to_le64(len); 1047 } 1048 1049 static void 1050 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) 1051 { 1052 AcpiSystemResourceAffinityTable *srat; 1053 AcpiSratProcessorAffinity *core; 1054 AcpiSratMemoryAffinity *numamem; 1055 1056 int i; 1057 uint64_t curnode; 1058 int srat_start, numa_start, slots; 1059 uint64_t mem_len, mem_base, next_base; 1060 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1061 ram_addr_t hotplugabble_address_space_size = 1062 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, 1063 NULL); 1064 1065 srat_start = table_data->len; 1066 1067 srat = acpi_data_push(table_data, sizeof *srat); 1068 srat->reserved1 = cpu_to_le32(1); 1069 core = (void *)(srat + 1); 1070 1071 for (i = 0; i < guest_info->apic_id_limit; ++i) { 1072 core = acpi_data_push(table_data, sizeof *core); 1073 core->type = ACPI_SRAT_PROCESSOR; 1074 core->length = sizeof(*core); 1075 core->local_apic_id = i; 1076 curnode = guest_info->node_cpu[i]; 1077 core->proximity_lo = curnode; 1078 memset(core->proximity_hi, 0, 3); 1079 core->local_sapic_eid = 0; 1080 core->flags = cpu_to_le32(1); 1081 } 1082 1083 1084 /* the memory map is a bit tricky, it contains at least one hole 1085 * from 640k-1M and possibly another one from 3.5G-4G. 1086 */ 1087 next_base = 0; 1088 numa_start = table_data->len; 1089 1090 numamem = acpi_data_push(table_data, sizeof *numamem); 1091 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED); 1092 next_base = 1024 * 1024; 1093 for (i = 1; i < guest_info->numa_nodes + 1; ++i) { 1094 mem_base = next_base; 1095 mem_len = guest_info->node_mem[i - 1]; 1096 if (i == 1) { 1097 mem_len -= 1024 * 1024; 1098 } 1099 next_base = mem_base + mem_len; 1100 1101 /* Cut out the ACPI_PCI hole */ 1102 if (mem_base <= guest_info->ram_size_below_4g && 1103 next_base > guest_info->ram_size_below_4g) { 1104 mem_len -= next_base - guest_info->ram_size_below_4g; 1105 if (mem_len > 0) { 1106 numamem = acpi_data_push(table_data, sizeof *numamem); 1107 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1108 MEM_AFFINITY_ENABLED); 1109 } 1110 mem_base = 1ULL << 32; 1111 mem_len = next_base - guest_info->ram_size_below_4g; 1112 next_base += (1ULL << 32) - guest_info->ram_size_below_4g; 1113 } 1114 numamem = acpi_data_push(table_data, sizeof *numamem); 1115 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1116 MEM_AFFINITY_ENABLED); 1117 } 1118 slots = (table_data->len - numa_start) / sizeof *numamem; 1119 for (; slots < guest_info->numa_nodes + 2; slots++) { 1120 numamem = acpi_data_push(table_data, sizeof *numamem); 1121 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1122 } 1123 1124 /* 1125 * Entry is required for Windows to enable memory hotplug in OS. 1126 * Memory devices may override proximity set by this entry, 1127 * providing _PXM method if necessary. 1128 */ 1129 if (hotplugabble_address_space_size) { 1130 numamem = acpi_data_push(table_data, sizeof *numamem); 1131 acpi_build_srat_memory(numamem, pcms->hotplug_memory_base, 1132 hotplugabble_address_space_size, 0, 1133 MEM_AFFINITY_HOTPLUGGABLE | 1134 MEM_AFFINITY_ENABLED); 1135 } 1136 1137 build_header(linker, table_data, 1138 (void *)(table_data->data + srat_start), 1139 "SRAT", 1140 table_data->len - srat_start, 1); 1141 } 1142 1143 static void 1144 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info) 1145 { 1146 AcpiTableMcfg *mcfg; 1147 const char *sig; 1148 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); 1149 1150 mcfg = acpi_data_push(table_data, len); 1151 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); 1152 /* Only a single allocation so no need to play with segments */ 1153 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 1154 mcfg->allocation[0].start_bus_number = 0; 1155 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); 1156 1157 /* MCFG is used for ECAM which can be enabled or disabled by guest. 1158 * To avoid table size changes (which create migration issues), 1159 * always create the table even if there are no allocations, 1160 * but set the signature to a reserved value in this case. 1161 * ACPI spec requires OSPMs to ignore such tables. 1162 */ 1163 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { 1164 /* Reserved signature: ignored by OSPM */ 1165 sig = "QEMU"; 1166 } else { 1167 sig = "MCFG"; 1168 } 1169 build_header(linker, table_data, (void *)mcfg, sig, len, 1); 1170 } 1171 1172 static void 1173 build_dmar_q35(GArray *table_data, GArray *linker) 1174 { 1175 int dmar_start = table_data->len; 1176 1177 AcpiTableDmar *dmar; 1178 AcpiDmarHardwareUnit *drhd; 1179 1180 dmar = acpi_data_push(table_data, sizeof(*dmar)); 1181 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1; 1182 dmar->flags = 0; /* No intr_remap for now */ 1183 1184 /* DMAR Remapping Hardware Unit Definition structure */ 1185 drhd = acpi_data_push(table_data, sizeof(*drhd)); 1186 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 1187 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */ 1188 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 1189 drhd->pci_segment = cpu_to_le16(0); 1190 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 1191 1192 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 1193 "DMAR", table_data->len - dmar_start, 1); 1194 } 1195 1196 static void 1197 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc) 1198 { 1199 AcpiTableHeader *dsdt; 1200 1201 assert(misc->dsdt_code && misc->dsdt_size); 1202 1203 dsdt = acpi_data_push(table_data, misc->dsdt_size); 1204 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size); 1205 1206 memset(dsdt, 0, sizeof *dsdt); 1207 build_header(linker, table_data, dsdt, "DSDT", 1208 misc->dsdt_size, 1); 1209 } 1210 1211 /* Build final rsdt table */ 1212 static void 1213 build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets) 1214 { 1215 AcpiRsdtDescriptorRev1 *rsdt; 1216 size_t rsdt_len; 1217 int i; 1218 1219 rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len; 1220 rsdt = acpi_data_push(table_data, rsdt_len); 1221 memcpy(rsdt->table_offset_entry, table_offsets->data, 1222 sizeof(uint32_t) * table_offsets->len); 1223 for (i = 0; i < table_offsets->len; ++i) { 1224 /* rsdt->table_offset_entry to be filled by Guest linker */ 1225 bios_linker_loader_add_pointer(linker, 1226 ACPI_BUILD_TABLE_FILE, 1227 ACPI_BUILD_TABLE_FILE, 1228 table_data, &rsdt->table_offset_entry[i], 1229 sizeof(uint32_t)); 1230 } 1231 build_header(linker, table_data, 1232 (void *)rsdt, "RSDT", rsdt_len, 1); 1233 } 1234 1235 static GArray * 1236 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 1237 { 1238 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 1239 1240 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 1241 true /* fseg memory */); 1242 1243 memcpy(&rsdp->signature, "RSD PTR ", 8); 1244 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); 1245 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 1246 /* Address to be filled by Guest linker */ 1247 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 1248 ACPI_BUILD_TABLE_FILE, 1249 rsdp_table, &rsdp->rsdt_physical_address, 1250 sizeof rsdp->rsdt_physical_address); 1251 rsdp->checksum = 0; 1252 /* Checksum to be filled by Guest linker */ 1253 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 1254 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum); 1255 1256 return rsdp_table; 1257 } 1258 1259 typedef 1260 struct AcpiBuildState { 1261 /* Copy of table in RAM (for patching). */ 1262 MemoryRegion *table_mr; 1263 /* Is table patched? */ 1264 uint8_t patched; 1265 PcGuestInfo *guest_info; 1266 void *rsdp; 1267 MemoryRegion *rsdp_mr; 1268 MemoryRegion *linker_mr; 1269 } AcpiBuildState; 1270 1271 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 1272 { 1273 Object *pci_host; 1274 QObject *o; 1275 bool ambiguous; 1276 1277 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 1278 g_assert(!ambiguous); 1279 g_assert(pci_host); 1280 1281 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 1282 if (!o) { 1283 return false; 1284 } 1285 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o)); 1286 qobject_decref(o); 1287 1288 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 1289 assert(o); 1290 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o)); 1291 qobject_decref(o); 1292 return true; 1293 } 1294 1295 static bool acpi_has_iommu(void) 1296 { 1297 bool ambiguous; 1298 Object *intel_iommu; 1299 1300 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, 1301 &ambiguous); 1302 return intel_iommu && !ambiguous; 1303 } 1304 1305 static 1306 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) 1307 { 1308 GArray *table_offsets; 1309 unsigned facs, ssdt, dsdt, rsdt; 1310 AcpiCpuInfo cpu; 1311 AcpiPmInfo pm; 1312 AcpiMiscInfo misc; 1313 AcpiMcfgInfo mcfg; 1314 PcPciInfo pci; 1315 uint8_t *u; 1316 size_t aml_len = 0; 1317 GArray *tables_blob = tables->table_data; 1318 1319 acpi_get_cpu_info(&cpu); 1320 acpi_get_pm_info(&pm); 1321 acpi_get_dsdt(&misc); 1322 acpi_get_misc_info(&misc); 1323 acpi_get_pci_info(&pci); 1324 1325 table_offsets = g_array_new(false, true /* clear */, 1326 sizeof(uint32_t)); 1327 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 1328 1329 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 1330 64 /* Ensure FACS is aligned */, 1331 false /* high memory */); 1332 1333 /* 1334 * FACS is pointed to by FADT. 1335 * We place it first since it's the only table that has alignment 1336 * requirements. 1337 */ 1338 facs = tables_blob->len; 1339 build_facs(tables_blob, tables->linker, guest_info); 1340 1341 /* DSDT is pointed to by FADT */ 1342 dsdt = tables_blob->len; 1343 build_dsdt(tables_blob, tables->linker, &misc); 1344 1345 /* Count the size of the DSDT and SSDT, we will need it for legacy 1346 * sizing of ACPI tables. 1347 */ 1348 aml_len += tables_blob->len - dsdt; 1349 1350 /* ACPI tables pointed to by RSDT */ 1351 acpi_add_table(table_offsets, tables_blob); 1352 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt); 1353 1354 ssdt = tables_blob->len; 1355 acpi_add_table(table_offsets, tables_blob); 1356 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci, 1357 guest_info); 1358 aml_len += tables_blob->len - ssdt; 1359 1360 acpi_add_table(table_offsets, tables_blob); 1361 build_madt(tables_blob, tables->linker, &cpu, guest_info); 1362 1363 if (misc.has_hpet) { 1364 acpi_add_table(table_offsets, tables_blob); 1365 build_hpet(tables_blob, tables->linker); 1366 } 1367 if (misc.has_tpm) { 1368 acpi_add_table(table_offsets, tables_blob); 1369 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 1370 1371 acpi_add_table(table_offsets, tables_blob); 1372 build_tpm_ssdt(tables_blob, tables->linker); 1373 } 1374 if (guest_info->numa_nodes) { 1375 acpi_add_table(table_offsets, tables_blob); 1376 build_srat(tables_blob, tables->linker, guest_info); 1377 } 1378 if (acpi_get_mcfg(&mcfg)) { 1379 acpi_add_table(table_offsets, tables_blob); 1380 build_mcfg_q35(tables_blob, tables->linker, &mcfg); 1381 } 1382 if (acpi_has_iommu()) { 1383 acpi_add_table(table_offsets, tables_blob); 1384 build_dmar_q35(tables_blob, tables->linker); 1385 } 1386 1387 /* Add tables supplied by user (if any) */ 1388 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 1389 unsigned len = acpi_table_len(u); 1390 1391 acpi_add_table(table_offsets, tables_blob); 1392 g_array_append_vals(tables_blob, u, len); 1393 } 1394 1395 /* RSDT is pointed to by RSDP */ 1396 rsdt = tables_blob->len; 1397 build_rsdt(tables_blob, tables->linker, table_offsets); 1398 1399 /* RSDP is in FSEG memory, so allocate it separately */ 1400 build_rsdp(tables->rsdp, tables->linker, rsdt); 1401 1402 /* We'll expose it all to Guest so we want to reduce 1403 * chance of size changes. 1404 * 1405 * We used to align the tables to 4k, but of course this would 1406 * too simple to be enough. 4k turned out to be too small an 1407 * alignment very soon, and in fact it is almost impossible to 1408 * keep the table size stable for all (max_cpus, max_memory_slots) 1409 * combinations. So the table size is always 64k for pc-i440fx-2.1 1410 * and we give an error if the table grows beyond that limit. 1411 * 1412 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 1413 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 1414 * than 2.0 and we can always pad the smaller tables with zeros. We can 1415 * then use the exact size of the 2.0 tables. 1416 * 1417 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 1418 */ 1419 if (guest_info->legacy_acpi_table_size) { 1420 /* Subtracting aml_len gives the size of fixed tables. Then add the 1421 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 1422 */ 1423 int legacy_aml_len = 1424 guest_info->legacy_acpi_table_size + 1425 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus; 1426 int legacy_table_size = 1427 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 1428 ACPI_BUILD_ALIGN_SIZE); 1429 if (tables_blob->len > legacy_table_size) { 1430 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 1431 error_report("Warning: migration may not work."); 1432 } 1433 g_array_set_size(tables_blob, legacy_table_size); 1434 } else { 1435 /* Make sure we have a buffer in case we need to resize the tables. */ 1436 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 1437 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 1438 error_report("Warning: ACPI tables are larger than 64k."); 1439 error_report("Warning: migration may not work."); 1440 error_report("Warning: please remove CPUs, NUMA nodes, " 1441 "memory slots or PCI bridges."); 1442 } 1443 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 1444 } 1445 1446 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE); 1447 1448 /* Cleanup memory that's no longer used. */ 1449 g_array_free(table_offsets, true); 1450 } 1451 1452 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 1453 { 1454 uint32_t size = acpi_data_len(data); 1455 1456 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 1457 memory_region_ram_resize(mr, size, &error_abort); 1458 1459 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 1460 memory_region_set_dirty(mr, 0, size); 1461 } 1462 1463 static void acpi_build_update(void *build_opaque, uint32_t offset) 1464 { 1465 AcpiBuildState *build_state = build_opaque; 1466 AcpiBuildTables tables; 1467 1468 /* No state to update or already patched? Nothing to do. */ 1469 if (!build_state || build_state->patched) { 1470 return; 1471 } 1472 build_state->patched = 1; 1473 1474 acpi_build_tables_init(&tables); 1475 1476 acpi_build(build_state->guest_info, &tables); 1477 1478 acpi_ram_update(build_state->table_mr, tables.table_data); 1479 1480 if (build_state->rsdp) { 1481 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 1482 } else { 1483 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 1484 } 1485 1486 acpi_ram_update(build_state->linker_mr, tables.linker); 1487 acpi_build_tables_cleanup(&tables, true); 1488 } 1489 1490 static void acpi_build_reset(void *build_opaque) 1491 { 1492 AcpiBuildState *build_state = build_opaque; 1493 build_state->patched = 0; 1494 } 1495 1496 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 1497 GArray *blob, const char *name, 1498 uint64_t max_size) 1499 { 1500 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 1501 name, acpi_build_update, build_state); 1502 } 1503 1504 static const VMStateDescription vmstate_acpi_build = { 1505 .name = "acpi_build", 1506 .version_id = 1, 1507 .minimum_version_id = 1, 1508 .fields = (VMStateField[]) { 1509 VMSTATE_UINT8(patched, AcpiBuildState), 1510 VMSTATE_END_OF_LIST() 1511 }, 1512 }; 1513 1514 void acpi_setup(PcGuestInfo *guest_info) 1515 { 1516 AcpiBuildTables tables; 1517 AcpiBuildState *build_state; 1518 1519 if (!guest_info->fw_cfg) { 1520 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 1521 return; 1522 } 1523 1524 if (!guest_info->has_acpi_build) { 1525 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 1526 return; 1527 } 1528 1529 if (!acpi_enabled) { 1530 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 1531 return; 1532 } 1533 1534 build_state = g_malloc0(sizeof *build_state); 1535 1536 build_state->guest_info = guest_info; 1537 1538 acpi_set_pci_info(); 1539 1540 acpi_build_tables_init(&tables); 1541 acpi_build(build_state->guest_info, &tables); 1542 1543 /* Now expose it all to Guest */ 1544 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 1545 ACPI_BUILD_TABLE_FILE, 1546 ACPI_BUILD_TABLE_MAX_SIZE); 1547 assert(build_state->table_mr != NULL); 1548 1549 build_state->linker_mr = 1550 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 1551 1552 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 1553 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 1554 1555 if (!guest_info->rsdp_in_ram) { 1556 /* 1557 * Keep for compatibility with old machine types. 1558 * Though RSDP is small, its contents isn't immutable, so 1559 * we'll update it along with the rest of tables on guest access. 1560 */ 1561 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 1562 1563 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 1564 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE, 1565 acpi_build_update, build_state, 1566 build_state->rsdp, rsdp_size); 1567 build_state->rsdp_mr = NULL; 1568 } else { 1569 build_state->rsdp = NULL; 1570 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 1571 ACPI_BUILD_RSDP_FILE, 0); 1572 } 1573 1574 qemu_register_reset(acpi_build_reset, build_state); 1575 acpi_build_reset(build_state); 1576 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 1577 1578 /* Cleanup tables but don't free the memory: we track it 1579 * in build_state. 1580 */ 1581 acpi_build_tables_cleanup(&tables, false); 1582 } 1583