fsl-imx25.c (c221287f8ff4e46fffad11bb2a6bc99442e845be) fsl-imx25.c (9bca0edb282de0007a4f068d9d20f3e3c3aadef7)
1/*
2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
3 *
4 * i.MX25 SOC emulation.
5 *
6 * Based on hw/arm/xlnx-zynqmp.c
7 *
8 * Copyright (C) 2015 Xilinx Inc

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113 { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
114 { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
115 { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
116 { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
117 { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
118 };
119
120 if (i < MAX_SERIAL_PORTS) {
1/*
2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
3 *
4 * i.MX25 SOC emulation.
5 *
6 * Based on hw/arm/xlnx-zynqmp.c
7 *
8 * Copyright (C) 2015 Xilinx Inc

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113 { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
114 { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
115 { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
116 { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
117 { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
118 };
119
120 if (i < MAX_SERIAL_PORTS) {
121 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]);
121 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
122 }
123
124 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
125 if (err) {
126 error_propagate(errp, err);
127 return;
128 }
129 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);

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123
124 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
125 if (err) {
126 error_propagate(errp, err);
127 return;
128 }
129 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);

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