1 /* 2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX25 SOC emulation. 5 * 6 * Based on hw/arm/xlnx-zynqmp.c 7 * 8 * Copyright (C) 2015 Xilinx Inc 9 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 19 * for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "qemu-common.h" 28 #include "cpu.h" 29 #include "hw/arm/fsl-imx25.h" 30 #include "sysemu/sysemu.h" 31 #include "exec/address-spaces.h" 32 #include "hw/boards.h" 33 #include "chardev/char.h" 34 35 static void fsl_imx25_init(Object *obj) 36 { 37 FslIMX25State *s = FSL_IMX25(obj); 38 int i; 39 40 object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU); 41 42 object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC); 43 qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default()); 44 45 object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM); 46 qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default()); 47 48 for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { 49 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL); 50 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 51 } 52 53 for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { 54 object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX25_GPT); 55 qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus_get_default()); 56 } 57 58 for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { 59 object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT); 60 qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default()); 61 } 62 63 object_initialize(&s->fec, sizeof(s->fec), TYPE_IMX_FEC); 64 qdev_set_parent_bus(DEVICE(&s->fec), sysbus_get_default()); 65 66 for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { 67 object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C); 68 qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default()); 69 } 70 71 for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { 72 object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO); 73 qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default()); 74 } 75 } 76 77 static void fsl_imx25_realize(DeviceState *dev, Error **errp) 78 { 79 FslIMX25State *s = FSL_IMX25(dev); 80 uint8_t i; 81 Error *err = NULL; 82 83 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 84 if (err) { 85 error_propagate(errp, err); 86 return; 87 } 88 89 object_property_set_bool(OBJECT(&s->avic), true, "realized", &err); 90 if (err) { 91 error_propagate(errp, err); 92 return; 93 } 94 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR); 95 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, 96 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 97 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, 98 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 99 100 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); 101 if (err) { 102 error_propagate(errp, err); 103 return; 104 } 105 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR); 106 107 /* Initialize all UARTs */ 108 for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { 109 static const struct { 110 hwaddr addr; 111 unsigned int irq; 112 } serial_table[FSL_IMX25_NUM_UARTS] = { 113 { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ }, 114 { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ }, 115 { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ }, 116 { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ }, 117 { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ } 118 }; 119 120 if (i < MAX_SERIAL_PORTS) { 121 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 122 } 123 124 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 125 if (err) { 126 error_propagate(errp, err); 127 return; 128 } 129 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 130 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 131 qdev_get_gpio_in(DEVICE(&s->avic), 132 serial_table[i].irq)); 133 } 134 135 /* Initialize all GPT timers */ 136 for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { 137 static const struct { 138 hwaddr addr; 139 unsigned int irq; 140 } gpt_table[FSL_IMX25_NUM_GPTS] = { 141 { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ }, 142 { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ }, 143 { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ }, 144 { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ } 145 }; 146 147 s->gpt[i].ccm = IMX_CCM(&s->ccm); 148 149 object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err); 150 if (err) { 151 error_propagate(errp, err); 152 return; 153 } 154 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr); 155 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, 156 qdev_get_gpio_in(DEVICE(&s->avic), 157 gpt_table[i].irq)); 158 } 159 160 /* Initialize all EPIT timers */ 161 for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { 162 static const struct { 163 hwaddr addr; 164 unsigned int irq; 165 } epit_table[FSL_IMX25_NUM_EPITS] = { 166 { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ }, 167 { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ } 168 }; 169 170 s->epit[i].ccm = IMX_CCM(&s->ccm); 171 172 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); 173 if (err) { 174 error_propagate(errp, err); 175 return; 176 } 177 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 178 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 179 qdev_get_gpio_in(DEVICE(&s->avic), 180 epit_table[i].irq)); 181 } 182 183 qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]); 184 185 object_property_set_bool(OBJECT(&s->fec), true, "realized", &err); 186 if (err) { 187 error_propagate(errp, err); 188 return; 189 } 190 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR); 191 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0, 192 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ)); 193 194 195 /* Initialize all I2C */ 196 for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { 197 static const struct { 198 hwaddr addr; 199 unsigned int irq; 200 } i2c_table[FSL_IMX25_NUM_I2CS] = { 201 { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ }, 202 { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ }, 203 { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ } 204 }; 205 206 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); 207 if (err) { 208 error_propagate(errp, err); 209 return; 210 } 211 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 212 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 213 qdev_get_gpio_in(DEVICE(&s->avic), 214 i2c_table[i].irq)); 215 } 216 217 /* Initialize all GPIOs */ 218 for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { 219 static const struct { 220 hwaddr addr; 221 unsigned int irq; 222 } gpio_table[FSL_IMX25_NUM_GPIOS] = { 223 { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ }, 224 { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ }, 225 { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ }, 226 { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ } 227 }; 228 229 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); 230 if (err) { 231 error_propagate(errp, err); 232 return; 233 } 234 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 235 /* Connect GPIO IRQ to PIC */ 236 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 237 qdev_get_gpio_in(DEVICE(&s->avic), 238 gpio_table[i].irq)); 239 } 240 241 /* initialize 2 x 16 KB ROM */ 242 memory_region_init_rom(&s->rom[0], NULL, 243 "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err); 244 if (err) { 245 error_propagate(errp, err); 246 return; 247 } 248 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR, 249 &s->rom[0]); 250 memory_region_init_rom(&s->rom[1], NULL, 251 "imx25.rom1", FSL_IMX25_ROM1_SIZE, &err); 252 if (err) { 253 error_propagate(errp, err); 254 return; 255 } 256 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR, 257 &s->rom[1]); 258 259 /* initialize internal RAM (128 KB) */ 260 memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE, 261 &err); 262 if (err) { 263 error_propagate(errp, err); 264 return; 265 } 266 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR, 267 &s->iram); 268 269 /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */ 270 memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias", 271 &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE); 272 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR, 273 &s->iram_alias); 274 } 275 276 static void fsl_imx25_class_init(ObjectClass *oc, void *data) 277 { 278 DeviceClass *dc = DEVICE_CLASS(oc); 279 280 dc->realize = fsl_imx25_realize; 281 dc->desc = "i.MX25 SOC"; 282 /* 283 * Reason: uses serial_hds in realize and the imx25 board does not 284 * support multiple CPUs 285 */ 286 dc->user_creatable = false; 287 } 288 289 static const TypeInfo fsl_imx25_type_info = { 290 .name = TYPE_FSL_IMX25, 291 .parent = TYPE_DEVICE, 292 .instance_size = sizeof(FslIMX25State), 293 .instance_init = fsl_imx25_init, 294 .class_init = fsl_imx25_class_init, 295 }; 296 297 static void fsl_imx25_register_types(void) 298 { 299 type_register_static(&fsl_imx25_type_info); 300 } 301 302 type_init(fsl_imx25_register_types) 303