aspeed_ast2600.c (f4d7517c4560c7ae31d1e79f5db5b37df22c5c90) aspeed_ast2600.c (42bea956f6f7477c06186c7add62fa0107a27a9c)
1/*
2 * ASPEED SoC 2600 family
3 *
4 * Copyright (c) 2016-2019, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */

--- 30 unchanged lines hidden (view full) ---

39 [ASPEED_DEV_ETH1] = 0x1E660000,
40 [ASPEED_DEV_ETH3] = 0x1E670000,
41 [ASPEED_DEV_ETH2] = 0x1E680000,
42 [ASPEED_DEV_ETH4] = 0x1E690000,
43 [ASPEED_DEV_VIC] = 0x1E6C0000,
44 [ASPEED_DEV_HACE] = 0x1E6D0000,
45 [ASPEED_DEV_SDMC] = 0x1E6E0000,
46 [ASPEED_DEV_SCU] = 0x1E6E2000,
1/*
2 * ASPEED SoC 2600 family
3 *
4 * Copyright (c) 2016-2019, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */

--- 30 unchanged lines hidden (view full) ---

39 [ASPEED_DEV_ETH1] = 0x1E660000,
40 [ASPEED_DEV_ETH3] = 0x1E670000,
41 [ASPEED_DEV_ETH2] = 0x1E680000,
42 [ASPEED_DEV_ETH4] = 0x1E690000,
43 [ASPEED_DEV_VIC] = 0x1E6C0000,
44 [ASPEED_DEV_HACE] = 0x1E6D0000,
45 [ASPEED_DEV_SDMC] = 0x1E6E0000,
46 [ASPEED_DEV_SCU] = 0x1E6E2000,
47 [ASPEED_DEV_GFX] = 0x1E6E6000,
48 [ASPEED_DEV_XDMA] = 0x1E6E7000,
49 [ASPEED_DEV_ADC] = 0x1E6E9000,
50 [ASPEED_DEV_DP] = 0x1E6EB000,
47 [ASPEED_DEV_XDMA] = 0x1E6E7000,
48 [ASPEED_DEV_ADC] = 0x1E6E9000,
49 [ASPEED_DEV_DP] = 0x1E6EB000,
51 [ASPEED_DEV_PCIE_PHY1] = 0x1E6ED000,
52 [ASPEED_DEV_PCIE_PHY2] = 0x1E6ED200,
53 [ASPEED_DEV_SBC] = 0x1E6F2000,
54 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000,
55 [ASPEED_DEV_VIDEO] = 0x1E700000,
56 [ASPEED_DEV_SDHCI] = 0x1E740000,
57 [ASPEED_DEV_EMMC] = 0x1E750000,
50 [ASPEED_DEV_SBC] = 0x1E6F2000,
51 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000,
52 [ASPEED_DEV_VIDEO] = 0x1E700000,
53 [ASPEED_DEV_SDHCI] = 0x1E740000,
54 [ASPEED_DEV_EMMC] = 0x1E750000,
58 [ASPEED_DEV_PCIE] = 0x1E770000,
59 [ASPEED_DEV_GPIO] = 0x1E780000,
60 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800,
61 [ASPEED_DEV_RTC] = 0x1E781000,
62 [ASPEED_DEV_TIMER1] = 0x1E782000,
63 [ASPEED_DEV_WDT] = 0x1E785000,
64 [ASPEED_DEV_LPC] = 0x1E789000,
65 [ASPEED_DEV_IBT] = 0x1E789140,
66 [ASPEED_DEV_I2C] = 0x1E78A000,

--- 7 unchanged lines hidden (view full) ---

74 [ASPEED_DEV_UART7] = 0x1E790100,
75 [ASPEED_DEV_UART8] = 0x1E790200,
76 [ASPEED_DEV_UART9] = 0x1E790300,
77 [ASPEED_DEV_UART10] = 0x1E790400,
78 [ASPEED_DEV_UART11] = 0x1E790500,
79 [ASPEED_DEV_UART12] = 0x1E790600,
80 [ASPEED_DEV_UART13] = 0x1E790700,
81 [ASPEED_DEV_VUART] = 0x1E787000,
55 [ASPEED_DEV_GPIO] = 0x1E780000,
56 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800,
57 [ASPEED_DEV_RTC] = 0x1E781000,
58 [ASPEED_DEV_TIMER1] = 0x1E782000,
59 [ASPEED_DEV_WDT] = 0x1E785000,
60 [ASPEED_DEV_LPC] = 0x1E789000,
61 [ASPEED_DEV_IBT] = 0x1E789140,
62 [ASPEED_DEV_I2C] = 0x1E78A000,

--- 7 unchanged lines hidden (view full) ---

70 [ASPEED_DEV_UART7] = 0x1E790100,
71 [ASPEED_DEV_UART8] = 0x1E790200,
72 [ASPEED_DEV_UART9] = 0x1E790300,
73 [ASPEED_DEV_UART10] = 0x1E790400,
74 [ASPEED_DEV_UART11] = 0x1E790500,
75 [ASPEED_DEV_UART12] = 0x1E790600,
76 [ASPEED_DEV_UART13] = 0x1E790700,
77 [ASPEED_DEV_VUART] = 0x1E787000,
82 [ASPEED_DEV_FSI1] = 0x1E79B000,
83 [ASPEED_DEV_FSI2] = 0x1E79B100,
84 [ASPEED_DEV_I3C] = 0x1E7A0000,
78 [ASPEED_DEV_I3C] = 0x1E7A0000,
85 [ASPEED_DEV_PCIE_MMIO1] = 0x60000000,
86 [ASPEED_DEV_PCIE_MMIO2] = 0x70000000,
87 [ASPEED_DEV_SDRAM] = 0x80000000,
88};
89
90#define ASPEED_A7MPCORE_ADDR 0x40460000
91
92#define AST2600_MAX_IRQ 197
93
94/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */

--- 32 unchanged lines hidden (view full) ---

127 [ASPEED_DEV_TIMER6] = 21,
128 [ASPEED_DEV_TIMER7] = 22,
129 [ASPEED_DEV_TIMER8] = 23,
130 [ASPEED_DEV_WDT] = 24,
131 [ASPEED_DEV_PWM] = 44,
132 [ASPEED_DEV_LPC] = 35,
133 [ASPEED_DEV_IBT] = 143,
134 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */
79 [ASPEED_DEV_SDRAM] = 0x80000000,
80};
81
82#define ASPEED_A7MPCORE_ADDR 0x40460000
83
84#define AST2600_MAX_IRQ 197
85
86/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */

--- 32 unchanged lines hidden (view full) ---

119 [ASPEED_DEV_TIMER6] = 21,
120 [ASPEED_DEV_TIMER7] = 22,
121 [ASPEED_DEV_TIMER8] = 23,
122 [ASPEED_DEV_WDT] = 24,
123 [ASPEED_DEV_PWM] = 44,
124 [ASPEED_DEV_LPC] = 35,
125 [ASPEED_DEV_IBT] = 143,
126 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */
135 [ASPEED_DEV_PCIE] = 167, /* 167 -> 168 */
136 [ASPEED_DEV_PECI] = 38,
137 [ASPEED_DEV_ETH1] = 2,
138 [ASPEED_DEV_ETH2] = 3,
139 [ASPEED_DEV_HACE] = 4,
140 [ASPEED_DEV_ETH3] = 32,
141 [ASPEED_DEV_ETH4] = 33,
142 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
143 [ASPEED_DEV_DP] = 62,
127 [ASPEED_DEV_PECI] = 38,
128 [ASPEED_DEV_ETH1] = 2,
129 [ASPEED_DEV_ETH2] = 3,
130 [ASPEED_DEV_HACE] = 4,
131 [ASPEED_DEV_ETH3] = 32,
132 [ASPEED_DEV_ETH4] = 33,
133 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
134 [ASPEED_DEV_DP] = 62,
144 [ASPEED_DEV_FSI1] = 100,
145 [ASPEED_DEV_FSI2] = 101,
146 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */
147};
148
149static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
150{
151 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
152
153 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);

--- 29 unchanged lines hidden (view full) ---

183 object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
184 TYPE_A15MPCORE_PRIV);
185
186 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
187
188 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
189 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
190
135 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */
136};
137
138static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
139{
140 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
141
142 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);

--- 29 unchanged lines hidden (view full) ---

172 object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
173 TYPE_A15MPCORE_PRIV);
174
175 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
176
177 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
178 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
179
191 for (i = 0; i < sc->wdts_num; i++) {
192 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
193 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
194 }
195
196 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
197 object_initialize_child(obj, "adc", &s->adc, typename);
198
199 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
200 object_initialize_child(obj, "i2c", &s->i2c, typename);
201
180 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
181 object_initialize_child(obj, "adc", &s->adc, typename);
182
183 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
184 object_initialize_child(obj, "i2c", &s->i2c, typename);
185
202 object_initialize_child(obj, "pcie-rc", &s->pcie, TYPE_ASPEED_PCIE_CFG);
203
204 for (i = 0; i < ARRAY_SIZE(s->pcie_phy); i++) {
205 object_initialize_child(obj, "pcie-phy[*]", &s->pcie_phy[i],
206 TYPE_ASPEED_PCIE_PHY);
207 }
208
209 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
210
211 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
212 object_initialize_child(obj, "fmc", &s->fmc, typename);
213
214 for (i = 0; i < sc->spis_num; i++) {
215 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
216 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);

--- 4 unchanged lines hidden (view full) ---

221 TYPE_PLATFORM_EHCI);
222 }
223
224 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
225 object_initialize_child(obj, "sdmc", &s->sdmc, typename);
226 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
227 "ram-size");
228
186 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
187
188 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
189 object_initialize_child(obj, "fmc", &s->fmc, typename);
190
191 for (i = 0; i < sc->spis_num; i++) {
192 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
193 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);

--- 4 unchanged lines hidden (view full) ---

198 TYPE_PLATFORM_EHCI);
199 }
200
201 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
202 object_initialize_child(obj, "sdmc", &s->sdmc, typename);
203 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
204 "ram-size");
205
206 for (i = 0; i < sc->wdts_num; i++) {
207 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
208 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
209 }
210
229 for (i = 0; i < sc->macs_num; i++) {
230 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
231 TYPE_FTGMAC100);
232
233 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
234 }
235
236 for (i = 0; i < sc->uarts_num; i++) {

--- 25 unchanged lines hidden (view full) ---

262
263 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);
264
265 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
266 TYPE_SYSBUS_SDHCI);
267
268 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
269
211 for (i = 0; i < sc->macs_num; i++) {
212 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
213 TYPE_FTGMAC100);
214
215 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
216 }
217
218 for (i = 0; i < sc->uarts_num; i++) {

--- 25 unchanged lines hidden (view full) ---

244
245 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);
246
247 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
248 TYPE_SYSBUS_SDHCI);
249
250 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
251
270 object_initialize_child(obj, "ibt", &s->ibt, TYPE_ASPEED_IBT);
271
272 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
273 object_initialize_child(obj, "hace", &s->hace, typename);
274
275 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
276
277 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
278
252 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
253 object_initialize_child(obj, "hace", &s->hace, typename);
254
255 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
256
257 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
258
279 object_initialize_child(obj, "gfx", &s->gfx, TYPE_ASPEED_GFX);
280
281 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
282 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
283 object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE);
284 object_initialize_child(obj, "emmc-boot-controller",
285 &s->emmc_boot_controller,
286 TYPE_UNIMPLEMENTED_DEVICE);
259 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
260 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
261 object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE);
262 object_initialize_child(obj, "emmc-boot-controller",
263 &s->emmc_boot_controller,
264 TYPE_UNIMPLEMENTED_DEVICE);
287
288 object_initialize_child(obj, "pwm", &s->pwm, TYPE_ASPEED_PWM);
289
290 object_initialize_child(obj, "fsi[*]", &s->fsi[0], TYPE_ASPEED_APB2OPB);
291}
292
293/*
294 * ASPEED ast2600 has 0xf as cluster ID
295 *
296 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register
297 */
298static uint64_t aspeed_calc_affinity(int cpu)

--- 114 unchanged lines hidden (view full) ---

413 }
414 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
415 sc->memmap[ASPEED_DEV_TIMER1]);
416 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
417 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
418 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
419 }
420
265}
266
267/*
268 * ASPEED ast2600 has 0xf as cluster ID
269 *
270 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register
271 */
272static uint64_t aspeed_calc_affinity(int cpu)

--- 114 unchanged lines hidden (view full) ---

387 }
388 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
389 sc->memmap[ASPEED_DEV_TIMER1]);
390 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
391 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
392 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
393 }
394
421 /* Watch dog */
422 for (i = 0; i < sc->wdts_num; i++) {
423 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
424
425 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
426 &error_abort);
427 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
428 return;
429 }
430 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
431 sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize);
432 }
433
434 /* ADC */
435 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
436 return;
437 }
438 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
439 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
440 aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
441

--- 20 unchanged lines hidden (view full) ---

462 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
463 return;
464 }
465 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
466 sc->memmap[ASPEED_DEV_PECI]);
467 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
468 aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
469
395 /* ADC */
396 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
397 return;
398 }
399 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
400 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
401 aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
402

--- 20 unchanged lines hidden (view full) ---

423 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
424 return;
425 }
426 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
427 sc->memmap[ASPEED_DEV_PECI]);
428 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
429 aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
430
470 /* PCIe */
471 for (i = 0; i < ARRAY_SIZE(s->pcie_phy); i++) {
472 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy[i]), errp)) {
473 return;
474 }
475 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie_phy[i]), 0,
476 sc->memmap[ASPEED_DEV_PCIE_PHY1 + i]);
477 }
478
479 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) {
480 return;
481 }
482 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie), 0,
483 sc->memmap[ASPEED_DEV_PCIE]);
484
485 for (i = 0; i < ARRAY_SIZE(s->pcie.rcs); i++) {
486 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
487 sc->irqmap[ASPEED_DEV_PCIE] + i);
488 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie.rcs[i]), 0, irq);
489 }
490
491 for (i = 0; i < ARRAY_SIZE(s->pcie.rcs); i++) {
492 g_autofree char *name = g_strdup_printf("pcie-mmio-%d", i);
493 MemoryRegion *mmio_alias;
494 MemoryRegion *mmio_mr;
495
496 mmio_alias = g_new0(MemoryRegion, 1);
497 mmio_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pcie.rcs[i]), 1);
498
499 memory_region_init_alias(mmio_alias, OBJECT(&s->pcie.rcs[i]), name,
500 mmio_mr, sc->memmap[ASPEED_DEV_PCIE_MMIO1 + i],
501 0x10000000);
502
503 memory_region_add_subregion(s->memory,
504 sc->memmap[ASPEED_DEV_PCIE_MMIO1 + i],
505 mmio_alias);
506 }
507
508 /* FMC, The number of CS is set at the board level */
431 /* FMC, The number of CS is set at the board level */
509 object_property_set_link(OBJECT(&s->fmc), "wdt2", OBJECT(&s->wdt[2].iomem),
510 &error_abort);
511 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
512 &error_abort);
513 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
514 return;
515 }
516 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
517 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
518 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);

--- 32 unchanged lines hidden (view full) ---

551
552 /* SDMC - SDRAM Memory Controller */
553 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
554 return;
555 }
556 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
557 sc->memmap[ASPEED_DEV_SDMC]);
558
432 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
433 &error_abort);
434 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
435 return;
436 }
437 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
438 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
439 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);

--- 32 unchanged lines hidden (view full) ---

472
473 /* SDMC - SDRAM Memory Controller */
474 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
475 return;
476 }
477 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
478 sc->memmap[ASPEED_DEV_SDMC]);
479
480 /* Watch dog */
481 for (i = 0; i < sc->wdts_num; i++) {
482 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
483 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
484
485 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
486 &error_abort);
487 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
488 return;
489 }
490 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
491 }
492
559 /* RAM */
560 if (!aspeed_soc_dram_init(s, errp)) {
561 return;
562 }
563
564 /* Net */
565 for (i = 0; i < sc->macs_num; i++) {
566 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,

--- 88 unchanged lines hidden (view full) ---

655 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
656 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
657 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
658
659 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
660 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
661 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
662
493 /* RAM */
494 if (!aspeed_soc_dram_init(s, errp)) {
495 return;
496 }
497
498 /* Net */
499 for (i = 0; i < sc->macs_num; i++) {
500 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,

--- 88 unchanged lines hidden (view full) ---

589 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
590 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
591 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
592
593 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
594 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
595 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
596
663 /* iBT */
664 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ibt), errp)) {
665 return;
666 }
667 memory_region_add_subregion(&s->lpc.iomem,
668 sc->memmap[ASPEED_DEV_IBT] - sc->memmap[ASPEED_DEV_LPC],
669 &s->ibt.iomem);
670 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ibt), 0,
671 aspeed_soc_get_irq(s, ASPEED_DEV_IBT));
672
673 /* HACE */
674 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
675 &error_abort);
676 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
677 return;
678 }
679 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
680 sc->memmap[ASPEED_DEV_HACE]);

--- 12 unchanged lines hidden (view full) ---

693 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
694 }
695
696 /* Secure Boot Controller */
697 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
698 return;
699 }
700 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
597 /* HACE */
598 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
599 &error_abort);
600 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
601 return;
602 }
603 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
604 sc->memmap[ASPEED_DEV_HACE]);

--- 12 unchanged lines hidden (view full) ---

617 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
618 }
619
620 /* Secure Boot Controller */
621 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
622 return;
623 }
624 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
701
702 /* GFX */
703 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gfx), errp)) {
704 return;
705 }
706 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gfx), 0, sc->memmap[ASPEED_DEV_GFX]);
707 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gfx), 0,
708 aspeed_soc_get_irq(s, ASPEED_DEV_GFX));
709
710 /* PWM */
711 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp)) {
712 return;
713 }
714 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pwm), 0, sc->memmap[ASPEED_DEV_PWM]);
715 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm), 0,
716 aspeed_soc_get_irq(s, ASPEED_DEV_PWM));
717
718 /* FSI */
719 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[0]), errp)) {
720 return;
721 }
722 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fsi[0]), 0,
723 sc->memmap[ASPEED_DEV_FSI1]);
724 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[0]), 0,
725 aspeed_soc_get_irq(s, ASPEED_DEV_FSI1));
726}
727
728static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
729{
730 DeviceClass *dc = DEVICE_CLASS(oc);
731 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
732
733 dc->realize = aspeed_soc_ast2600_realize;

--- 6 unchanged lines hidden (view full) ---

740 sc->ehcis_num = 2;
741 sc->wdts_num = 4;
742 sc->macs_num = 4;
743 sc->uarts_num = 13;
744 sc->irqmap = aspeed_soc_ast2600_irqmap;
745 sc->memmap = aspeed_soc_ast2600_memmap;
746 sc->num_cpus = 2;
747 sc->get_irq = aspeed_soc_ast2600_get_irq;
625}
626
627static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
628{
629 DeviceClass *dc = DEVICE_CLASS(oc);
630 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
631
632 dc->realize = aspeed_soc_ast2600_realize;

--- 6 unchanged lines hidden (view full) ---

639 sc->ehcis_num = 2;
640 sc->wdts_num = 4;
641 sc->macs_num = 4;
642 sc->uarts_num = 13;
643 sc->irqmap = aspeed_soc_ast2600_irqmap;
644 sc->memmap = aspeed_soc_ast2600_memmap;
645 sc->num_cpus = 2;
646 sc->get_irq = aspeed_soc_ast2600_get_irq;
748 sc->boot_emmc = true;
749}
750
751static const TypeInfo aspeed_soc_ast2600_type_info = {
752 .name = "ast2600-a3",
753 .parent = TYPE_ASPEED_SOC,
754 .instance_size = sizeof(AspeedSoCState),
755 .instance_init = aspeed_soc_ast2600_init,
756 .class_init = aspeed_soc_ast2600_class_init,
757 .class_size = sizeof(AspeedSoCClass),
758};
759
760static void aspeed_soc_register_types(void)
761{
762 type_register_static(&aspeed_soc_ast2600_type_info);
763};
764
765type_init(aspeed_soc_register_types)
647}
648
649static const TypeInfo aspeed_soc_ast2600_type_info = {
650 .name = "ast2600-a3",
651 .parent = TYPE_ASPEED_SOC,
652 .instance_size = sizeof(AspeedSoCState),
653 .instance_init = aspeed_soc_ast2600_init,
654 .class_init = aspeed_soc_ast2600_class_init,
655 .class_size = sizeof(AspeedSoCClass),
656};
657
658static void aspeed_soc_register_types(void)
659{
660 type_register_static(&aspeed_soc_ast2600_type_info);
661};
662
663type_init(aspeed_soc_register_types)