allwinner-a10.c (423ec28bb8c20d9dfa68faef50699772899ab64d) allwinner-a10.c (edd3a59d5b98964ed72265346cb4dc7e9ffccd27)
1/*
2 * Allwinner A10 SoC emulation
3 *
4 * Copyright (C) 2013 Li Guang
5 * Written by Li Guang <lig.fnst@cn.fujitsu.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the

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20#include "qemu/module.h"
21#include "hw/sysbus.h"
22#include "hw/arm/allwinner-a10.h"
23#include "hw/misc/unimp.h"
24#include "sysemu/sysemu.h"
25#include "hw/boards.h"
26#include "hw/usb/hcd-ohci.h"
27
1/*
2 * Allwinner A10 SoC emulation
3 *
4 * Copyright (C) 2013 Li Guang
5 * Written by Li Guang <lig.fnst@cn.fujitsu.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the

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20#include "qemu/module.h"
21#include "hw/sysbus.h"
22#include "hw/arm/allwinner-a10.h"
23#include "hw/misc/unimp.h"
24#include "sysemu/sysemu.h"
25#include "hw/boards.h"
26#include "hw/usb/hcd-ohci.h"
27
28#define AW_A10_DRAMC_BASE 0x01c01000
28#define AW_A10_MMC0_BASE 0x01c0f000
29#define AW_A10_CCM_BASE 0x01c20000
30#define AW_A10_PIC_REG_BASE 0x01c20400
31#define AW_A10_PIT_REG_BASE 0x01c20c00
32#define AW_A10_UART0_REG_BASE 0x01c28000
33#define AW_A10_EMAC_BASE 0x01c0b000
34#define AW_A10_EHCI_BASE 0x01c14000
35#define AW_A10_OHCI_BASE 0x01c14400

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44 ARM_CPU_TYPE_NAME("cortex-a8"));
45
46 object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC);
47
48 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
49
50 object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
51
29#define AW_A10_MMC0_BASE 0x01c0f000
30#define AW_A10_CCM_BASE 0x01c20000
31#define AW_A10_PIC_REG_BASE 0x01c20400
32#define AW_A10_PIT_REG_BASE 0x01c20c00
33#define AW_A10_UART0_REG_BASE 0x01c28000
34#define AW_A10_EMAC_BASE 0x01c0b000
35#define AW_A10_EHCI_BASE 0x01c14000
36#define AW_A10_OHCI_BASE 0x01c14400

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45 ARM_CPU_TYPE_NAME("cortex-a8"));
46
47 object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC);
48
49 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
50
51 object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
52
53 object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_A10_DRAMC);
54
52 object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
53
54 object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
55
56 if (machine_usb(current_machine)) {
57 int i;
58
59 for (i = 0; i < AW_A10_NUM_USB; i++) {

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105 &error_fatal);
106 memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
107 create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
108
109 /* Clock Control Module */
110 sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
111 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
112
55 object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
56
57 object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
58
59 if (machine_usb(current_machine)) {
60 int i;
61
62 for (i = 0; i < AW_A10_NUM_USB; i++) {

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108 &error_fatal);
109 memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
110 create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
111
112 /* Clock Control Module */
113 sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
114 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
115
116 /* DRAM Control Module */
117 sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
118 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, AW_A10_DRAMC_BASE);
119
113 /* FIXME use qdev NIC properties instead of nd_table[] */
114 if (nd_table[0].used) {
115 qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
116 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
117 }
118 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), errp)) {
119 return;
120 }

--- 76 unchanged lines hidden --- 		120 /* FIXME use qdev NIC properties instead of nd_table[] */
121 if (nd_table[0].used) {
122 qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
123 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
124 }
125 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), errp)) {
126 return;
127 }

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