1 /* 2 * Allwinner A10 SoC emulation 3 * 4 * Copyright (C) 2013 Li Guang 5 * Written by Li Guang <lig.fnst@cn.fujitsu.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu/module.h" 21 #include "hw/sysbus.h" 22 #include "hw/arm/allwinner-a10.h" 23 #include "hw/misc/unimp.h" 24 #include "sysemu/sysemu.h" 25 #include "hw/boards.h" 26 #include "hw/usb/hcd-ohci.h" 27 28 #define AW_A10_MMC0_BASE 0x01c0f000 29 #define AW_A10_CCM_BASE 0x01c20000 30 #define AW_A10_PIC_REG_BASE 0x01c20400 31 #define AW_A10_PIT_REG_BASE 0x01c20c00 32 #define AW_A10_UART0_REG_BASE 0x01c28000 33 #define AW_A10_EMAC_BASE 0x01c0b000 34 #define AW_A10_EHCI_BASE 0x01c14000 35 #define AW_A10_OHCI_BASE 0x01c14400 36 #define AW_A10_SATA_BASE 0x01c18000 37 #define AW_A10_RTC_BASE 0x01c20d00 38 39 static void aw_a10_init(Object *obj) 40 { 41 AwA10State *s = AW_A10(obj); 42 43 object_initialize_child(obj, "cpu", &s->cpu, 44 ARM_CPU_TYPE_NAME("cortex-a8")); 45 46 object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC); 47 48 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT); 49 50 object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM); 51 52 object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC); 53 54 object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI); 55 56 if (machine_usb(current_machine)) { 57 int i; 58 59 for (i = 0; i < AW_A10_NUM_USB; i++) { 60 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 61 TYPE_PLATFORM_EHCI); 62 object_initialize_child(obj, "ohci[*]", &s->ohci[i], 63 TYPE_SYSBUS_OHCI); 64 } 65 } 66 67 object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I); 68 69 object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I); 70 } 71 72 static void aw_a10_realize(DeviceState *dev, Error **errp) 73 { 74 AwA10State *s = AW_A10(dev); 75 SysBusDevice *sysbusdev; 76 77 if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { 78 return; 79 } 80 81 if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), errp)) { 82 return; 83 } 84 sysbusdev = SYS_BUS_DEVICE(&s->intc); 85 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE); 86 sysbus_connect_irq(sysbusdev, 0, 87 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 88 sysbus_connect_irq(sysbusdev, 1, 89 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 90 qdev_pass_gpios(DEVICE(&s->intc), dev, NULL); 91 92 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) { 93 return; 94 } 95 sysbusdev = SYS_BUS_DEVICE(&s->timer); 96 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE); 97 sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22)); 98 sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23)); 99 sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24)); 100 sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25)); 101 sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67)); 102 sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68)); 103 104 memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB, 105 &error_fatal); 106 memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a); 107 create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB); 108 109 /* Clock Control Module */ 110 sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal); 111 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE); 112 113 /* FIXME use qdev NIC properties instead of nd_table[] */ 114 if (nd_table[0].used) { 115 qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); 116 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); 117 } 118 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), errp)) { 119 return; 120 } 121 sysbusdev = SYS_BUS_DEVICE(&s->emac); 122 sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE); 123 sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55)); 124 125 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) { 126 return; 127 } 128 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE); 129 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56)); 130 131 /* FIXME use a qdev chardev prop instead of serial_hd() */ 132 serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, 133 qdev_get_gpio_in(dev, 1), 134 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 135 136 if (machine_usb(current_machine)) { 137 int i; 138 139 for (i = 0; i < AW_A10_NUM_USB; i++) { 140 g_autofree char *bus = g_strdup_printf("usb-bus.%d", i); 141 142 object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", 143 true, &error_fatal); 144 sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal); 145 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 146 AW_A10_EHCI_BASE + i * 0x8000); 147 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 148 qdev_get_gpio_in(dev, 39 + i)); 149 150 object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus, 151 &error_fatal); 152 sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal); 153 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0, 154 AW_A10_OHCI_BASE + i * 0x8000); 155 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0, 156 qdev_get_gpio_in(dev, 64 + i)); 157 } 158 } 159 160 /* SD/MMC */ 161 object_property_set_link(OBJECT(&s->mmc0), "dma-memory", 162 OBJECT(get_system_memory()), &error_fatal); 163 sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal); 164 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE); 165 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32)); 166 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), 167 "sd-bus"); 168 169 /* RTC */ 170 sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal); 171 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10); 172 } 173 174 static void aw_a10_class_init(ObjectClass *oc, void *data) 175 { 176 DeviceClass *dc = DEVICE_CLASS(oc); 177 178 dc->realize = aw_a10_realize; 179 /* Reason: Uses serial_hds and nd_table in realize function */ 180 dc->user_creatable = false; 181 } 182 183 static const TypeInfo aw_a10_type_info = { 184 .name = TYPE_AW_A10, 185 .parent = TYPE_DEVICE, 186 .instance_size = sizeof(AwA10State), 187 .instance_init = aw_a10_init, 188 .class_init = aw_a10_class_init, 189 }; 190 191 static void aw_a10_register_types(void) 192 { 193 type_register_static(&aw_a10_type_info); 194 } 195 196 type_init(aw_a10_register_types) 197