turbostat.c (5a63426e2a18775ed05b20e3bc90c68bacb1f68a) turbostat.c (e4085d543e256aff6606ba99ed257f7c06685f3b)
1/*
2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
4 *
5 * Copyright (c) 2013 Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it

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1293 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"};
1294
1295int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1296int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1297int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1298int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1299int amt_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1300int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1/*
2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
4 *
5 * Copyright (c) 2013 Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it

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1293 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"};
1294
1295int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1296int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1297int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1298int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1299int amt_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1300int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1301int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1301
1302
1303static void
1304calculate_tsc_tweak()
1305{
1306 tsc_tweak = base_hz / tsc_hz;
1307}
1308

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2194 pkg_cstate_limits = slv_pkg_cstate_limits;
2195 break;
2196 case 0x4C: /* AMT */
2197 pkg_cstate_limits = amt_pkg_cstate_limits;
2198 break;
2199 case 0x57: /* PHI */
2200 pkg_cstate_limits = phi_pkg_cstate_limits;
2201 break;
1302
1303
1304static void
1305calculate_tsc_tweak()
1306{
1307 tsc_tweak = base_hz / tsc_hz;
1308}
1309

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2195 pkg_cstate_limits = slv_pkg_cstate_limits;
2196 break;
2197 case 0x4C: /* AMT */
2198 pkg_cstate_limits = amt_pkg_cstate_limits;
2199 break;
2200 case 0x57: /* PHI */
2201 pkg_cstate_limits = phi_pkg_cstate_limits;
2202 break;
2203 case 0x5C: /* BXT */
2204 pkg_cstate_limits = bxt_pkg_cstate_limits;
2205 break;
2202 default:
2203 return 0;
2204 }
2205 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr);
2206 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
2207
2208 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
2209 base_ratio = (msr >> 8) & 0xFF;

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2623 case 0x3A:
2624 case 0x3C: /* HSW */
2625 case 0x45: /* HSW */
2626 case 0x46: /* HSW */
2627 case 0x3D: /* BDW */
2628 case 0x47: /* BDW */
2629 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
2630 break;
2206 default:
2207 return 0;
2208 }
2209 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr);
2210 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
2211
2212 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
2213 base_ratio = (msr >> 8) & 0xFF;

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2627 case 0x3A:
2628 case 0x3C: /* HSW */
2629 case 0x45: /* HSW */
2630 case 0x46: /* HSW */
2631 case 0x3D: /* BDW */
2632 case 0x47: /* BDW */
2633 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
2634 break;
2635 case 0x5C: /* BXT */
2636 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
2637 break;
2631 case 0x4E: /* SKL */
2632 case 0x5E: /* SKL */
2633 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
2634 break;
2635 case 0x3F: /* HSX */
2636 case 0x4F: /* BDX */
2637 case 0x56: /* BDX-DE */
2638 case 0x57: /* KNL */

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2909 case 0x45: /* HSW */
2910 case 0x46: /* HSW */
2911 case 0x3D: /* BDW */
2912 case 0x47: /* BDW */
2913 case 0x4F: /* BDX */
2914 case 0x56: /* BDX-DE */
2915 case 0x4E: /* SKL */
2916 case 0x5E: /* SKL */
2638 case 0x4E: /* SKL */
2639 case 0x5E: /* SKL */
2640 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
2641 break;
2642 case 0x3F: /* HSX */
2643 case 0x4F: /* BDX */
2644 case 0x56: /* BDX-DE */
2645 case 0x57: /* KNL */

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2916 case 0x45: /* HSW */
2917 case 0x46: /* HSW */
2918 case 0x3D: /* BDW */
2919 case 0x47: /* BDW */
2920 case 0x4F: /* BDX */
2921 case 0x56: /* BDX-DE */
2922 case 0x4E: /* SKL */
2923 case 0x5E: /* SKL */
2924 case 0x5C: /* BXT */
2917 return 1;
2918 }
2919 return 0;
2920}
2921
2922/*
2923 * HSW adds support for additional MSRs:
2924 *

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2936 if (!genuine_intel)
2937 return 0;
2938
2939 switch (model) {
2940 case 0x45: /* HSW */
2941 case 0x3D: /* BDW */
2942 case 0x4E: /* SKL */
2943 case 0x5E: /* SKL */
2925 return 1;
2926 }
2927 return 0;
2928}
2929
2930/*
2931 * HSW adds support for additional MSRs:
2932 *

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2944 if (!genuine_intel)
2945 return 0;
2946
2947 switch (model) {
2948 case 0x45: /* HSW */
2949 case 0x3D: /* BDW */
2950 case 0x4E: /* SKL */
2951 case 0x5E: /* SKL */
2952 case 0x5C: /* BXT */
2944 return 1;
2945 }
2946 return 0;
2947}
2948
2949/*
2950 * SKL adds support for additional MSRS:
2951 *

--- 852 unchanged lines hidden --- 		2953 return 1;
2954 }
2955 return 0;
2956}
2957
2958/*
2959 * SKL adds support for additional MSRS:
2960 *

--- 852 unchanged lines hidden ---