exynos850.h (45bbf4d76a6730acf63805798d6fe7a126e49dbc) exynos850.h (f20f35f46f1a65e1c4b65d8fb62acdbdafd11e1e)
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2/*
3 * Copyright (C) 2021 Linaro Ltd.
4 * Author: Sam Protsenko <semen.protsenko@linaro.org>
5 *
6 * Device Tree binding constants for Exynos850 clock controller.
7 */
8

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56#define CLK_GOUT_PERI_UART 44
57#define CLK_GOUT_PERI_IP 45
58#define CLK_MOUT_CLKCMU_APM_BUS 46
59#define CLK_DOUT_CLKCMU_APM_BUS 47
60#define CLK_GOUT_CLKCMU_APM_BUS 48
61#define CLK_MOUT_AUD 49
62#define CLK_GOUT_AUD 50
63#define CLK_DOUT_AUD 51
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2/*
3 * Copyright (C) 2021 Linaro Ltd.
4 * Author: Sam Protsenko <semen.protsenko@linaro.org>
5 *
6 * Device Tree binding constants for Exynos850 clock controller.
7 */
8

--- 47 unchanged lines hidden (view full) ---

56#define CLK_GOUT_PERI_UART 44
57#define CLK_GOUT_PERI_IP 45
58#define CLK_MOUT_CLKCMU_APM_BUS 46
59#define CLK_DOUT_CLKCMU_APM_BUS 47
60#define CLK_GOUT_CLKCMU_APM_BUS 48
61#define CLK_MOUT_AUD 49
62#define CLK_GOUT_AUD 50
63#define CLK_DOUT_AUD 51
64#define TOP_NR_CLK 52
64#define CLK_MOUT_IS_BUS 52
65#define CLK_MOUT_IS_ITP 53
66#define CLK_MOUT_IS_VRA 54
67#define CLK_MOUT_IS_GDC 55
68#define CLK_GOUT_IS_BUS 56
69#define CLK_GOUT_IS_ITP 57
70#define CLK_GOUT_IS_VRA 58
71#define CLK_GOUT_IS_GDC 59
72#define CLK_DOUT_IS_BUS 60
73#define CLK_DOUT_IS_ITP 61
74#define CLK_DOUT_IS_VRA 62
75#define CLK_DOUT_IS_GDC 63
76#define TOP_NR_CLK 64
65
66/* CMU_APM */
67#define CLK_RCO_I3C_PMIC 1
68#define OSCCLK_RCO_APM 2
69#define CLK_RCO_APM__ALV 3
70#define CLK_DLL_DCO 4
71#define CLK_MOUT_APM_BUS_USER 5
72#define CLK_MOUT_RCO_APM_I3C_USER 6

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182#define CLK_GOUT_USB_PHY_ACLK 8
183#define CLK_GOUT_USB_BUS_EARLY_CLK 9
184#define CLK_GOUT_GPIO_HSI_PCLK 10
185#define CLK_GOUT_MMC_CARD_ACLK 11
186#define CLK_GOUT_MMC_CARD_SDCLKIN 12
187#define CLK_GOUT_SYSREG_HSI_PCLK 13
188#define HSI_NR_CLK 14
189
77
78/* CMU_APM */
79#define CLK_RCO_I3C_PMIC 1
80#define OSCCLK_RCO_APM 2
81#define CLK_RCO_APM__ALV 3
82#define CLK_DLL_DCO 4
83#define CLK_MOUT_APM_BUS_USER 5
84#define CLK_MOUT_RCO_APM_I3C_USER 6

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194#define CLK_GOUT_USB_PHY_ACLK 8
195#define CLK_GOUT_USB_BUS_EARLY_CLK 9
196#define CLK_GOUT_GPIO_HSI_PCLK 10
197#define CLK_GOUT_MMC_CARD_ACLK 11
198#define CLK_GOUT_MMC_CARD_SDCLKIN 12
199#define CLK_GOUT_SYSREG_HSI_PCLK 13
200#define HSI_NR_CLK 14
201
202/* CMU_IS */
203#define CLK_MOUT_IS_BUS_USER 1
204#define CLK_MOUT_IS_ITP_USER 2
205#define CLK_MOUT_IS_VRA_USER 3
206#define CLK_MOUT_IS_GDC_USER 4
207#define CLK_DOUT_IS_BUSP 5
208#define CLK_GOUT_IS_CMU_IS_PCLK 6
209#define CLK_GOUT_IS_CSIS0_ACLK 7
210#define CLK_GOUT_IS_CSIS1_ACLK 8
211#define CLK_GOUT_IS_CSIS2_ACLK 9
212#define CLK_GOUT_IS_TZPC_PCLK 10
213#define CLK_GOUT_IS_CSIS_DMA_CLK 11
214#define CLK_GOUT_IS_GDC_CLK 12
215#define CLK_GOUT_IS_IPP_CLK 13
216#define CLK_GOUT_IS_ITP_CLK 14
217#define CLK_GOUT_IS_MCSC_CLK 15
218#define CLK_GOUT_IS_VRA_CLK 16
219#define CLK_GOUT_IS_PPMU_IS0_ACLK 17
220#define CLK_GOUT_IS_PPMU_IS0_PCLK 18
221#define CLK_GOUT_IS_PPMU_IS1_ACLK 19
222#define CLK_GOUT_IS_PPMU_IS1_PCLK 20
223#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21
224#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22
225#define CLK_GOUT_IS_SYSREG_PCLK 23
226#define IS_NR_CLK 24
227
190/* CMU_PERI */
191#define CLK_MOUT_PERI_BUS_USER 1
192#define CLK_MOUT_PERI_UART_USER 2
193#define CLK_MOUT_PERI_HSI2C_USER 3
194#define CLK_MOUT_PERI_SPI_USER 4
195#define CLK_DOUT_PERI_HSI2C0 5
196#define CLK_DOUT_PERI_HSI2C1 6
197#define CLK_DOUT_PERI_HSI2C2 7

--- 60 unchanged lines hidden --- 		228/* CMU_PERI */
229#define CLK_MOUT_PERI_BUS_USER 1
230#define CLK_MOUT_PERI_UART_USER 2
231#define CLK_MOUT_PERI_HSI2C_USER 3
232#define CLK_MOUT_PERI_SPI_USER 4
233#define CLK_DOUT_PERI_HSI2C0 5
234#define CLK_DOUT_PERI_HSI2C1 6
235#define CLK_DOUT_PERI_HSI2C2 7

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