stm32-usart.c (c0f3332cb5f2e370c041594fa1ff59db4ee68925) stm32-usart.c (3d530017bef1de7f7773eb9d3c65fbce924894a2)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *

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919 }
920
921 } else {
922 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
923 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
924 }
925
926 /* Configure wake up from low power on start bit detection */
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *

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919 }
920
921 } else {
922 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
923 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
924 }
925
926 /* Configure wake up from low power on start bit detection */
927 if (stm32_port->wakeirq > 0) {
927 if (stm32_port->wakeup_src) {
928 cr3 &= ~USART_CR3_WUS_MASK;
929 cr3 |= USART_CR3_WUS_START_BIT;
930 }
931
932 writel_relaxed(cr3, port->membase + ofs->cr3);
933 writel_relaxed(cr2, port->membase + ofs->cr2);
934 writel_relaxed(cr1, port->membase + ofs->cr1);
935

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1039 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
1040 port->irq = irq;
1041 port->rs485_config = stm32_usart_config_rs485;
1042
1043 ret = stm32_usart_init_rs485(port, pdev);
1044 if (ret)
1045 return ret;
1046
928 cr3 &= ~USART_CR3_WUS_MASK;
929 cr3 |= USART_CR3_WUS_START_BIT;
930 }
931
932 writel_relaxed(cr3, port->membase + ofs->cr3);
933 writel_relaxed(cr2, port->membase + ofs->cr2);
934 writel_relaxed(cr1, port->membase + ofs->cr1);
935

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1039 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
1040 port->irq = irq;
1041 port->rs485_config = stm32_usart_config_rs485;
1042
1043 ret = stm32_usart_init_rs485(port, pdev);
1044 if (ret)
1045 return ret;
1046
1047 if (stm32port->info->cfg.has_wakeup) {
1048 stm32port->wakeirq = platform_get_irq_optional(pdev, 1);
1049 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO)
1050 return stm32port->wakeirq ? : -ENODEV;
1051 }
1047 stm32port->wakeup_src = stm32port->info->cfg.has_wakeup &&
1048 of_property_read_bool(pdev->dev.of_node, "wakeup-source");
1052
1053 stm32port->fifoen = stm32port->info->cfg.has_fifo;
1054
1055 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1056 port->membase = devm_ioremap_resource(&pdev->dev, res);
1057 if (IS_ERR(port->membase))
1058 return PTR_ERR(port->membase);
1059 port->mapbase = res->start;

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1278 stm32port->info = of_device_get_match_data(&pdev->dev);
1279 if (!stm32port->info)
1280 return -EINVAL;
1281
1282 ret = stm32_usart_init_port(stm32port, pdev);
1283 if (ret)
1284 return ret;
1285
1049
1050 stm32port->fifoen = stm32port->info->cfg.has_fifo;
1051
1052 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1053 port->membase = devm_ioremap_resource(&pdev->dev, res);
1054 if (IS_ERR(port->membase))
1055 return PTR_ERR(port->membase);
1056 port->mapbase = res->start;

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1275 stm32port->info = of_device_get_match_data(&pdev->dev);
1276 if (!stm32port->info)
1277 return -EINVAL;
1278
1279 ret = stm32_usart_init_port(stm32port, pdev);
1280 if (ret)
1281 return ret;
1282
1286 if (stm32port->wakeirq > 0) {
1287 ret = device_init_wakeup(&pdev->dev, true);
1283 if (stm32port->wakeup_src) {
1284 device_set_wakeup_capable(&pdev->dev, true);
1285 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq);
1288 if (ret)
1286 if (ret)
1289 goto err_uninit;
1290
1291 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1292 stm32port->wakeirq);
1293 if (ret)
1294 goto err_nowup;
1287 goto err_nowup;
1295
1296 device_set_wakeup_enable(&pdev->dev, false);
1297 }
1298
1299 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev);
1300 if (ret)
1301 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1302
1303 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev);
1304 if (ret)

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1338 dma_release_channel(stm32port->tx_ch);
1339 }
1340
1341 if (stm32port->tx_dma_buf)
1342 dma_free_coherent(&pdev->dev,
1343 TX_BUF_L, stm32port->tx_buf,
1344 stm32port->tx_dma_buf);
1345
1288 }
1289
1290 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev);
1291 if (ret)
1292 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1293
1294 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev);
1295 if (ret)

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1329 dma_release_channel(stm32port->tx_ch);
1330 }
1331
1332 if (stm32port->tx_dma_buf)
1333 dma_free_coherent(&pdev->dev,
1334 TX_BUF_L, stm32port->tx_buf,
1335 stm32port->tx_dma_buf);
1336
1346 if (stm32port->wakeirq > 0)
1337 if (stm32port->wakeup_src)
1347 dev_pm_clear_wake_irq(&pdev->dev);
1348
1349err_nowup:
1338 dev_pm_clear_wake_irq(&pdev->dev);
1339
1340err_nowup:
1350 if (stm32port->wakeirq > 0)
1351 device_init_wakeup(&pdev->dev, false);
1341 if (stm32port->wakeup_src)
1342 device_set_wakeup_capable(&pdev->dev, false);
1352
1343
1353err_uninit:
1354 stm32_usart_deinit_port(stm32port);
1355
1356 return ret;
1357}
1358
1359static int stm32_usart_serial_remove(struct platform_device *pdev)
1360{
1361 struct uart_port *port = platform_get_drvdata(pdev);

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1391 dma_release_channel(stm32_port->tx_ch);
1392 }
1393
1394 if (stm32_port->tx_dma_buf)
1395 dma_free_coherent(&pdev->dev,
1396 TX_BUF_L, stm32_port->tx_buf,
1397 stm32_port->tx_dma_buf);
1398
1344 stm32_usart_deinit_port(stm32port);
1345
1346 return ret;
1347}
1348
1349static int stm32_usart_serial_remove(struct platform_device *pdev)
1350{
1351 struct uart_port *port = platform_get_drvdata(pdev);

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1381 dma_release_channel(stm32_port->tx_ch);
1382 }
1383
1384 if (stm32_port->tx_dma_buf)
1385 dma_free_coherent(&pdev->dev,
1386 TX_BUF_L, stm32_port->tx_buf,
1387 stm32_port->tx_dma_buf);
1388
1399 if (stm32_port->wakeirq > 0) {
1389 if (stm32_port->wakeup_src) {
1400 dev_pm_clear_wake_irq(&pdev->dev);
1401 device_init_wakeup(&pdev->dev, false);
1402 }
1403
1404 stm32_usart_deinit_port(stm32_port);
1405
1406 return 0;
1407}

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1507};
1508
1509static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
1510 bool enable)
1511{
1512 struct stm32_port *stm32_port = to_stm32_port(port);
1513 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1514
1390 dev_pm_clear_wake_irq(&pdev->dev);
1391 device_init_wakeup(&pdev->dev, false);
1392 }
1393
1394 stm32_usart_deinit_port(stm32_port);
1395
1396 return 0;
1397}

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1497};
1498
1499static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
1500 bool enable)
1501{
1502 struct stm32_port *stm32_port = to_stm32_port(port);
1503 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1504
1515 if (stm32_port->wakeirq <= 0)
1505 if (!stm32_port->wakeup_src)
1516 return;
1517
1518 /*
1519 * Enable low-power wake-up and wake-up irq if argument is set to
1520 * "enable", disable low-power wake-up and wake-up irq otherwise
1521 */
1522 if (enable) {
1523 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);

--- 111 unchanged lines hidden --- 		1506 return;
1507
1508 /*
1509 * Enable low-power wake-up and wake-up irq if argument is set to
1510 * "enable", disable low-power wake-up and wake-up irq otherwise
1511 */
1512 if (enable) {
1513 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);

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