1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@foss.st.com> 7 * Erwan Le Ray <erwan.leray@foss.st.com> 8 * 9 * Inspired by st-asc.c from STMicroelectronics (c) 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/delay.h> 15 #include <linux/dma-direction.h> 16 #include <linux/dmaengine.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/irq.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_platform.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/spinlock.h> 31 #include <linux/sysrq.h> 32 #include <linux/tty_flip.h> 33 #include <linux/tty.h> 34 35 #include "serial_mctrl_gpio.h" 36 #include "stm32-usart.h" 37 38 static void stm32_usart_stop_tx(struct uart_port *port); 39 static void stm32_usart_transmit_chars(struct uart_port *port); 40 41 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 42 { 43 return container_of(port, struct stm32_port, port); 44 } 45 46 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits) 47 { 48 u32 val; 49 50 val = readl_relaxed(port->membase + reg); 51 val |= bits; 52 writel_relaxed(val, port->membase + reg); 53 } 54 55 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits) 56 { 57 u32 val; 58 59 val = readl_relaxed(port->membase + reg); 60 val &= ~bits; 61 writel_relaxed(val, port->membase + reg); 62 } 63 64 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 65 u32 delay_DDE, u32 baud) 66 { 67 u32 rs485_deat_dedt; 68 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 69 bool over8; 70 71 *cr3 |= USART_CR3_DEM; 72 over8 = *cr1 & USART_CR1_OVER8; 73 74 if (over8) 75 rs485_deat_dedt = delay_ADE * baud * 8; 76 else 77 rs485_deat_dedt = delay_ADE * baud * 16; 78 79 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 80 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 81 rs485_deat_dedt_max : rs485_deat_dedt; 82 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 83 USART_CR1_DEAT_MASK; 84 *cr1 |= rs485_deat_dedt; 85 86 if (over8) 87 rs485_deat_dedt = delay_DDE * baud * 8; 88 else 89 rs485_deat_dedt = delay_DDE * baud * 16; 90 91 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 92 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 93 rs485_deat_dedt_max : rs485_deat_dedt; 94 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 95 USART_CR1_DEDT_MASK; 96 *cr1 |= rs485_deat_dedt; 97 } 98 99 static int stm32_usart_config_rs485(struct uart_port *port, 100 struct serial_rs485 *rs485conf) 101 { 102 struct stm32_port *stm32_port = to_stm32_port(port); 103 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 104 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 105 u32 usartdiv, baud, cr1, cr3; 106 bool over8; 107 108 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 109 110 port->rs485 = *rs485conf; 111 112 rs485conf->flags |= SER_RS485_RX_DURING_TX; 113 114 if (rs485conf->flags & SER_RS485_ENABLED) { 115 cr1 = readl_relaxed(port->membase + ofs->cr1); 116 cr3 = readl_relaxed(port->membase + ofs->cr3); 117 usartdiv = readl_relaxed(port->membase + ofs->brr); 118 usartdiv = usartdiv & GENMASK(15, 0); 119 over8 = cr1 & USART_CR1_OVER8; 120 121 if (over8) 122 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 123 << USART_BRR_04_R_SHIFT; 124 125 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 126 stm32_usart_config_reg_rs485(&cr1, &cr3, 127 rs485conf->delay_rts_before_send, 128 rs485conf->delay_rts_after_send, 129 baud); 130 131 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 132 cr3 &= ~USART_CR3_DEP; 133 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 134 } else { 135 cr3 |= USART_CR3_DEP; 136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 137 } 138 139 writel_relaxed(cr3, port->membase + ofs->cr3); 140 writel_relaxed(cr1, port->membase + ofs->cr1); 141 } else { 142 stm32_usart_clr_bits(port, ofs->cr3, 143 USART_CR3_DEM | USART_CR3_DEP); 144 stm32_usart_clr_bits(port, ofs->cr1, 145 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 146 } 147 148 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 149 150 return 0; 151 } 152 153 static int stm32_usart_init_rs485(struct uart_port *port, 154 struct platform_device *pdev) 155 { 156 struct serial_rs485 *rs485conf = &port->rs485; 157 158 rs485conf->flags = 0; 159 rs485conf->delay_rts_before_send = 0; 160 rs485conf->delay_rts_after_send = 0; 161 162 if (!pdev->dev.of_node) 163 return -ENODEV; 164 165 return uart_get_rs485_mode(port); 166 } 167 168 static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr, 169 int *last_res, bool threaded) 170 { 171 struct stm32_port *stm32_port = to_stm32_port(port); 172 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 173 enum dma_status status; 174 struct dma_tx_state state; 175 176 *sr = readl_relaxed(port->membase + ofs->isr); 177 178 if (threaded && stm32_port->rx_ch) { 179 status = dmaengine_tx_status(stm32_port->rx_ch, 180 stm32_port->rx_ch->cookie, 181 &state); 182 if (status == DMA_IN_PROGRESS && (*last_res != state.residue)) 183 return 1; 184 else 185 return 0; 186 } else if (*sr & USART_SR_RXNE) { 187 return 1; 188 } 189 return 0; 190 } 191 192 static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr, 193 int *last_res) 194 { 195 struct stm32_port *stm32_port = to_stm32_port(port); 196 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 197 unsigned long c; 198 199 if (stm32_port->rx_ch) { 200 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 201 if ((*last_res) == 0) 202 *last_res = RX_BUF_L; 203 } else { 204 c = readl_relaxed(port->membase + ofs->rdr); 205 /* apply RDR data mask */ 206 c &= stm32_port->rdr_mask; 207 } 208 209 return c; 210 } 211 212 static void stm32_usart_receive_chars(struct uart_port *port, bool threaded) 213 { 214 struct tty_port *tport = &port->state->port; 215 struct stm32_port *stm32_port = to_stm32_port(port); 216 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 217 unsigned long c, flags; 218 u32 sr; 219 char flag; 220 221 if (threaded) 222 spin_lock_irqsave(&port->lock, flags); 223 else 224 spin_lock(&port->lock); 225 226 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res, 227 threaded)) { 228 sr |= USART_SR_DUMMY_RX; 229 flag = TTY_NORMAL; 230 231 /* 232 * Status bits has to be cleared before reading the RDR: 233 * In FIFO mode, reading the RDR will pop the next data 234 * (if any) along with its status bits into the SR. 235 * Not doing so leads to misalignement between RDR and SR, 236 * and clear status bits of the next rx data. 237 * 238 * Clear errors flags for stm32f7 and stm32h7 compatible 239 * devices. On stm32f4 compatible devices, the error bit is 240 * cleared by the sequence [read SR - read DR]. 241 */ 242 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 243 writel_relaxed(sr & USART_SR_ERR_MASK, 244 port->membase + ofs->icr); 245 246 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res); 247 port->icount.rx++; 248 if (sr & USART_SR_ERR_MASK) { 249 if (sr & USART_SR_ORE) { 250 port->icount.overrun++; 251 } else if (sr & USART_SR_PE) { 252 port->icount.parity++; 253 } else if (sr & USART_SR_FE) { 254 /* Break detection if character is null */ 255 if (!c) { 256 port->icount.brk++; 257 if (uart_handle_break(port)) 258 continue; 259 } else { 260 port->icount.frame++; 261 } 262 } 263 264 sr &= port->read_status_mask; 265 266 if (sr & USART_SR_PE) { 267 flag = TTY_PARITY; 268 } else if (sr & USART_SR_FE) { 269 if (!c) 270 flag = TTY_BREAK; 271 else 272 flag = TTY_FRAME; 273 } 274 } 275 276 if (uart_handle_sysrq_char(port, c)) 277 continue; 278 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 279 } 280 281 if (threaded) 282 spin_unlock_irqrestore(&port->lock, flags); 283 else 284 spin_unlock(&port->lock); 285 286 tty_flip_buffer_push(tport); 287 } 288 289 static void stm32_usart_tx_dma_complete(void *arg) 290 { 291 struct uart_port *port = arg; 292 struct stm32_port *stm32port = to_stm32_port(port); 293 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 294 unsigned long flags; 295 296 dmaengine_terminate_async(stm32port->tx_ch); 297 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 298 stm32port->tx_dma_busy = false; 299 300 /* Let's see if we have pending data to send */ 301 spin_lock_irqsave(&port->lock, flags); 302 stm32_usart_transmit_chars(port); 303 spin_unlock_irqrestore(&port->lock, flags); 304 } 305 306 static void stm32_usart_tx_interrupt_enable(struct uart_port *port) 307 { 308 struct stm32_port *stm32_port = to_stm32_port(port); 309 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 310 311 /* 312 * Enables TX FIFO threashold irq when FIFO is enabled, 313 * or TX empty irq when FIFO is disabled 314 */ 315 if (stm32_port->fifoen) 316 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 317 else 318 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 319 } 320 321 static void stm32_usart_tx_interrupt_disable(struct uart_port *port) 322 { 323 struct stm32_port *stm32_port = to_stm32_port(port); 324 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 325 326 if (stm32_port->fifoen) 327 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 328 else 329 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 330 } 331 332 static void stm32_usart_transmit_chars_pio(struct uart_port *port) 333 { 334 struct stm32_port *stm32_port = to_stm32_port(port); 335 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 336 struct circ_buf *xmit = &port->state->xmit; 337 338 if (stm32_port->tx_dma_busy) { 339 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 340 stm32_port->tx_dma_busy = false; 341 } 342 343 while (!uart_circ_empty(xmit)) { 344 /* Check that TDR is empty before filling FIFO */ 345 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 346 break; 347 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 348 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 349 port->icount.tx++; 350 } 351 352 /* rely on TXE irq (mask or unmask) for sending remaining data */ 353 if (uart_circ_empty(xmit)) 354 stm32_usart_tx_interrupt_disable(port); 355 else 356 stm32_usart_tx_interrupt_enable(port); 357 } 358 359 static void stm32_usart_transmit_chars_dma(struct uart_port *port) 360 { 361 struct stm32_port *stm32port = to_stm32_port(port); 362 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 363 struct circ_buf *xmit = &port->state->xmit; 364 struct dma_async_tx_descriptor *desc = NULL; 365 unsigned int count, i; 366 367 if (stm32port->tx_dma_busy) 368 return; 369 370 stm32port->tx_dma_busy = true; 371 372 count = uart_circ_chars_pending(xmit); 373 374 if (count > TX_BUF_L) 375 count = TX_BUF_L; 376 377 if (xmit->tail < xmit->head) { 378 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 379 } else { 380 size_t one = UART_XMIT_SIZE - xmit->tail; 381 size_t two; 382 383 if (one > count) 384 one = count; 385 two = count - one; 386 387 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 388 if (two) 389 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 390 } 391 392 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 393 stm32port->tx_dma_buf, 394 count, 395 DMA_MEM_TO_DEV, 396 DMA_PREP_INTERRUPT); 397 398 if (!desc) 399 goto fallback_err; 400 401 desc->callback = stm32_usart_tx_dma_complete; 402 desc->callback_param = port; 403 404 /* Push current DMA TX transaction in the pending queue */ 405 if (dma_submit_error(dmaengine_submit(desc))) { 406 /* dma no yet started, safe to free resources */ 407 dmaengine_terminate_async(stm32port->tx_ch); 408 goto fallback_err; 409 } 410 411 /* Issue pending DMA TX requests */ 412 dma_async_issue_pending(stm32port->tx_ch); 413 414 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 415 416 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 417 port->icount.tx += count; 418 return; 419 420 fallback_err: 421 for (i = count; i > 0; i--) 422 stm32_usart_transmit_chars_pio(port); 423 } 424 425 static void stm32_usart_transmit_chars(struct uart_port *port) 426 { 427 struct stm32_port *stm32_port = to_stm32_port(port); 428 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 429 struct circ_buf *xmit = &port->state->xmit; 430 431 if (port->x_char) { 432 if (stm32_port->tx_dma_busy) 433 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 434 writel_relaxed(port->x_char, port->membase + ofs->tdr); 435 port->x_char = 0; 436 port->icount.tx++; 437 if (stm32_port->tx_dma_busy) 438 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 439 return; 440 } 441 442 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 443 stm32_usart_tx_interrupt_disable(port); 444 return; 445 } 446 447 if (ofs->icr == UNDEF_REG) 448 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); 449 else 450 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 451 452 if (stm32_port->tx_ch) 453 stm32_usart_transmit_chars_dma(port); 454 else 455 stm32_usart_transmit_chars_pio(port); 456 457 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 458 uart_write_wakeup(port); 459 460 if (uart_circ_empty(xmit)) 461 stm32_usart_tx_interrupt_disable(port); 462 } 463 464 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) 465 { 466 struct uart_port *port = ptr; 467 struct tty_port *tport = &port->state->port; 468 struct stm32_port *stm32_port = to_stm32_port(port); 469 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 470 u32 sr; 471 472 sr = readl_relaxed(port->membase + ofs->isr); 473 474 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 475 writel_relaxed(USART_ICR_RTOCF, 476 port->membase + ofs->icr); 477 478 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { 479 /* Clear wake up flag and disable wake up interrupt */ 480 writel_relaxed(USART_ICR_WUCF, 481 port->membase + ofs->icr); 482 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 483 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 484 pm_wakeup_event(tport->tty->dev, 0); 485 } 486 487 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 488 stm32_usart_receive_chars(port, false); 489 490 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { 491 spin_lock(&port->lock); 492 stm32_usart_transmit_chars(port); 493 spin_unlock(&port->lock); 494 } 495 496 if (stm32_port->rx_ch) 497 return IRQ_WAKE_THREAD; 498 else 499 return IRQ_HANDLED; 500 } 501 502 static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr) 503 { 504 struct uart_port *port = ptr; 505 struct stm32_port *stm32_port = to_stm32_port(port); 506 507 if (stm32_port->rx_ch) 508 stm32_usart_receive_chars(port, true); 509 510 return IRQ_HANDLED; 511 } 512 513 static unsigned int stm32_usart_tx_empty(struct uart_port *port) 514 { 515 struct stm32_port *stm32_port = to_stm32_port(port); 516 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 517 518 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC) 519 return TIOCSER_TEMT; 520 521 return 0; 522 } 523 524 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl) 525 { 526 struct stm32_port *stm32_port = to_stm32_port(port); 527 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 528 529 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 530 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); 531 else 532 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 533 534 mctrl_gpio_set(stm32_port->gpios, mctrl); 535 } 536 537 static unsigned int stm32_usart_get_mctrl(struct uart_port *port) 538 { 539 struct stm32_port *stm32_port = to_stm32_port(port); 540 unsigned int ret; 541 542 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 543 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 544 545 return mctrl_gpio_get(stm32_port->gpios, &ret); 546 } 547 548 static void stm32_usart_enable_ms(struct uart_port *port) 549 { 550 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 551 } 552 553 static void stm32_usart_disable_ms(struct uart_port *port) 554 { 555 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 556 } 557 558 /* Transmit stop */ 559 static void stm32_usart_stop_tx(struct uart_port *port) 560 { 561 struct stm32_port *stm32_port = to_stm32_port(port); 562 struct serial_rs485 *rs485conf = &port->rs485; 563 564 stm32_usart_tx_interrupt_disable(port); 565 566 if (rs485conf->flags & SER_RS485_ENABLED) { 567 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 568 mctrl_gpio_set(stm32_port->gpios, 569 stm32_port->port.mctrl & ~TIOCM_RTS); 570 } else { 571 mctrl_gpio_set(stm32_port->gpios, 572 stm32_port->port.mctrl | TIOCM_RTS); 573 } 574 } 575 } 576 577 /* There are probably characters waiting to be transmitted. */ 578 static void stm32_usart_start_tx(struct uart_port *port) 579 { 580 struct stm32_port *stm32_port = to_stm32_port(port); 581 struct serial_rs485 *rs485conf = &port->rs485; 582 struct circ_buf *xmit = &port->state->xmit; 583 584 if (uart_circ_empty(xmit)) 585 return; 586 587 if (rs485conf->flags & SER_RS485_ENABLED) { 588 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 589 mctrl_gpio_set(stm32_port->gpios, 590 stm32_port->port.mctrl | TIOCM_RTS); 591 } else { 592 mctrl_gpio_set(stm32_port->gpios, 593 stm32_port->port.mctrl & ~TIOCM_RTS); 594 } 595 } 596 597 stm32_usart_transmit_chars(port); 598 } 599 600 /* Flush the transmit buffer. */ 601 static void stm32_usart_flush_buffer(struct uart_port *port) 602 { 603 struct stm32_port *stm32_port = to_stm32_port(port); 604 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 605 606 if (stm32_port->tx_ch) { 607 dmaengine_terminate_async(stm32_port->tx_ch); 608 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 609 stm32_port->tx_dma_busy = false; 610 } 611 } 612 613 /* Throttle the remote when input buffer is about to overflow. */ 614 static void stm32_usart_throttle(struct uart_port *port) 615 { 616 struct stm32_port *stm32_port = to_stm32_port(port); 617 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 618 unsigned long flags; 619 620 spin_lock_irqsave(&port->lock, flags); 621 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 622 if (stm32_port->cr3_irq) 623 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 624 625 spin_unlock_irqrestore(&port->lock, flags); 626 } 627 628 /* Unthrottle the remote, the input buffer can now accept data. */ 629 static void stm32_usart_unthrottle(struct uart_port *port) 630 { 631 struct stm32_port *stm32_port = to_stm32_port(port); 632 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 633 unsigned long flags; 634 635 spin_lock_irqsave(&port->lock, flags); 636 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 637 if (stm32_port->cr3_irq) 638 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 639 640 spin_unlock_irqrestore(&port->lock, flags); 641 } 642 643 /* Receive stop */ 644 static void stm32_usart_stop_rx(struct uart_port *port) 645 { 646 struct stm32_port *stm32_port = to_stm32_port(port); 647 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 648 649 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 650 if (stm32_port->cr3_irq) 651 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 652 } 653 654 /* Handle breaks - ignored by us */ 655 static void stm32_usart_break_ctl(struct uart_port *port, int break_state) 656 { 657 } 658 659 static int stm32_usart_startup(struct uart_port *port) 660 { 661 struct stm32_port *stm32_port = to_stm32_port(port); 662 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 663 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 664 const char *name = to_platform_device(port->dev)->name; 665 u32 val; 666 int ret; 667 668 ret = request_threaded_irq(port->irq, stm32_usart_interrupt, 669 stm32_usart_threaded_interrupt, 670 IRQF_NO_SUSPEND, name, port); 671 if (ret) 672 return ret; 673 674 /* RX FIFO Flush */ 675 if (ofs->rqr != UNDEF_REG) 676 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); 677 678 /* RX enabling */ 679 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); 680 stm32_usart_set_bits(port, ofs->cr1, val); 681 682 return 0; 683 } 684 685 static void stm32_usart_shutdown(struct uart_port *port) 686 { 687 struct stm32_port *stm32_port = to_stm32_port(port); 688 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 689 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 690 u32 val, isr; 691 int ret; 692 693 /* Disable modem control interrupts */ 694 stm32_usart_disable_ms(port); 695 696 val = USART_CR1_TXEIE | USART_CR1_TE; 697 val |= stm32_port->cr1_irq | USART_CR1_RE; 698 val |= BIT(cfg->uart_enable_bit); 699 if (stm32_port->fifoen) 700 val |= USART_CR1_FIFOEN; 701 702 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 703 isr, (isr & USART_SR_TC), 704 10, 100000); 705 706 /* Send the TC error message only when ISR_TC is not set */ 707 if (ret) 708 dev_err(port->dev, "Transmission is not complete\n"); 709 710 /* flush RX & TX FIFO */ 711 if (ofs->rqr != UNDEF_REG) 712 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 713 port->membase + ofs->rqr); 714 715 stm32_usart_clr_bits(port, ofs->cr1, val); 716 717 free_irq(port->irq, port); 718 } 719 720 static unsigned int stm32_usart_get_databits(struct ktermios *termios) 721 { 722 unsigned int bits; 723 724 tcflag_t cflag = termios->c_cflag; 725 726 switch (cflag & CSIZE) { 727 /* 728 * CSIZE settings are not necessarily supported in hardware. 729 * CSIZE unsupported configurations are handled here to set word length 730 * to 8 bits word as default configuration and to print debug message. 731 */ 732 case CS5: 733 bits = 5; 734 break; 735 case CS6: 736 bits = 6; 737 break; 738 case CS7: 739 bits = 7; 740 break; 741 /* default including CS8 */ 742 default: 743 bits = 8; 744 break; 745 } 746 747 return bits; 748 } 749 750 static void stm32_usart_set_termios(struct uart_port *port, 751 struct ktermios *termios, 752 struct ktermios *old) 753 { 754 struct stm32_port *stm32_port = to_stm32_port(port); 755 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 756 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 757 struct serial_rs485 *rs485conf = &port->rs485; 758 unsigned int baud, bits; 759 u32 usartdiv, mantissa, fraction, oversampling; 760 tcflag_t cflag = termios->c_cflag; 761 u32 cr1, cr2, cr3, isr; 762 unsigned long flags; 763 int ret; 764 765 if (!stm32_port->hw_flow_control) 766 cflag &= ~CRTSCTS; 767 768 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 769 770 spin_lock_irqsave(&port->lock, flags); 771 772 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 773 isr, 774 (isr & USART_SR_TC), 775 10, 100000); 776 777 /* Send the TC error message only when ISR_TC is not set. */ 778 if (ret) 779 dev_err(port->dev, "Transmission is not complete\n"); 780 781 /* Stop serial port and reset value */ 782 writel_relaxed(0, port->membase + ofs->cr1); 783 784 /* flush RX & TX FIFO */ 785 if (ofs->rqr != UNDEF_REG) 786 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 787 port->membase + ofs->rqr); 788 789 cr1 = USART_CR1_TE | USART_CR1_RE; 790 if (stm32_port->fifoen) 791 cr1 |= USART_CR1_FIFOEN; 792 cr2 = 0; 793 794 /* Tx and RX FIFO configuration */ 795 cr3 = readl_relaxed(port->membase + ofs->cr3); 796 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE; 797 if (stm32_port->fifoen) { 798 cr3 &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); 799 cr3 |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT; 800 cr3 |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT; 801 } 802 803 if (cflag & CSTOPB) 804 cr2 |= USART_CR2_STOP_2B; 805 806 bits = stm32_usart_get_databits(termios); 807 stm32_port->rdr_mask = (BIT(bits) - 1); 808 809 if (cflag & PARENB) { 810 bits++; 811 cr1 |= USART_CR1_PCE; 812 } 813 814 /* 815 * Word length configuration: 816 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 817 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 818 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 819 * M0 and M1 already cleared by cr1 initialization. 820 */ 821 if (bits == 9) 822 cr1 |= USART_CR1_M0; 823 else if ((bits == 7) && cfg->has_7bits_data) 824 cr1 |= USART_CR1_M1; 825 else if (bits != 8) 826 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 827 , bits); 828 829 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 830 stm32_port->fifoen)) { 831 if (cflag & CSTOPB) 832 bits = bits + 3; /* 1 start bit + 2 stop bits */ 833 else 834 bits = bits + 2; /* 1 start bit + 1 stop bit */ 835 836 /* RX timeout irq to occur after last stop bit + bits */ 837 stm32_port->cr1_irq = USART_CR1_RTOIE; 838 writel_relaxed(bits, port->membase + ofs->rtor); 839 cr2 |= USART_CR2_RTOEN; 840 /* Not using dma, enable fifo threshold irq */ 841 if (!stm32_port->rx_ch) 842 stm32_port->cr3_irq = USART_CR3_RXFTIE; 843 } 844 845 cr1 |= stm32_port->cr1_irq; 846 cr3 |= stm32_port->cr3_irq; 847 848 if (cflag & PARODD) 849 cr1 |= USART_CR1_PS; 850 851 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 852 if (cflag & CRTSCTS) { 853 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 854 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 855 } 856 857 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 858 859 /* 860 * The USART supports 16 or 8 times oversampling. 861 * By default we prefer 16 times oversampling, so that the receiver 862 * has a better tolerance to clock deviations. 863 * 8 times oversampling is only used to achieve higher speeds. 864 */ 865 if (usartdiv < 16) { 866 oversampling = 8; 867 cr1 |= USART_CR1_OVER8; 868 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); 869 } else { 870 oversampling = 16; 871 cr1 &= ~USART_CR1_OVER8; 872 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 873 } 874 875 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 876 fraction = usartdiv % oversampling; 877 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 878 879 uart_update_timeout(port, cflag, baud); 880 881 port->read_status_mask = USART_SR_ORE; 882 if (termios->c_iflag & INPCK) 883 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 884 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 885 port->read_status_mask |= USART_SR_FE; 886 887 /* Characters to ignore */ 888 port->ignore_status_mask = 0; 889 if (termios->c_iflag & IGNPAR) 890 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 891 if (termios->c_iflag & IGNBRK) { 892 port->ignore_status_mask |= USART_SR_FE; 893 /* 894 * If we're ignoring parity and break indicators, 895 * ignore overruns too (for real raw support). 896 */ 897 if (termios->c_iflag & IGNPAR) 898 port->ignore_status_mask |= USART_SR_ORE; 899 } 900 901 /* Ignore all characters if CREAD is not set */ 902 if ((termios->c_cflag & CREAD) == 0) 903 port->ignore_status_mask |= USART_SR_DUMMY_RX; 904 905 if (stm32_port->rx_ch) 906 cr3 |= USART_CR3_DMAR; 907 908 if (rs485conf->flags & SER_RS485_ENABLED) { 909 stm32_usart_config_reg_rs485(&cr1, &cr3, 910 rs485conf->delay_rts_before_send, 911 rs485conf->delay_rts_after_send, 912 baud); 913 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 914 cr3 &= ~USART_CR3_DEP; 915 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 916 } else { 917 cr3 |= USART_CR3_DEP; 918 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 919 } 920 921 } else { 922 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 923 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 924 } 925 926 /* Configure wake up from low power on start bit detection */ 927 if (stm32_port->wakeup_src) { 928 cr3 &= ~USART_CR3_WUS_MASK; 929 cr3 |= USART_CR3_WUS_START_BIT; 930 } 931 932 writel_relaxed(cr3, port->membase + ofs->cr3); 933 writel_relaxed(cr2, port->membase + ofs->cr2); 934 writel_relaxed(cr1, port->membase + ofs->cr1); 935 936 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 937 spin_unlock_irqrestore(&port->lock, flags); 938 939 /* Handle modem control interrupts */ 940 if (UART_ENABLE_MS(port, termios->c_cflag)) 941 stm32_usart_enable_ms(port); 942 else 943 stm32_usart_disable_ms(port); 944 } 945 946 static const char *stm32_usart_type(struct uart_port *port) 947 { 948 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 949 } 950 951 static void stm32_usart_release_port(struct uart_port *port) 952 { 953 } 954 955 static int stm32_usart_request_port(struct uart_port *port) 956 { 957 return 0; 958 } 959 960 static void stm32_usart_config_port(struct uart_port *port, int flags) 961 { 962 if (flags & UART_CONFIG_TYPE) 963 port->type = PORT_STM32; 964 } 965 966 static int 967 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser) 968 { 969 /* No user changeable parameters */ 970 return -EINVAL; 971 } 972 973 static void stm32_usart_pm(struct uart_port *port, unsigned int state, 974 unsigned int oldstate) 975 { 976 struct stm32_port *stm32port = container_of(port, 977 struct stm32_port, port); 978 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 979 const struct stm32_usart_config *cfg = &stm32port->info->cfg; 980 unsigned long flags = 0; 981 982 switch (state) { 983 case UART_PM_STATE_ON: 984 pm_runtime_get_sync(port->dev); 985 break; 986 case UART_PM_STATE_OFF: 987 spin_lock_irqsave(&port->lock, flags); 988 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 989 spin_unlock_irqrestore(&port->lock, flags); 990 pm_runtime_put_sync(port->dev); 991 break; 992 } 993 } 994 995 static const struct uart_ops stm32_uart_ops = { 996 .tx_empty = stm32_usart_tx_empty, 997 .set_mctrl = stm32_usart_set_mctrl, 998 .get_mctrl = stm32_usart_get_mctrl, 999 .stop_tx = stm32_usart_stop_tx, 1000 .start_tx = stm32_usart_start_tx, 1001 .throttle = stm32_usart_throttle, 1002 .unthrottle = stm32_usart_unthrottle, 1003 .stop_rx = stm32_usart_stop_rx, 1004 .enable_ms = stm32_usart_enable_ms, 1005 .break_ctl = stm32_usart_break_ctl, 1006 .startup = stm32_usart_startup, 1007 .shutdown = stm32_usart_shutdown, 1008 .flush_buffer = stm32_usart_flush_buffer, 1009 .set_termios = stm32_usart_set_termios, 1010 .pm = stm32_usart_pm, 1011 .type = stm32_usart_type, 1012 .release_port = stm32_usart_release_port, 1013 .request_port = stm32_usart_request_port, 1014 .config_port = stm32_usart_config_port, 1015 .verify_port = stm32_usart_verify_port, 1016 }; 1017 1018 static void stm32_usart_deinit_port(struct stm32_port *stm32port) 1019 { 1020 clk_disable_unprepare(stm32port->clk); 1021 } 1022 1023 static int stm32_usart_init_port(struct stm32_port *stm32port, 1024 struct platform_device *pdev) 1025 { 1026 struct uart_port *port = &stm32port->port; 1027 struct resource *res; 1028 int ret, irq; 1029 1030 irq = platform_get_irq(pdev, 0); 1031 if (irq <= 0) 1032 return irq ? : -ENODEV; 1033 1034 port->iotype = UPIO_MEM; 1035 port->flags = UPF_BOOT_AUTOCONF; 1036 port->ops = &stm32_uart_ops; 1037 port->dev = &pdev->dev; 1038 port->fifosize = stm32port->info->cfg.fifosize; 1039 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 1040 port->irq = irq; 1041 port->rs485_config = stm32_usart_config_rs485; 1042 1043 ret = stm32_usart_init_rs485(port, pdev); 1044 if (ret) 1045 return ret; 1046 1047 stm32port->wakeup_src = stm32port->info->cfg.has_wakeup && 1048 of_property_read_bool(pdev->dev.of_node, "wakeup-source"); 1049 1050 stm32port->fifoen = stm32port->info->cfg.has_fifo; 1051 1052 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1053 port->membase = devm_ioremap_resource(&pdev->dev, res); 1054 if (IS_ERR(port->membase)) 1055 return PTR_ERR(port->membase); 1056 port->mapbase = res->start; 1057 1058 spin_lock_init(&port->lock); 1059 1060 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 1061 if (IS_ERR(stm32port->clk)) 1062 return PTR_ERR(stm32port->clk); 1063 1064 /* Ensure that clk rate is correct by enabling the clk */ 1065 ret = clk_prepare_enable(stm32port->clk); 1066 if (ret) 1067 return ret; 1068 1069 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 1070 if (!stm32port->port.uartclk) { 1071 ret = -EINVAL; 1072 goto err_clk; 1073 } 1074 1075 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 1076 if (IS_ERR(stm32port->gpios)) { 1077 ret = PTR_ERR(stm32port->gpios); 1078 goto err_clk; 1079 } 1080 1081 /* 1082 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" 1083 * properties should not be specified. 1084 */ 1085 if (stm32port->hw_flow_control) { 1086 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 1087 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 1088 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 1089 ret = -EINVAL; 1090 goto err_clk; 1091 } 1092 } 1093 1094 return ret; 1095 1096 err_clk: 1097 clk_disable_unprepare(stm32port->clk); 1098 1099 return ret; 1100 } 1101 1102 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev) 1103 { 1104 struct device_node *np = pdev->dev.of_node; 1105 int id; 1106 1107 if (!np) 1108 return NULL; 1109 1110 id = of_alias_get_id(np, "serial"); 1111 if (id < 0) { 1112 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1113 return NULL; 1114 } 1115 1116 if (WARN_ON(id >= STM32_MAX_PORTS)) 1117 return NULL; 1118 1119 stm32_ports[id].hw_flow_control = 1120 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || 1121 of_property_read_bool (np, "uart-has-rtscts"); 1122 stm32_ports[id].port.line = id; 1123 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1124 stm32_ports[id].cr3_irq = 0; 1125 stm32_ports[id].last_res = RX_BUF_L; 1126 return &stm32_ports[id]; 1127 } 1128 1129 #ifdef CONFIG_OF 1130 static const struct of_device_id stm32_match[] = { 1131 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1132 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1133 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1134 {}, 1135 }; 1136 1137 MODULE_DEVICE_TABLE(of, stm32_match); 1138 #endif 1139 1140 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port, 1141 struct platform_device *pdev) 1142 { 1143 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1144 struct uart_port *port = &stm32port->port; 1145 struct device *dev = &pdev->dev; 1146 struct dma_slave_config config; 1147 struct dma_async_tx_descriptor *desc = NULL; 1148 int ret; 1149 1150 /* Request DMA RX channel */ 1151 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 1152 if (!stm32port->rx_ch) { 1153 dev_info(dev, "rx dma alloc failed\n"); 1154 return -ENODEV; 1155 } 1156 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 1157 &stm32port->rx_dma_buf, 1158 GFP_KERNEL); 1159 if (!stm32port->rx_buf) { 1160 ret = -ENOMEM; 1161 goto alloc_err; 1162 } 1163 1164 /* Configure DMA channel */ 1165 memset(&config, 0, sizeof(config)); 1166 config.src_addr = port->mapbase + ofs->rdr; 1167 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1168 1169 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1170 if (ret < 0) { 1171 dev_err(dev, "rx dma channel config failed\n"); 1172 ret = -ENODEV; 1173 goto config_err; 1174 } 1175 1176 /* Prepare a DMA cyclic transaction */ 1177 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 1178 stm32port->rx_dma_buf, 1179 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 1180 DMA_PREP_INTERRUPT); 1181 if (!desc) { 1182 dev_err(dev, "rx dma prep cyclic failed\n"); 1183 ret = -ENODEV; 1184 goto config_err; 1185 } 1186 1187 /* No callback as dma buffer is drained on usart interrupt */ 1188 desc->callback = NULL; 1189 desc->callback_param = NULL; 1190 1191 /* Push current DMA transaction in the pending queue */ 1192 ret = dma_submit_error(dmaengine_submit(desc)); 1193 if (ret) { 1194 dmaengine_terminate_sync(stm32port->rx_ch); 1195 goto config_err; 1196 } 1197 1198 /* Issue pending DMA requests */ 1199 dma_async_issue_pending(stm32port->rx_ch); 1200 1201 return 0; 1202 1203 config_err: 1204 dma_free_coherent(&pdev->dev, 1205 RX_BUF_L, stm32port->rx_buf, 1206 stm32port->rx_dma_buf); 1207 1208 alloc_err: 1209 dma_release_channel(stm32port->rx_ch); 1210 stm32port->rx_ch = NULL; 1211 1212 return ret; 1213 } 1214 1215 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port, 1216 struct platform_device *pdev) 1217 { 1218 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1219 struct uart_port *port = &stm32port->port; 1220 struct device *dev = &pdev->dev; 1221 struct dma_slave_config config; 1222 int ret; 1223 1224 stm32port->tx_dma_busy = false; 1225 1226 /* Request DMA TX channel */ 1227 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 1228 if (!stm32port->tx_ch) { 1229 dev_info(dev, "tx dma alloc failed\n"); 1230 return -ENODEV; 1231 } 1232 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 1233 &stm32port->tx_dma_buf, 1234 GFP_KERNEL); 1235 if (!stm32port->tx_buf) { 1236 ret = -ENOMEM; 1237 goto alloc_err; 1238 } 1239 1240 /* Configure DMA channel */ 1241 memset(&config, 0, sizeof(config)); 1242 config.dst_addr = port->mapbase + ofs->tdr; 1243 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1244 1245 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1246 if (ret < 0) { 1247 dev_err(dev, "tx dma channel config failed\n"); 1248 ret = -ENODEV; 1249 goto config_err; 1250 } 1251 1252 return 0; 1253 1254 config_err: 1255 dma_free_coherent(&pdev->dev, 1256 TX_BUF_L, stm32port->tx_buf, 1257 stm32port->tx_dma_buf); 1258 1259 alloc_err: 1260 dma_release_channel(stm32port->tx_ch); 1261 stm32port->tx_ch = NULL; 1262 1263 return ret; 1264 } 1265 1266 static int stm32_usart_serial_probe(struct platform_device *pdev) 1267 { 1268 struct stm32_port *stm32port; 1269 int ret; 1270 1271 stm32port = stm32_usart_of_get_port(pdev); 1272 if (!stm32port) 1273 return -ENODEV; 1274 1275 stm32port->info = of_device_get_match_data(&pdev->dev); 1276 if (!stm32port->info) 1277 return -EINVAL; 1278 1279 ret = stm32_usart_init_port(stm32port, pdev); 1280 if (ret) 1281 return ret; 1282 1283 if (stm32port->wakeup_src) { 1284 device_set_wakeup_capable(&pdev->dev, true); 1285 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq); 1286 if (ret) 1287 goto err_nowup; 1288 } 1289 1290 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev); 1291 if (ret) 1292 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 1293 1294 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev); 1295 if (ret) 1296 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 1297 1298 platform_set_drvdata(pdev, &stm32port->port); 1299 1300 pm_runtime_get_noresume(&pdev->dev); 1301 pm_runtime_set_active(&pdev->dev); 1302 pm_runtime_enable(&pdev->dev); 1303 1304 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1305 if (ret) 1306 goto err_port; 1307 1308 pm_runtime_put_sync(&pdev->dev); 1309 1310 return 0; 1311 1312 err_port: 1313 pm_runtime_disable(&pdev->dev); 1314 pm_runtime_set_suspended(&pdev->dev); 1315 pm_runtime_put_noidle(&pdev->dev); 1316 1317 if (stm32port->rx_ch) { 1318 dmaengine_terminate_async(stm32port->rx_ch); 1319 dma_release_channel(stm32port->rx_ch); 1320 } 1321 1322 if (stm32port->rx_dma_buf) 1323 dma_free_coherent(&pdev->dev, 1324 RX_BUF_L, stm32port->rx_buf, 1325 stm32port->rx_dma_buf); 1326 1327 if (stm32port->tx_ch) { 1328 dmaengine_terminate_async(stm32port->tx_ch); 1329 dma_release_channel(stm32port->tx_ch); 1330 } 1331 1332 if (stm32port->tx_dma_buf) 1333 dma_free_coherent(&pdev->dev, 1334 TX_BUF_L, stm32port->tx_buf, 1335 stm32port->tx_dma_buf); 1336 1337 if (stm32port->wakeup_src) 1338 dev_pm_clear_wake_irq(&pdev->dev); 1339 1340 err_nowup: 1341 if (stm32port->wakeup_src) 1342 device_set_wakeup_capable(&pdev->dev, false); 1343 1344 stm32_usart_deinit_port(stm32port); 1345 1346 return ret; 1347 } 1348 1349 static int stm32_usart_serial_remove(struct platform_device *pdev) 1350 { 1351 struct uart_port *port = platform_get_drvdata(pdev); 1352 struct stm32_port *stm32_port = to_stm32_port(port); 1353 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1354 int err; 1355 1356 pm_runtime_get_sync(&pdev->dev); 1357 err = uart_remove_one_port(&stm32_usart_driver, port); 1358 if (err) 1359 return(err); 1360 1361 pm_runtime_disable(&pdev->dev); 1362 pm_runtime_set_suspended(&pdev->dev); 1363 pm_runtime_put_noidle(&pdev->dev); 1364 1365 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 1366 1367 if (stm32_port->rx_ch) { 1368 dmaengine_terminate_async(stm32_port->rx_ch); 1369 dma_release_channel(stm32_port->rx_ch); 1370 } 1371 1372 if (stm32_port->rx_dma_buf) 1373 dma_free_coherent(&pdev->dev, 1374 RX_BUF_L, stm32_port->rx_buf, 1375 stm32_port->rx_dma_buf); 1376 1377 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1378 1379 if (stm32_port->tx_ch) { 1380 dmaengine_terminate_async(stm32_port->tx_ch); 1381 dma_release_channel(stm32_port->tx_ch); 1382 } 1383 1384 if (stm32_port->tx_dma_buf) 1385 dma_free_coherent(&pdev->dev, 1386 TX_BUF_L, stm32_port->tx_buf, 1387 stm32_port->tx_dma_buf); 1388 1389 if (stm32_port->wakeup_src) { 1390 dev_pm_clear_wake_irq(&pdev->dev); 1391 device_init_wakeup(&pdev->dev, false); 1392 } 1393 1394 stm32_usart_deinit_port(stm32_port); 1395 1396 return 0; 1397 } 1398 1399 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1400 static void stm32_usart_console_putchar(struct uart_port *port, int ch) 1401 { 1402 struct stm32_port *stm32_port = to_stm32_port(port); 1403 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1404 1405 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 1406 cpu_relax(); 1407 1408 writel_relaxed(ch, port->membase + ofs->tdr); 1409 } 1410 1411 static void stm32_usart_console_write(struct console *co, const char *s, 1412 unsigned int cnt) 1413 { 1414 struct uart_port *port = &stm32_ports[co->index].port; 1415 struct stm32_port *stm32_port = to_stm32_port(port); 1416 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1417 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1418 unsigned long flags; 1419 u32 old_cr1, new_cr1; 1420 int locked = 1; 1421 1422 local_irq_save(flags); 1423 if (port->sysrq) 1424 locked = 0; 1425 else if (oops_in_progress) 1426 locked = spin_trylock(&port->lock); 1427 else 1428 spin_lock(&port->lock); 1429 1430 /* Save and disable interrupts, enable the transmitter */ 1431 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1432 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1433 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1434 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1435 1436 uart_console_write(port, s, cnt, stm32_usart_console_putchar); 1437 1438 /* Restore interrupt state */ 1439 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1440 1441 if (locked) 1442 spin_unlock(&port->lock); 1443 local_irq_restore(flags); 1444 } 1445 1446 static int stm32_usart_console_setup(struct console *co, char *options) 1447 { 1448 struct stm32_port *stm32port; 1449 int baud = 9600; 1450 int bits = 8; 1451 int parity = 'n'; 1452 int flow = 'n'; 1453 1454 if (co->index >= STM32_MAX_PORTS) 1455 return -ENODEV; 1456 1457 stm32port = &stm32_ports[co->index]; 1458 1459 /* 1460 * This driver does not support early console initialization 1461 * (use ARM early printk support instead), so we only expect 1462 * this to be called during the uart port registration when the 1463 * driver gets probed and the port should be mapped at that point. 1464 */ 1465 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) 1466 return -ENXIO; 1467 1468 if (options) 1469 uart_parse_options(options, &baud, &parity, &bits, &flow); 1470 1471 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1472 } 1473 1474 static struct console stm32_console = { 1475 .name = STM32_SERIAL_NAME, 1476 .device = uart_console_device, 1477 .write = stm32_usart_console_write, 1478 .setup = stm32_usart_console_setup, 1479 .flags = CON_PRINTBUFFER, 1480 .index = -1, 1481 .data = &stm32_usart_driver, 1482 }; 1483 1484 #define STM32_SERIAL_CONSOLE (&stm32_console) 1485 1486 #else 1487 #define STM32_SERIAL_CONSOLE NULL 1488 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1489 1490 static struct uart_driver stm32_usart_driver = { 1491 .driver_name = DRIVER_NAME, 1492 .dev_name = STM32_SERIAL_NAME, 1493 .major = 0, 1494 .minor = 0, 1495 .nr = STM32_MAX_PORTS, 1496 .cons = STM32_SERIAL_CONSOLE, 1497 }; 1498 1499 static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port, 1500 bool enable) 1501 { 1502 struct stm32_port *stm32_port = to_stm32_port(port); 1503 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1504 1505 if (!stm32_port->wakeup_src) 1506 return; 1507 1508 /* 1509 * Enable low-power wake-up and wake-up irq if argument is set to 1510 * "enable", disable low-power wake-up and wake-up irq otherwise 1511 */ 1512 if (enable) { 1513 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); 1514 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); 1515 } else { 1516 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1517 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 1518 } 1519 } 1520 1521 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev) 1522 { 1523 struct uart_port *port = dev_get_drvdata(dev); 1524 1525 uart_suspend_port(&stm32_usart_driver, port); 1526 1527 if (device_may_wakeup(dev) || device_wakeup_path(dev)) 1528 stm32_usart_serial_en_wakeup(port, true); 1529 1530 /* 1531 * When "no_console_suspend" is enabled, keep the pinctrl default state 1532 * and rely on bootloader stage to restore this state upon resume. 1533 * Otherwise, apply the idle or sleep states depending on wakeup 1534 * capabilities. 1535 */ 1536 if (console_suspend_enabled || !uart_console(port)) { 1537 if (device_may_wakeup(dev) || device_wakeup_path(dev)) 1538 pinctrl_pm_select_idle_state(dev); 1539 else 1540 pinctrl_pm_select_sleep_state(dev); 1541 } 1542 1543 return 0; 1544 } 1545 1546 static int __maybe_unused stm32_usart_serial_resume(struct device *dev) 1547 { 1548 struct uart_port *port = dev_get_drvdata(dev); 1549 1550 pinctrl_pm_select_default_state(dev); 1551 1552 if (device_may_wakeup(dev) || device_wakeup_path(dev)) 1553 stm32_usart_serial_en_wakeup(port, false); 1554 1555 return uart_resume_port(&stm32_usart_driver, port); 1556 } 1557 1558 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev) 1559 { 1560 struct uart_port *port = dev_get_drvdata(dev); 1561 struct stm32_port *stm32port = container_of(port, 1562 struct stm32_port, port); 1563 1564 clk_disable_unprepare(stm32port->clk); 1565 1566 return 0; 1567 } 1568 1569 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev) 1570 { 1571 struct uart_port *port = dev_get_drvdata(dev); 1572 struct stm32_port *stm32port = container_of(port, 1573 struct stm32_port, port); 1574 1575 return clk_prepare_enable(stm32port->clk); 1576 } 1577 1578 static const struct dev_pm_ops stm32_serial_pm_ops = { 1579 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend, 1580 stm32_usart_runtime_resume, NULL) 1581 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend, 1582 stm32_usart_serial_resume) 1583 }; 1584 1585 static struct platform_driver stm32_serial_driver = { 1586 .probe = stm32_usart_serial_probe, 1587 .remove = stm32_usart_serial_remove, 1588 .driver = { 1589 .name = DRIVER_NAME, 1590 .pm = &stm32_serial_pm_ops, 1591 .of_match_table = of_match_ptr(stm32_match), 1592 }, 1593 }; 1594 1595 static int __init stm32_usart_init(void) 1596 { 1597 static char banner[] __initdata = "STM32 USART driver initialized"; 1598 int ret; 1599 1600 pr_info("%s\n", banner); 1601 1602 ret = uart_register_driver(&stm32_usart_driver); 1603 if (ret) 1604 return ret; 1605 1606 ret = platform_driver_register(&stm32_serial_driver); 1607 if (ret) 1608 uart_unregister_driver(&stm32_usart_driver); 1609 1610 return ret; 1611 } 1612 1613 static void __exit stm32_usart_exit(void) 1614 { 1615 platform_driver_unregister(&stm32_serial_driver); 1616 uart_unregister_driver(&stm32_usart_driver); 1617 } 1618 1619 module_init(stm32_usart_init); 1620 module_exit(stm32_usart_exit); 1621 1622 MODULE_ALIAS("platform:" DRIVER_NAME); 1623 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1624 MODULE_LICENSE("GPL v2"); 1625