stm32-usart.c (ada8004374afc35cc3b450dec35fb53531570e7b) stm32-usart.c (270e5a74fe4c78a857d65f1a129d3d77a36b8d58)
1/*
2 * Copyright (C) Maxime Coquelin 2015
3 * Copyright (C) STMicroelectronics SA 2017
4 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
5 * Gerald Baeza <gerald.baeza@st.com>
6 * License terms: GNU General Public License (GPL), version 2
7 *
8 * Inspired by st-asc.c from STMicroelectronics (c)

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21#include <linux/io.h>
22#include <linux/iopoll.h>
23#include <linux/irq.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/of_platform.h>
27#include <linux/platform_device.h>
28#include <linux/pm_runtime.h>
1/*
2 * Copyright (C) Maxime Coquelin 2015
3 * Copyright (C) STMicroelectronics SA 2017
4 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
5 * Gerald Baeza <gerald.baeza@st.com>
6 * License terms: GNU General Public License (GPL), version 2
7 *
8 * Inspired by st-asc.c from STMicroelectronics (c)

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21#include <linux/io.h>
22#include <linux/iopoll.h>
23#include <linux/irq.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/of_platform.h>
27#include <linux/platform_device.h>
28#include <linux/pm_runtime.h>
29#include <linux/pm_wakeirq.h>
29#include <linux/serial_core.h>
30#include <linux/serial.h>
31#include <linux/spinlock.h>
32#include <linux/sysrq.h>
33#include <linux/tty_flip.h>
34#include <linux/tty.h>
35
36#include "stm32-usart.h"

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321 struct stm32_port *stm32_port = to_stm32_port(port);
322 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
323 u32 sr;
324
325 spin_lock(&port->lock);
326
327 sr = readl_relaxed(port->membase + ofs->isr);
328
30#include <linux/serial_core.h>
31#include <linux/serial.h>
32#include <linux/spinlock.h>
33#include <linux/sysrq.h>
34#include <linux/tty_flip.h>
35#include <linux/tty.h>
36
37#include "stm32-usart.h"

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322 struct stm32_port *stm32_port = to_stm32_port(port);
323 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
324 u32 sr;
325
326 spin_lock(&port->lock);
327
328 sr = readl_relaxed(port->membase + ofs->isr);
329
330 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
331 writel_relaxed(USART_ICR_WUCF,
332 port->membase + ofs->icr);
333
329 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
330 stm32_receive_chars(port, false);
331
332 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
333 stm32_transmit_chars(port);
334
335 spin_unlock(&port->lock);
336

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437static void stm32_break_ctl(struct uart_port *port, int break_state)
438{
439}
440
441static int stm32_startup(struct uart_port *port)
442{
443 struct stm32_port *stm32_port = to_stm32_port(port);
444 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
334 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
335 stm32_receive_chars(port, false);
336
337 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
338 stm32_transmit_chars(port);
339
340 spin_unlock(&port->lock);
341

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442static void stm32_break_ctl(struct uart_port *port, int break_state)
443{
444}
445
446static int stm32_startup(struct uart_port *port)
447{
448 struct stm32_port *stm32_port = to_stm32_port(port);
449 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
450 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
445 const char *name = to_platform_device(port->dev)->name;
446 u32 val;
447 int ret;
448
449 ret = request_threaded_irq(port->irq, stm32_interrupt,
450 stm32_threaded_interrupt,
451 IRQF_NO_SUSPEND, name, port);
452 if (ret)
453 return ret;
454
451 const char *name = to_platform_device(port->dev)->name;
452 u32 val;
453 int ret;
454
455 ret = request_threaded_irq(port->irq, stm32_interrupt,
456 stm32_threaded_interrupt,
457 IRQF_NO_SUSPEND, name, port);
458 if (ret)
459 return ret;
460
461 if (cfg->has_wakeup && stm32_port->wakeirq >= 0) {
462 ret = dev_pm_set_dedicated_wake_irq(port->dev,
463 stm32_port->wakeirq);
464 if (ret) {
465 free_irq(port->irq, port);
466 return ret;
467 }
468 }
469
455 val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
456 stm32_set_bits(port, ofs->cr1, val);
457
458 return 0;
459}
460
461static void stm32_shutdown(struct uart_port *port)
462{
463 struct stm32_port *stm32_port = to_stm32_port(port);
464 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
465 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
466 u32 val;
467
468 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
469 val |= BIT(cfg->uart_enable_bit);
470 stm32_clr_bits(port, ofs->cr1, val);
471
470 val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
471 stm32_set_bits(port, ofs->cr1, val);
472
473 return 0;
474}
475
476static void stm32_shutdown(struct uart_port *port)
477{
478 struct stm32_port *stm32_port = to_stm32_port(port);
479 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
480 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
481 u32 val;
482
483 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
484 val |= BIT(cfg->uart_enable_bit);
485 stm32_clr_bits(port, ofs->cr1, val);
486
487 dev_pm_clear_wake_irq(port->dev);
472 free_irq(port->irq, port);
473}
474
475static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
476 struct ktermios *old)
477{
478 struct stm32_port *stm32_port = to_stm32_port(port);
479 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;

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654 struct resource *res;
655 int ret;
656
657 port->iotype = UPIO_MEM;
658 port->flags = UPF_BOOT_AUTOCONF;
659 port->ops = &stm32_uart_ops;
660 port->dev = &pdev->dev;
661 port->irq = platform_get_irq(pdev, 0);
488 free_irq(port->irq, port);
489}
490
491static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
492 struct ktermios *old)
493{
494 struct stm32_port *stm32_port = to_stm32_port(port);
495 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;

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670 struct resource *res;
671 int ret;
672
673 port->iotype = UPIO_MEM;
674 port->flags = UPF_BOOT_AUTOCONF;
675 port->ops = &stm32_uart_ops;
676 port->dev = &pdev->dev;
677 port->irq = platform_get_irq(pdev, 0);
678 stm32port->wakeirq = platform_get_irq(pdev, 1);
662
663 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
664 port->membase = devm_ioremap_resource(&pdev->dev, res);
665 if (IS_ERR(port->membase))
666 return PTR_ERR(port->membase);
667 port->mapbase = res->start;
668
669 spin_lock_init(&port->lock);

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711}
712
713#ifdef CONFIG_OF
714static const struct of_device_id stm32_match[] = {
715 { .compatible = "st,stm32-usart", .data = &stm32f4_info},
716 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
717 { .compatible = "st,stm32f7-usart", .data = &stm32f7_info},
718 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
679
680 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
681 port->membase = devm_ioremap_resource(&pdev->dev, res);
682 if (IS_ERR(port->membase))
683 return PTR_ERR(port->membase);
684 port->mapbase = res->start;
685
686 spin_lock_init(&port->lock);

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728}
729
730#ifdef CONFIG_OF
731static const struct of_device_id stm32_match[] = {
732 { .compatible = "st,stm32-usart", .data = &stm32f4_info},
733 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
734 { .compatible = "st,stm32f7-usart", .data = &stm32f7_info},
735 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
736 { .compatible = "st,stm32h7-usart", .data = &stm32h7_info},
737 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
719 {},
720};
721
722MODULE_DEVICE_TABLE(of, stm32_match);
723#endif
724
725static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
726 struct platform_device *pdev)

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860 stm32port->info = (struct stm32_usart_info *)match->data;
861 else
862 return -EINVAL;
863
864 ret = stm32_init_port(stm32port, pdev);
865 if (ret)
866 return ret;
867
738 {},
739};
740
741MODULE_DEVICE_TABLE(of, stm32_match);
742#endif
743
744static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
745 struct platform_device *pdev)

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879 stm32port->info = (struct stm32_usart_info *)match->data;
880 else
881 return -EINVAL;
882
883 ret = stm32_init_port(stm32port, pdev);
884 if (ret)
885 return ret;
886
887 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) {
888 ret = device_init_wakeup(&pdev->dev, true);
889 if (ret)
890 goto err_uninit;
891 }
892
868 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
869 if (ret)
893 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
894 if (ret)
870 goto err_uninit;
895 goto err_nowup;
871
872 ret = stm32_of_dma_rx_probe(stm32port, pdev);
873 if (ret)
874 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
875
876 ret = stm32_of_dma_tx_probe(stm32port, pdev);
877 if (ret)
878 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
879
880 platform_set_drvdata(pdev, &stm32port->port);
881
882 return 0;
883
896
897 ret = stm32_of_dma_rx_probe(stm32port, pdev);
898 if (ret)
899 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
900
901 ret = stm32_of_dma_tx_probe(stm32port, pdev);
902 if (ret)
903 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
904
905 platform_set_drvdata(pdev, &stm32port->port);
906
907 return 0;
908
909err_nowup:
910 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
911 device_init_wakeup(&pdev->dev, false);
912
884err_uninit:
885 clk_disable_unprepare(stm32port->clk);
886
887 return ret;
888}
889
890static int stm32_serial_remove(struct platform_device *pdev)
891{
892 struct uart_port *port = platform_get_drvdata(pdev);
893 struct stm32_port *stm32_port = to_stm32_port(port);
894 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
913err_uninit:
914 clk_disable_unprepare(stm32port->clk);
915
916 return ret;
917}
918
919static int stm32_serial_remove(struct platform_device *pdev)
920{
921 struct uart_port *port = platform_get_drvdata(pdev);
922 struct stm32_port *stm32_port = to_stm32_port(port);
923 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
924 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
895
896 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
897
898 if (stm32_port->rx_ch)
899 dma_release_channel(stm32_port->rx_ch);
900
901 if (stm32_port->rx_dma_buf)
902 dma_free_coherent(&pdev->dev,

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908 if (stm32_port->tx_ch)
909 dma_release_channel(stm32_port->tx_ch);
910
911 if (stm32_port->tx_dma_buf)
912 dma_free_coherent(&pdev->dev,
913 TX_BUF_L, stm32_port->tx_buf,
914 stm32_port->tx_dma_buf);
915
925
926 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
927
928 if (stm32_port->rx_ch)
929 dma_release_channel(stm32_port->rx_ch);
930
931 if (stm32_port->rx_dma_buf)
932 dma_free_coherent(&pdev->dev,

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938 if (stm32_port->tx_ch)
939 dma_release_channel(stm32_port->tx_ch);
940
941 if (stm32_port->tx_dma_buf)
942 dma_free_coherent(&pdev->dev,
943 TX_BUF_L, stm32_port->tx_buf,
944 stm32_port->tx_dma_buf);
945
946 if (cfg->has_wakeup && stm32_port->wakeirq >= 0)
947 device_init_wakeup(&pdev->dev, false);
948
916 clk_disable_unprepare(stm32_port->clk);
917
918 return uart_remove_one_port(&stm32_usart_driver, port);
919}
920
921
922#ifdef CONFIG_SERIAL_STM32_CONSOLE
923static void stm32_console_putchar(struct uart_port *port, int ch)

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1013 .driver_name = DRIVER_NAME,
1014 .dev_name = STM32_SERIAL_NAME,
1015 .major = 0,
1016 .minor = 0,
1017 .nr = STM32_MAX_PORTS,
1018 .cons = STM32_SERIAL_CONSOLE,
1019};
1020
949 clk_disable_unprepare(stm32_port->clk);
950
951 return uart_remove_one_port(&stm32_usart_driver, port);
952}
953
954
955#ifdef CONFIG_SERIAL_STM32_CONSOLE
956static void stm32_console_putchar(struct uart_port *port, int ch)

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1046 .driver_name = DRIVER_NAME,
1047 .dev_name = STM32_SERIAL_NAME,
1048 .major = 0,
1049 .minor = 0,
1050 .nr = STM32_MAX_PORTS,
1051 .cons = STM32_SERIAL_CONSOLE,
1052};
1053
1054#ifdef CONFIG_PM_SLEEP
1055static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable)
1056{
1057 struct stm32_port *stm32_port = to_stm32_port(port);
1058 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1059 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1060 u32 val;
1061
1062 if (!cfg->has_wakeup || stm32_port->wakeirq < 0)
1063 return;
1064
1065 if (enable) {
1066 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1067 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1068 val = readl_relaxed(port->membase + ofs->cr3);
1069 val &= ~USART_CR3_WUS_MASK;
1070 /* Enable Wake up interrupt from low power on start bit */
1071 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1072 writel_relaxed(val, port->membase + ofs->cr3);
1073 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1074 } else {
1075 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1076 }
1077}
1078
1079static int stm32_serial_suspend(struct device *dev)
1080{
1081 struct uart_port *port = dev_get_drvdata(dev);
1082
1083 uart_suspend_port(&stm32_usart_driver, port);
1084
1085 if (device_may_wakeup(dev))
1086 stm32_serial_enable_wakeup(port, true);
1087 else
1088 stm32_serial_enable_wakeup(port, false);
1089
1090 return 0;
1091}
1092
1093static int stm32_serial_resume(struct device *dev)
1094{
1095 struct uart_port *port = dev_get_drvdata(dev);
1096
1097 if (device_may_wakeup(dev))
1098 stm32_serial_enable_wakeup(port, false);
1099
1100 return uart_resume_port(&stm32_usart_driver, port);
1101}
1102#endif /* CONFIG_PM_SLEEP */
1103
1104static const struct dev_pm_ops stm32_serial_pm_ops = {
1105 SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1106};
1107
1021static struct platform_driver stm32_serial_driver = {
1022 .probe = stm32_serial_probe,
1023 .remove = stm32_serial_remove,
1024 .driver = {
1025 .name = DRIVER_NAME,
1108static struct platform_driver stm32_serial_driver = {
1109 .probe = stm32_serial_probe,
1110 .remove = stm32_serial_remove,
1111 .driver = {
1112 .name = DRIVER_NAME,
1113 .pm = &stm32_serial_pm_ops,
1026 .of_match_table = of_match_ptr(stm32_match),
1027 },
1028};
1029
1030static int __init usart_init(void)
1031{
1032 static char banner[] __initdata = "STM32 USART driver initialized";
1033 int ret;

--- 26 unchanged lines hidden --- 		1114 .of_match_table = of_match_ptr(stm32_match),
1115 },
1116};
1117
1118static int __init usart_init(void)
1119{
1120 static char banner[] __initdata = "STM32 USART driver initialized";
1121 int ret;

--- 26 unchanged lines hidden ---