1 /* 2 * Copyright (C) Maxime Coquelin 2015 3 * Copyright (C) STMicroelectronics SA 2017 4 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 5 * Gerald Baeza <gerald.baeza@st.com> 6 * License terms: GNU General Public License (GPL), version 2 7 * 8 * Inspired by st-asc.c from STMicroelectronics (c) 9 */ 10 11 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 12 #define SUPPORT_SYSRQ 13 #endif 14 15 #include <linux/clk.h> 16 #include <linux/console.h> 17 #include <linux/delay.h> 18 #include <linux/dma-direction.h> 19 #include <linux/dmaengine.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/irq.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/of_platform.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/pm_wakeirq.h> 30 #include <linux/serial_core.h> 31 #include <linux/serial.h> 32 #include <linux/spinlock.h> 33 #include <linux/sysrq.h> 34 #include <linux/tty_flip.h> 35 #include <linux/tty.h> 36 37 #include "stm32-usart.h" 38 39 static void stm32_stop_tx(struct uart_port *port); 40 static void stm32_transmit_chars(struct uart_port *port); 41 42 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 43 { 44 return container_of(port, struct stm32_port, port); 45 } 46 47 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits) 48 { 49 u32 val; 50 51 val = readl_relaxed(port->membase + reg); 52 val |= bits; 53 writel_relaxed(val, port->membase + reg); 54 } 55 56 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits) 57 { 58 u32 val; 59 60 val = readl_relaxed(port->membase + reg); 61 val &= ~bits; 62 writel_relaxed(val, port->membase + reg); 63 } 64 65 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res, 66 bool threaded) 67 { 68 struct stm32_port *stm32_port = to_stm32_port(port); 69 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 70 enum dma_status status; 71 struct dma_tx_state state; 72 73 *sr = readl_relaxed(port->membase + ofs->isr); 74 75 if (threaded && stm32_port->rx_ch) { 76 status = dmaengine_tx_status(stm32_port->rx_ch, 77 stm32_port->rx_ch->cookie, 78 &state); 79 if ((status == DMA_IN_PROGRESS) && 80 (*last_res != state.residue)) 81 return 1; 82 else 83 return 0; 84 } else if (*sr & USART_SR_RXNE) { 85 return 1; 86 } 87 return 0; 88 } 89 90 static unsigned long 91 stm32_get_char(struct uart_port *port, u32 *sr, int *last_res) 92 { 93 struct stm32_port *stm32_port = to_stm32_port(port); 94 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 95 unsigned long c; 96 97 if (stm32_port->rx_ch) { 98 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 99 if ((*last_res) == 0) 100 *last_res = RX_BUF_L; 101 return c; 102 } else { 103 return readl_relaxed(port->membase + ofs->rdr); 104 } 105 } 106 107 static void stm32_receive_chars(struct uart_port *port, bool threaded) 108 { 109 struct tty_port *tport = &port->state->port; 110 struct stm32_port *stm32_port = to_stm32_port(port); 111 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 112 unsigned long c; 113 u32 sr; 114 char flag; 115 116 if (port->irq_wake) 117 pm_wakeup_event(tport->tty->dev, 0); 118 119 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) { 120 sr |= USART_SR_DUMMY_RX; 121 c = stm32_get_char(port, &sr, &stm32_port->last_res); 122 flag = TTY_NORMAL; 123 port->icount.rx++; 124 125 if (sr & USART_SR_ERR_MASK) { 126 if (sr & USART_SR_LBD) { 127 port->icount.brk++; 128 if (uart_handle_break(port)) 129 continue; 130 } else if (sr & USART_SR_ORE) { 131 if (ofs->icr != UNDEF_REG) 132 writel_relaxed(USART_ICR_ORECF, 133 port->membase + 134 ofs->icr); 135 port->icount.overrun++; 136 } else if (sr & USART_SR_PE) { 137 port->icount.parity++; 138 } else if (sr & USART_SR_FE) { 139 port->icount.frame++; 140 } 141 142 sr &= port->read_status_mask; 143 144 if (sr & USART_SR_LBD) 145 flag = TTY_BREAK; 146 else if (sr & USART_SR_PE) 147 flag = TTY_PARITY; 148 else if (sr & USART_SR_FE) 149 flag = TTY_FRAME; 150 } 151 152 if (uart_handle_sysrq_char(port, c)) 153 continue; 154 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 155 } 156 157 spin_unlock(&port->lock); 158 tty_flip_buffer_push(tport); 159 spin_lock(&port->lock); 160 } 161 162 static void stm32_tx_dma_complete(void *arg) 163 { 164 struct uart_port *port = arg; 165 struct stm32_port *stm32port = to_stm32_port(port); 166 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 167 unsigned int isr; 168 int ret; 169 170 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 171 isr, 172 (isr & USART_SR_TC), 173 10, 100000); 174 175 if (ret) 176 dev_err(port->dev, "terminal count not set\n"); 177 178 if (ofs->icr == UNDEF_REG) 179 stm32_clr_bits(port, ofs->isr, USART_SR_TC); 180 else 181 stm32_set_bits(port, ofs->icr, USART_CR_TC); 182 183 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 184 stm32port->tx_dma_busy = false; 185 186 /* Let's see if we have pending data to send */ 187 stm32_transmit_chars(port); 188 } 189 190 static void stm32_transmit_chars_pio(struct uart_port *port) 191 { 192 struct stm32_port *stm32_port = to_stm32_port(port); 193 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 194 struct circ_buf *xmit = &port->state->xmit; 195 unsigned int isr; 196 int ret; 197 198 if (stm32_port->tx_dma_busy) { 199 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 200 stm32_port->tx_dma_busy = false; 201 } 202 203 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 204 isr, 205 (isr & USART_SR_TXE), 206 10, 100); 207 208 if (ret) 209 dev_err(port->dev, "tx empty not set\n"); 210 211 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 212 213 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 214 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 215 port->icount.tx++; 216 } 217 218 static void stm32_transmit_chars_dma(struct uart_port *port) 219 { 220 struct stm32_port *stm32port = to_stm32_port(port); 221 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 222 struct circ_buf *xmit = &port->state->xmit; 223 struct dma_async_tx_descriptor *desc = NULL; 224 dma_cookie_t cookie; 225 unsigned int count, i; 226 227 if (stm32port->tx_dma_busy) 228 return; 229 230 stm32port->tx_dma_busy = true; 231 232 count = uart_circ_chars_pending(xmit); 233 234 if (count > TX_BUF_L) 235 count = TX_BUF_L; 236 237 if (xmit->tail < xmit->head) { 238 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 239 } else { 240 size_t one = UART_XMIT_SIZE - xmit->tail; 241 size_t two; 242 243 if (one > count) 244 one = count; 245 two = count - one; 246 247 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 248 if (two) 249 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 250 } 251 252 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 253 stm32port->tx_dma_buf, 254 count, 255 DMA_MEM_TO_DEV, 256 DMA_PREP_INTERRUPT); 257 258 if (!desc) { 259 for (i = count; i > 0; i--) 260 stm32_transmit_chars_pio(port); 261 return; 262 } 263 264 desc->callback = stm32_tx_dma_complete; 265 desc->callback_param = port; 266 267 /* Push current DMA TX transaction in the pending queue */ 268 cookie = dmaengine_submit(desc); 269 270 /* Issue pending DMA TX requests */ 271 dma_async_issue_pending(stm32port->tx_ch); 272 273 stm32_clr_bits(port, ofs->isr, USART_SR_TC); 274 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 275 276 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 277 port->icount.tx += count; 278 } 279 280 static void stm32_transmit_chars(struct uart_port *port) 281 { 282 struct stm32_port *stm32_port = to_stm32_port(port); 283 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 284 struct circ_buf *xmit = &port->state->xmit; 285 286 if (port->x_char) { 287 if (stm32_port->tx_dma_busy) 288 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 289 writel_relaxed(port->x_char, port->membase + ofs->tdr); 290 port->x_char = 0; 291 port->icount.tx++; 292 if (stm32_port->tx_dma_busy) 293 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 294 return; 295 } 296 297 if (uart_tx_stopped(port)) { 298 stm32_stop_tx(port); 299 return; 300 } 301 302 if (uart_circ_empty(xmit)) { 303 stm32_stop_tx(port); 304 return; 305 } 306 307 if (stm32_port->tx_ch) 308 stm32_transmit_chars_dma(port); 309 else 310 stm32_transmit_chars_pio(port); 311 312 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 313 uart_write_wakeup(port); 314 315 if (uart_circ_empty(xmit)) 316 stm32_stop_tx(port); 317 } 318 319 static irqreturn_t stm32_interrupt(int irq, void *ptr) 320 { 321 struct uart_port *port = ptr; 322 struct stm32_port *stm32_port = to_stm32_port(port); 323 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 324 u32 sr; 325 326 spin_lock(&port->lock); 327 328 sr = readl_relaxed(port->membase + ofs->isr); 329 330 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG)) 331 writel_relaxed(USART_ICR_WUCF, 332 port->membase + ofs->icr); 333 334 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 335 stm32_receive_chars(port, false); 336 337 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) 338 stm32_transmit_chars(port); 339 340 spin_unlock(&port->lock); 341 342 if (stm32_port->rx_ch) 343 return IRQ_WAKE_THREAD; 344 else 345 return IRQ_HANDLED; 346 } 347 348 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr) 349 { 350 struct uart_port *port = ptr; 351 struct stm32_port *stm32_port = to_stm32_port(port); 352 353 spin_lock(&port->lock); 354 355 if (stm32_port->rx_ch) 356 stm32_receive_chars(port, true); 357 358 spin_unlock(&port->lock); 359 360 return IRQ_HANDLED; 361 } 362 363 static unsigned int stm32_tx_empty(struct uart_port *port) 364 { 365 struct stm32_port *stm32_port = to_stm32_port(port); 366 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 367 368 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 369 } 370 371 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl) 372 { 373 struct stm32_port *stm32_port = to_stm32_port(port); 374 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 375 376 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 377 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE); 378 else 379 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 380 } 381 382 static unsigned int stm32_get_mctrl(struct uart_port *port) 383 { 384 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 385 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 386 } 387 388 /* Transmit stop */ 389 static void stm32_stop_tx(struct uart_port *port) 390 { 391 struct stm32_port *stm32_port = to_stm32_port(port); 392 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 393 394 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 395 } 396 397 /* There are probably characters waiting to be transmitted. */ 398 static void stm32_start_tx(struct uart_port *port) 399 { 400 struct circ_buf *xmit = &port->state->xmit; 401 402 if (uart_circ_empty(xmit)) 403 return; 404 405 stm32_transmit_chars(port); 406 } 407 408 /* Throttle the remote when input buffer is about to overflow. */ 409 static void stm32_throttle(struct uart_port *port) 410 { 411 struct stm32_port *stm32_port = to_stm32_port(port); 412 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 413 unsigned long flags; 414 415 spin_lock_irqsave(&port->lock, flags); 416 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); 417 spin_unlock_irqrestore(&port->lock, flags); 418 } 419 420 /* Unthrottle the remote, the input buffer can now accept data. */ 421 static void stm32_unthrottle(struct uart_port *port) 422 { 423 struct stm32_port *stm32_port = to_stm32_port(port); 424 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 425 unsigned long flags; 426 427 spin_lock_irqsave(&port->lock, flags); 428 stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE); 429 spin_unlock_irqrestore(&port->lock, flags); 430 } 431 432 /* Receive stop */ 433 static void stm32_stop_rx(struct uart_port *port) 434 { 435 struct stm32_port *stm32_port = to_stm32_port(port); 436 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 437 438 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); 439 } 440 441 /* Handle breaks - ignored by us */ 442 static void stm32_break_ctl(struct uart_port *port, int break_state) 443 { 444 } 445 446 static int stm32_startup(struct uart_port *port) 447 { 448 struct stm32_port *stm32_port = to_stm32_port(port); 449 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 450 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 451 const char *name = to_platform_device(port->dev)->name; 452 u32 val; 453 int ret; 454 455 ret = request_threaded_irq(port->irq, stm32_interrupt, 456 stm32_threaded_interrupt, 457 IRQF_NO_SUSPEND, name, port); 458 if (ret) 459 return ret; 460 461 if (cfg->has_wakeup && stm32_port->wakeirq >= 0) { 462 ret = dev_pm_set_dedicated_wake_irq(port->dev, 463 stm32_port->wakeirq); 464 if (ret) { 465 free_irq(port->irq, port); 466 return ret; 467 } 468 } 469 470 val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; 471 stm32_set_bits(port, ofs->cr1, val); 472 473 return 0; 474 } 475 476 static void stm32_shutdown(struct uart_port *port) 477 { 478 struct stm32_port *stm32_port = to_stm32_port(port); 479 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 480 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 481 u32 val; 482 483 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; 484 val |= BIT(cfg->uart_enable_bit); 485 stm32_clr_bits(port, ofs->cr1, val); 486 487 dev_pm_clear_wake_irq(port->dev); 488 free_irq(port->irq, port); 489 } 490 491 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, 492 struct ktermios *old) 493 { 494 struct stm32_port *stm32_port = to_stm32_port(port); 495 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 496 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 497 unsigned int baud; 498 u32 usartdiv, mantissa, fraction, oversampling; 499 tcflag_t cflag = termios->c_cflag; 500 u32 cr1, cr2, cr3; 501 unsigned long flags; 502 503 if (!stm32_port->hw_flow_control) 504 cflag &= ~CRTSCTS; 505 506 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 507 508 spin_lock_irqsave(&port->lock, flags); 509 510 /* Stop serial port and reset value */ 511 writel_relaxed(0, port->membase + ofs->cr1); 512 513 cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE; 514 cr1 |= BIT(cfg->uart_enable_bit); 515 cr2 = 0; 516 cr3 = 0; 517 518 if (cflag & CSTOPB) 519 cr2 |= USART_CR2_STOP_2B; 520 521 if (cflag & PARENB) { 522 cr1 |= USART_CR1_PCE; 523 if ((cflag & CSIZE) == CS8) { 524 if (cfg->has_7bits_data) 525 cr1 |= USART_CR1_M0; 526 else 527 cr1 |= USART_CR1_M; 528 } 529 } 530 531 if (cflag & PARODD) 532 cr1 |= USART_CR1_PS; 533 534 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 535 if (cflag & CRTSCTS) { 536 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 537 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 538 } 539 540 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 541 542 /* 543 * The USART supports 16 or 8 times oversampling. 544 * By default we prefer 16 times oversampling, so that the receiver 545 * has a better tolerance to clock deviations. 546 * 8 times oversampling is only used to achieve higher speeds. 547 */ 548 if (usartdiv < 16) { 549 oversampling = 8; 550 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8); 551 } else { 552 oversampling = 16; 553 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 554 } 555 556 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 557 fraction = usartdiv % oversampling; 558 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 559 560 uart_update_timeout(port, cflag, baud); 561 562 port->read_status_mask = USART_SR_ORE; 563 if (termios->c_iflag & INPCK) 564 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 565 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 566 port->read_status_mask |= USART_SR_LBD; 567 568 /* Characters to ignore */ 569 port->ignore_status_mask = 0; 570 if (termios->c_iflag & IGNPAR) 571 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 572 if (termios->c_iflag & IGNBRK) { 573 port->ignore_status_mask |= USART_SR_LBD; 574 /* 575 * If we're ignoring parity and break indicators, 576 * ignore overruns too (for real raw support). 577 */ 578 if (termios->c_iflag & IGNPAR) 579 port->ignore_status_mask |= USART_SR_ORE; 580 } 581 582 /* Ignore all characters if CREAD is not set */ 583 if ((termios->c_cflag & CREAD) == 0) 584 port->ignore_status_mask |= USART_SR_DUMMY_RX; 585 586 if (stm32_port->rx_ch) 587 cr3 |= USART_CR3_DMAR; 588 589 writel_relaxed(cr3, port->membase + ofs->cr3); 590 writel_relaxed(cr2, port->membase + ofs->cr2); 591 writel_relaxed(cr1, port->membase + ofs->cr1); 592 593 spin_unlock_irqrestore(&port->lock, flags); 594 } 595 596 static const char *stm32_type(struct uart_port *port) 597 { 598 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 599 } 600 601 static void stm32_release_port(struct uart_port *port) 602 { 603 } 604 605 static int stm32_request_port(struct uart_port *port) 606 { 607 return 0; 608 } 609 610 static void stm32_config_port(struct uart_port *port, int flags) 611 { 612 if (flags & UART_CONFIG_TYPE) 613 port->type = PORT_STM32; 614 } 615 616 static int 617 stm32_verify_port(struct uart_port *port, struct serial_struct *ser) 618 { 619 /* No user changeable parameters */ 620 return -EINVAL; 621 } 622 623 static void stm32_pm(struct uart_port *port, unsigned int state, 624 unsigned int oldstate) 625 { 626 struct stm32_port *stm32port = container_of(port, 627 struct stm32_port, port); 628 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 629 struct stm32_usart_config *cfg = &stm32port->info->cfg; 630 unsigned long flags = 0; 631 632 switch (state) { 633 case UART_PM_STATE_ON: 634 clk_prepare_enable(stm32port->clk); 635 break; 636 case UART_PM_STATE_OFF: 637 spin_lock_irqsave(&port->lock, flags); 638 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 639 spin_unlock_irqrestore(&port->lock, flags); 640 clk_disable_unprepare(stm32port->clk); 641 break; 642 } 643 } 644 645 static const struct uart_ops stm32_uart_ops = { 646 .tx_empty = stm32_tx_empty, 647 .set_mctrl = stm32_set_mctrl, 648 .get_mctrl = stm32_get_mctrl, 649 .stop_tx = stm32_stop_tx, 650 .start_tx = stm32_start_tx, 651 .throttle = stm32_throttle, 652 .unthrottle = stm32_unthrottle, 653 .stop_rx = stm32_stop_rx, 654 .break_ctl = stm32_break_ctl, 655 .startup = stm32_startup, 656 .shutdown = stm32_shutdown, 657 .set_termios = stm32_set_termios, 658 .pm = stm32_pm, 659 .type = stm32_type, 660 .release_port = stm32_release_port, 661 .request_port = stm32_request_port, 662 .config_port = stm32_config_port, 663 .verify_port = stm32_verify_port, 664 }; 665 666 static int stm32_init_port(struct stm32_port *stm32port, 667 struct platform_device *pdev) 668 { 669 struct uart_port *port = &stm32port->port; 670 struct resource *res; 671 int ret; 672 673 port->iotype = UPIO_MEM; 674 port->flags = UPF_BOOT_AUTOCONF; 675 port->ops = &stm32_uart_ops; 676 port->dev = &pdev->dev; 677 port->irq = platform_get_irq(pdev, 0); 678 stm32port->wakeirq = platform_get_irq(pdev, 1); 679 680 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 681 port->membase = devm_ioremap_resource(&pdev->dev, res); 682 if (IS_ERR(port->membase)) 683 return PTR_ERR(port->membase); 684 port->mapbase = res->start; 685 686 spin_lock_init(&port->lock); 687 688 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 689 if (IS_ERR(stm32port->clk)) 690 return PTR_ERR(stm32port->clk); 691 692 /* Ensure that clk rate is correct by enabling the clk */ 693 ret = clk_prepare_enable(stm32port->clk); 694 if (ret) 695 return ret; 696 697 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 698 if (!stm32port->port.uartclk) { 699 clk_disable_unprepare(stm32port->clk); 700 ret = -EINVAL; 701 } 702 703 return ret; 704 } 705 706 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev) 707 { 708 struct device_node *np = pdev->dev.of_node; 709 int id; 710 711 if (!np) 712 return NULL; 713 714 id = of_alias_get_id(np, "serial"); 715 if (id < 0) { 716 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 717 return NULL; 718 } 719 720 if (WARN_ON(id >= STM32_MAX_PORTS)) 721 return NULL; 722 723 stm32_ports[id].hw_flow_control = of_property_read_bool(np, 724 "st,hw-flow-ctrl"); 725 stm32_ports[id].port.line = id; 726 stm32_ports[id].last_res = RX_BUF_L; 727 return &stm32_ports[id]; 728 } 729 730 #ifdef CONFIG_OF 731 static const struct of_device_id stm32_match[] = { 732 { .compatible = "st,stm32-usart", .data = &stm32f4_info}, 733 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 734 { .compatible = "st,stm32f7-usart", .data = &stm32f7_info}, 735 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 736 { .compatible = "st,stm32h7-usart", .data = &stm32h7_info}, 737 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 738 {}, 739 }; 740 741 MODULE_DEVICE_TABLE(of, stm32_match); 742 #endif 743 744 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port, 745 struct platform_device *pdev) 746 { 747 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 748 struct uart_port *port = &stm32port->port; 749 struct device *dev = &pdev->dev; 750 struct dma_slave_config config; 751 struct dma_async_tx_descriptor *desc = NULL; 752 dma_cookie_t cookie; 753 int ret; 754 755 /* Request DMA RX channel */ 756 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 757 if (!stm32port->rx_ch) { 758 dev_info(dev, "rx dma alloc failed\n"); 759 return -ENODEV; 760 } 761 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 762 &stm32port->rx_dma_buf, 763 GFP_KERNEL); 764 if (!stm32port->rx_buf) { 765 ret = -ENOMEM; 766 goto alloc_err; 767 } 768 769 /* Configure DMA channel */ 770 memset(&config, 0, sizeof(config)); 771 config.src_addr = port->mapbase + ofs->rdr; 772 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 773 774 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 775 if (ret < 0) { 776 dev_err(dev, "rx dma channel config failed\n"); 777 ret = -ENODEV; 778 goto config_err; 779 } 780 781 /* Prepare a DMA cyclic transaction */ 782 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 783 stm32port->rx_dma_buf, 784 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 785 DMA_PREP_INTERRUPT); 786 if (!desc) { 787 dev_err(dev, "rx dma prep cyclic failed\n"); 788 ret = -ENODEV; 789 goto config_err; 790 } 791 792 /* No callback as dma buffer is drained on usart interrupt */ 793 desc->callback = NULL; 794 desc->callback_param = NULL; 795 796 /* Push current DMA transaction in the pending queue */ 797 cookie = dmaengine_submit(desc); 798 799 /* Issue pending DMA requests */ 800 dma_async_issue_pending(stm32port->rx_ch); 801 802 return 0; 803 804 config_err: 805 dma_free_coherent(&pdev->dev, 806 RX_BUF_L, stm32port->rx_buf, 807 stm32port->rx_dma_buf); 808 809 alloc_err: 810 dma_release_channel(stm32port->rx_ch); 811 stm32port->rx_ch = NULL; 812 813 return ret; 814 } 815 816 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port, 817 struct platform_device *pdev) 818 { 819 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 820 struct uart_port *port = &stm32port->port; 821 struct device *dev = &pdev->dev; 822 struct dma_slave_config config; 823 int ret; 824 825 stm32port->tx_dma_busy = false; 826 827 /* Request DMA TX channel */ 828 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 829 if (!stm32port->tx_ch) { 830 dev_info(dev, "tx dma alloc failed\n"); 831 return -ENODEV; 832 } 833 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 834 &stm32port->tx_dma_buf, 835 GFP_KERNEL); 836 if (!stm32port->tx_buf) { 837 ret = -ENOMEM; 838 goto alloc_err; 839 } 840 841 /* Configure DMA channel */ 842 memset(&config, 0, sizeof(config)); 843 config.dst_addr = port->mapbase + ofs->tdr; 844 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 845 846 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 847 if (ret < 0) { 848 dev_err(dev, "tx dma channel config failed\n"); 849 ret = -ENODEV; 850 goto config_err; 851 } 852 853 return 0; 854 855 config_err: 856 dma_free_coherent(&pdev->dev, 857 TX_BUF_L, stm32port->tx_buf, 858 stm32port->tx_dma_buf); 859 860 alloc_err: 861 dma_release_channel(stm32port->tx_ch); 862 stm32port->tx_ch = NULL; 863 864 return ret; 865 } 866 867 static int stm32_serial_probe(struct platform_device *pdev) 868 { 869 const struct of_device_id *match; 870 struct stm32_port *stm32port; 871 int ret; 872 873 stm32port = stm32_of_get_stm32_port(pdev); 874 if (!stm32port) 875 return -ENODEV; 876 877 match = of_match_device(stm32_match, &pdev->dev); 878 if (match && match->data) 879 stm32port->info = (struct stm32_usart_info *)match->data; 880 else 881 return -EINVAL; 882 883 ret = stm32_init_port(stm32port, pdev); 884 if (ret) 885 return ret; 886 887 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) { 888 ret = device_init_wakeup(&pdev->dev, true); 889 if (ret) 890 goto err_uninit; 891 } 892 893 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 894 if (ret) 895 goto err_nowup; 896 897 ret = stm32_of_dma_rx_probe(stm32port, pdev); 898 if (ret) 899 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 900 901 ret = stm32_of_dma_tx_probe(stm32port, pdev); 902 if (ret) 903 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 904 905 platform_set_drvdata(pdev, &stm32port->port); 906 907 return 0; 908 909 err_nowup: 910 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) 911 device_init_wakeup(&pdev->dev, false); 912 913 err_uninit: 914 clk_disable_unprepare(stm32port->clk); 915 916 return ret; 917 } 918 919 static int stm32_serial_remove(struct platform_device *pdev) 920 { 921 struct uart_port *port = platform_get_drvdata(pdev); 922 struct stm32_port *stm32_port = to_stm32_port(port); 923 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 924 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 925 926 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 927 928 if (stm32_port->rx_ch) 929 dma_release_channel(stm32_port->rx_ch); 930 931 if (stm32_port->rx_dma_buf) 932 dma_free_coherent(&pdev->dev, 933 RX_BUF_L, stm32_port->rx_buf, 934 stm32_port->rx_dma_buf); 935 936 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 937 938 if (stm32_port->tx_ch) 939 dma_release_channel(stm32_port->tx_ch); 940 941 if (stm32_port->tx_dma_buf) 942 dma_free_coherent(&pdev->dev, 943 TX_BUF_L, stm32_port->tx_buf, 944 stm32_port->tx_dma_buf); 945 946 if (cfg->has_wakeup && stm32_port->wakeirq >= 0) 947 device_init_wakeup(&pdev->dev, false); 948 949 clk_disable_unprepare(stm32_port->clk); 950 951 return uart_remove_one_port(&stm32_usart_driver, port); 952 } 953 954 955 #ifdef CONFIG_SERIAL_STM32_CONSOLE 956 static void stm32_console_putchar(struct uart_port *port, int ch) 957 { 958 struct stm32_port *stm32_port = to_stm32_port(port); 959 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 960 961 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 962 cpu_relax(); 963 964 writel_relaxed(ch, port->membase + ofs->tdr); 965 } 966 967 static void stm32_console_write(struct console *co, const char *s, unsigned cnt) 968 { 969 struct uart_port *port = &stm32_ports[co->index].port; 970 struct stm32_port *stm32_port = to_stm32_port(port); 971 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 972 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 973 unsigned long flags; 974 u32 old_cr1, new_cr1; 975 int locked = 1; 976 977 local_irq_save(flags); 978 if (port->sysrq) 979 locked = 0; 980 else if (oops_in_progress) 981 locked = spin_trylock(&port->lock); 982 else 983 spin_lock(&port->lock); 984 985 /* Save and disable interrupts, enable the transmitter */ 986 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 987 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 988 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 989 writel_relaxed(new_cr1, port->membase + ofs->cr1); 990 991 uart_console_write(port, s, cnt, stm32_console_putchar); 992 993 /* Restore interrupt state */ 994 writel_relaxed(old_cr1, port->membase + ofs->cr1); 995 996 if (locked) 997 spin_unlock(&port->lock); 998 local_irq_restore(flags); 999 } 1000 1001 static int stm32_console_setup(struct console *co, char *options) 1002 { 1003 struct stm32_port *stm32port; 1004 int baud = 9600; 1005 int bits = 8; 1006 int parity = 'n'; 1007 int flow = 'n'; 1008 1009 if (co->index >= STM32_MAX_PORTS) 1010 return -ENODEV; 1011 1012 stm32port = &stm32_ports[co->index]; 1013 1014 /* 1015 * This driver does not support early console initialization 1016 * (use ARM early printk support instead), so we only expect 1017 * this to be called during the uart port registration when the 1018 * driver gets probed and the port should be mapped at that point. 1019 */ 1020 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL) 1021 return -ENXIO; 1022 1023 if (options) 1024 uart_parse_options(options, &baud, &parity, &bits, &flow); 1025 1026 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1027 } 1028 1029 static struct console stm32_console = { 1030 .name = STM32_SERIAL_NAME, 1031 .device = uart_console_device, 1032 .write = stm32_console_write, 1033 .setup = stm32_console_setup, 1034 .flags = CON_PRINTBUFFER, 1035 .index = -1, 1036 .data = &stm32_usart_driver, 1037 }; 1038 1039 #define STM32_SERIAL_CONSOLE (&stm32_console) 1040 1041 #else 1042 #define STM32_SERIAL_CONSOLE NULL 1043 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1044 1045 static struct uart_driver stm32_usart_driver = { 1046 .driver_name = DRIVER_NAME, 1047 .dev_name = STM32_SERIAL_NAME, 1048 .major = 0, 1049 .minor = 0, 1050 .nr = STM32_MAX_PORTS, 1051 .cons = STM32_SERIAL_CONSOLE, 1052 }; 1053 1054 #ifdef CONFIG_PM_SLEEP 1055 static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable) 1056 { 1057 struct stm32_port *stm32_port = to_stm32_port(port); 1058 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1059 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1060 u32 val; 1061 1062 if (!cfg->has_wakeup || stm32_port->wakeirq < 0) 1063 return; 1064 1065 if (enable) { 1066 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1067 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM); 1068 val = readl_relaxed(port->membase + ofs->cr3); 1069 val &= ~USART_CR3_WUS_MASK; 1070 /* Enable Wake up interrupt from low power on start bit */ 1071 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE; 1072 writel_relaxed(val, port->membase + ofs->cr3); 1073 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1074 } else { 1075 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1076 } 1077 } 1078 1079 static int stm32_serial_suspend(struct device *dev) 1080 { 1081 struct uart_port *port = dev_get_drvdata(dev); 1082 1083 uart_suspend_port(&stm32_usart_driver, port); 1084 1085 if (device_may_wakeup(dev)) 1086 stm32_serial_enable_wakeup(port, true); 1087 else 1088 stm32_serial_enable_wakeup(port, false); 1089 1090 return 0; 1091 } 1092 1093 static int stm32_serial_resume(struct device *dev) 1094 { 1095 struct uart_port *port = dev_get_drvdata(dev); 1096 1097 if (device_may_wakeup(dev)) 1098 stm32_serial_enable_wakeup(port, false); 1099 1100 return uart_resume_port(&stm32_usart_driver, port); 1101 } 1102 #endif /* CONFIG_PM_SLEEP */ 1103 1104 static const struct dev_pm_ops stm32_serial_pm_ops = { 1105 SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume) 1106 }; 1107 1108 static struct platform_driver stm32_serial_driver = { 1109 .probe = stm32_serial_probe, 1110 .remove = stm32_serial_remove, 1111 .driver = { 1112 .name = DRIVER_NAME, 1113 .pm = &stm32_serial_pm_ops, 1114 .of_match_table = of_match_ptr(stm32_match), 1115 }, 1116 }; 1117 1118 static int __init usart_init(void) 1119 { 1120 static char banner[] __initdata = "STM32 USART driver initialized"; 1121 int ret; 1122 1123 pr_info("%s\n", banner); 1124 1125 ret = uart_register_driver(&stm32_usart_driver); 1126 if (ret) 1127 return ret; 1128 1129 ret = platform_driver_register(&stm32_serial_driver); 1130 if (ret) 1131 uart_unregister_driver(&stm32_usart_driver); 1132 1133 return ret; 1134 } 1135 1136 static void __exit usart_exit(void) 1137 { 1138 platform_driver_unregister(&stm32_serial_driver); 1139 uart_unregister_driver(&stm32_usart_driver); 1140 } 1141 1142 module_init(usart_init); 1143 module_exit(usart_exit); 1144 1145 MODULE_ALIAS("platform:" DRIVER_NAME); 1146 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1147 MODULE_LICENSE("GPL v2"); 1148