stm32-usart.c (270e5a74fe4c78a857d65f1a129d3d77a36b8d58) stm32-usart.c (351a762aa8051960695a0f131731518e93b957fa)
1/*
2 * Copyright (C) Maxime Coquelin 2015
3 * Copyright (C) STMicroelectronics SA 2017
4 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
5 * Gerald Baeza <gerald.baeza@st.com>
6 * License terms: GNU General Public License (GPL), version 2
7 *
8 * Inspired by st-asc.c from STMicroelectronics (c)

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463 stm32_port->wakeirq);
464 if (ret) {
465 free_irq(port->irq, port);
466 return ret;
467 }
468 }
469
470 val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
1/*
2 * Copyright (C) Maxime Coquelin 2015
3 * Copyright (C) STMicroelectronics SA 2017
4 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
5 * Gerald Baeza <gerald.baeza@st.com>
6 * License terms: GNU General Public License (GPL), version 2
7 *
8 * Inspired by st-asc.c from STMicroelectronics (c)

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463 stm32_port->wakeirq);
464 if (ret) {
465 free_irq(port->irq, port);
466 return ret;
467 }
468 }
469
470 val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
471 if (stm32_port->fifoen)
472 val |= USART_CR1_FIFOEN;
471 stm32_set_bits(port, ofs->cr1, val);
472
473 return 0;
474}
475
476static void stm32_shutdown(struct uart_port *port)
477{
478 struct stm32_port *stm32_port = to_stm32_port(port);
479 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
480 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
481 u32 val;
482
483 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
484 val |= BIT(cfg->uart_enable_bit);
473 stm32_set_bits(port, ofs->cr1, val);
474
475 return 0;
476}
477
478static void stm32_shutdown(struct uart_port *port)
479{
480 struct stm32_port *stm32_port = to_stm32_port(port);
481 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
482 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
483 u32 val;
484
485 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
486 val |= BIT(cfg->uart_enable_bit);
487 if (stm32_port->fifoen)
488 val |= USART_CR1_FIFOEN;
485 stm32_clr_bits(port, ofs->cr1, val);
486
487 dev_pm_clear_wake_irq(port->dev);
488 free_irq(port->irq, port);
489}
490
491static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
492 struct ktermios *old)

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507
508 spin_lock_irqsave(&port->lock, flags);
509
510 /* Stop serial port and reset value */
511 writel_relaxed(0, port->membase + ofs->cr1);
512
513 cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
514 cr1 |= BIT(cfg->uart_enable_bit);
489 stm32_clr_bits(port, ofs->cr1, val);
490
491 dev_pm_clear_wake_irq(port->dev);
492 free_irq(port->irq, port);
493}
494
495static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
496 struct ktermios *old)

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511
512 spin_lock_irqsave(&port->lock, flags);
513
514 /* Stop serial port and reset value */
515 writel_relaxed(0, port->membase + ofs->cr1);
516
517 cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
518 cr1 |= BIT(cfg->uart_enable_bit);
519 if (stm32_port->fifoen)
520 cr1 |= USART_CR1_FIFOEN;
515 cr2 = 0;
516 cr3 = 0;
517
518 if (cflag & CSTOPB)
519 cr2 |= USART_CR2_STOP_2B;
520
521 if (cflag & PARENB) {
522 cr1 |= USART_CR1_PCE;

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671 int ret;
672
673 port->iotype = UPIO_MEM;
674 port->flags = UPF_BOOT_AUTOCONF;
675 port->ops = &stm32_uart_ops;
676 port->dev = &pdev->dev;
677 port->irq = platform_get_irq(pdev, 0);
678 stm32port->wakeirq = platform_get_irq(pdev, 1);
521 cr2 = 0;
522 cr3 = 0;
523
524 if (cflag & CSTOPB)
525 cr2 |= USART_CR2_STOP_2B;
526
527 if (cflag & PARENB) {
528 cr1 |= USART_CR1_PCE;

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677 int ret;
678
679 port->iotype = UPIO_MEM;
680 port->flags = UPF_BOOT_AUTOCONF;
681 port->ops = &stm32_uart_ops;
682 port->dev = &pdev->dev;
683 port->irq = platform_get_irq(pdev, 0);
684 stm32port->wakeirq = platform_get_irq(pdev, 1);
685 stm32port->fifoen = stm32port->info->cfg.has_fifo;
679
680 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
681 port->membase = devm_ioremap_resource(&pdev->dev, res);
682 if (IS_ERR(port->membase))
683 return PTR_ERR(port->membase);
684 port->mapbase = res->start;
685
686 spin_lock_init(&port->lock);

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687 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
688 port->membase = devm_ioremap_resource(&pdev->dev, res);
689 if (IS_ERR(port->membase))
690 return PTR_ERR(port->membase);
691 port->mapbase = res->start;
692
693 spin_lock_init(&port->lock);

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