stm32-usart.c (01d32d71610b0c56ce2c56bec370e275607a96e7) stm32-usart.c (87f1f809c9b90903e6a9ee0a8356a2303fd4270d)
1/*
2 * Copyright (C) Maxime Coquelin 2015
3 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * Gerald Baeza <gerald.baeza@st.com>
5 * License terms: GNU General Public License (GPL), version 2
6 *
7 * Inspired by st-asc.c from STMicroelectronics (c)
8 */

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456
457 return 0;
458}
459
460static void stm32_shutdown(struct uart_port *port)
461{
462 struct stm32_port *stm32_port = to_stm32_port(port);
463 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1/*
2 * Copyright (C) Maxime Coquelin 2015
3 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * Gerald Baeza <gerald.baeza@st.com>
5 * License terms: GNU General Public License (GPL), version 2
6 *
7 * Inspired by st-asc.c from STMicroelectronics (c)
8 */

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456
457 return 0;
458}
459
460static void stm32_shutdown(struct uart_port *port)
461{
462 struct stm32_port *stm32_port = to_stm32_port(port);
463 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
464 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
464 u32 val;
465
466 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
465 u32 val;
466
467 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
468 val |= BIT(cfg->uart_enable_bit);
467 stm32_clr_bits(port, ofs->cr1, val);
468
469 free_irq(port->irq, port);
470}
471
472static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
473 struct ktermios *old)
474{

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918 writel_relaxed(ch, port->membase + ofs->tdr);
919}
920
921static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
922{
923 struct uart_port *port = &stm32_ports[co->index].port;
924 struct stm32_port *stm32_port = to_stm32_port(port);
925 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
469 stm32_clr_bits(port, ofs->cr1, val);
470
471 free_irq(port->irq, port);
472}
473
474static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
475 struct ktermios *old)
476{

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920 writel_relaxed(ch, port->membase + ofs->tdr);
921}
922
923static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
924{
925 struct uart_port *port = &stm32_ports[co->index].port;
926 struct stm32_port *stm32_port = to_stm32_port(port);
927 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
928 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
926 unsigned long flags;
927 u32 old_cr1, new_cr1;
928 int locked = 1;
929
930 local_irq_save(flags);
931 if (port->sysrq)
932 locked = 0;
933 else if (oops_in_progress)
934 locked = spin_trylock(&port->lock);
935 else
936 spin_lock(&port->lock);
937
929 unsigned long flags;
930 u32 old_cr1, new_cr1;
931 int locked = 1;
932
933 local_irq_save(flags);
934 if (port->sysrq)
935 locked = 0;
936 else if (oops_in_progress)
937 locked = spin_trylock(&port->lock);
938 else
939 spin_lock(&port->lock);
940
938 /* Save and disable interrupts */
941 /* Save and disable interrupts, enable the transmitter */
939 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
940 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
942 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
943 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
944 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
941 writel_relaxed(new_cr1, port->membase + ofs->cr1);
942
943 uart_console_write(port, s, cnt, stm32_console_putchar);
944
945 /* Restore interrupt state */
946 writel_relaxed(old_cr1, port->membase + ofs->cr1);
947
948 if (locked)

--- 96 unchanged lines hidden --- 		945 writel_relaxed(new_cr1, port->membase + ofs->cr1);
946
947 uart_console_write(port, s, cnt, stm32_console_putchar);
948
949 /* Restore interrupt state */
950 writel_relaxed(old_cr1, port->membase + ofs->cr1);
951
952 if (locked)

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