1 /* 2 * Copyright (C) Maxime Coquelin 2015 3 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 4 * Gerald Baeza <gerald.baeza@st.com> 5 * License terms: GNU General Public License (GPL), version 2 6 * 7 * Inspired by st-asc.c from STMicroelectronics (c) 8 */ 9 10 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 11 #define SUPPORT_SYSRQ 12 #endif 13 14 #include <linux/clk.h> 15 #include <linux/console.h> 16 #include <linux/delay.h> 17 #include <linux/dma-direction.h> 18 #include <linux/dmaengine.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/io.h> 21 #include <linux/iopoll.h> 22 #include <linux/irq.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_platform.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/spinlock.h> 31 #include <linux/sysrq.h> 32 #include <linux/tty_flip.h> 33 #include <linux/tty.h> 34 35 #include "stm32-usart.h" 36 37 static void stm32_stop_tx(struct uart_port *port); 38 static void stm32_transmit_chars(struct uart_port *port); 39 40 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 41 { 42 return container_of(port, struct stm32_port, port); 43 } 44 45 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits) 46 { 47 u32 val; 48 49 val = readl_relaxed(port->membase + reg); 50 val |= bits; 51 writel_relaxed(val, port->membase + reg); 52 } 53 54 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits) 55 { 56 u32 val; 57 58 val = readl_relaxed(port->membase + reg); 59 val &= ~bits; 60 writel_relaxed(val, port->membase + reg); 61 } 62 63 int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res, 64 bool threaded) 65 { 66 struct stm32_port *stm32_port = to_stm32_port(port); 67 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 68 enum dma_status status; 69 struct dma_tx_state state; 70 71 *sr = readl_relaxed(port->membase + ofs->isr); 72 73 if (threaded && stm32_port->rx_ch) { 74 status = dmaengine_tx_status(stm32_port->rx_ch, 75 stm32_port->rx_ch->cookie, 76 &state); 77 if ((status == DMA_IN_PROGRESS) && 78 (*last_res != state.residue)) 79 return 1; 80 else 81 return 0; 82 } else if (*sr & USART_SR_RXNE) { 83 return 1; 84 } 85 return 0; 86 } 87 88 unsigned long stm32_get_char(struct uart_port *port, u32 *sr, int *last_res) 89 { 90 struct stm32_port *stm32_port = to_stm32_port(port); 91 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 92 unsigned long c; 93 94 if (stm32_port->rx_ch) { 95 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 96 if ((*last_res) == 0) 97 *last_res = RX_BUF_L; 98 return c; 99 } else { 100 return readl_relaxed(port->membase + ofs->rdr); 101 } 102 } 103 104 static void stm32_receive_chars(struct uart_port *port, bool threaded) 105 { 106 struct tty_port *tport = &port->state->port; 107 struct stm32_port *stm32_port = to_stm32_port(port); 108 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 109 unsigned long c; 110 u32 sr; 111 char flag; 112 static int last_res = RX_BUF_L; 113 114 if (port->irq_wake) 115 pm_wakeup_event(tport->tty->dev, 0); 116 117 while (stm32_pending_rx(port, &sr, &last_res, threaded)) { 118 sr |= USART_SR_DUMMY_RX; 119 c = stm32_get_char(port, &sr, &last_res); 120 flag = TTY_NORMAL; 121 port->icount.rx++; 122 123 if (sr & USART_SR_ERR_MASK) { 124 if (sr & USART_SR_LBD) { 125 port->icount.brk++; 126 if (uart_handle_break(port)) 127 continue; 128 } else if (sr & USART_SR_ORE) { 129 if (ofs->icr != UNDEF_REG) 130 writel_relaxed(USART_ICR_ORECF, 131 port->membase + 132 ofs->icr); 133 port->icount.overrun++; 134 } else if (sr & USART_SR_PE) { 135 port->icount.parity++; 136 } else if (sr & USART_SR_FE) { 137 port->icount.frame++; 138 } 139 140 sr &= port->read_status_mask; 141 142 if (sr & USART_SR_LBD) 143 flag = TTY_BREAK; 144 else if (sr & USART_SR_PE) 145 flag = TTY_PARITY; 146 else if (sr & USART_SR_FE) 147 flag = TTY_FRAME; 148 } 149 150 if (uart_handle_sysrq_char(port, c)) 151 continue; 152 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 153 } 154 155 spin_unlock(&port->lock); 156 tty_flip_buffer_push(tport); 157 spin_lock(&port->lock); 158 } 159 160 static void stm32_tx_dma_complete(void *arg) 161 { 162 struct uart_port *port = arg; 163 struct stm32_port *stm32port = to_stm32_port(port); 164 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 165 unsigned int isr; 166 int ret; 167 168 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 169 isr, 170 (isr & USART_SR_TC), 171 10, 100000); 172 173 if (ret) 174 dev_err(port->dev, "terminal count not set\n"); 175 176 if (ofs->icr == UNDEF_REG) 177 stm32_clr_bits(port, ofs->isr, USART_SR_TC); 178 else 179 stm32_set_bits(port, ofs->icr, USART_CR_TC); 180 181 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 182 stm32port->tx_dma_busy = false; 183 184 /* Let's see if we have pending data to send */ 185 stm32_transmit_chars(port); 186 } 187 188 static void stm32_transmit_chars_pio(struct uart_port *port) 189 { 190 struct stm32_port *stm32_port = to_stm32_port(port); 191 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 192 struct circ_buf *xmit = &port->state->xmit; 193 unsigned int isr; 194 int ret; 195 196 if (stm32_port->tx_dma_busy) { 197 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 198 stm32_port->tx_dma_busy = false; 199 } 200 201 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 202 isr, 203 (isr & USART_SR_TXE), 204 10, 100); 205 206 if (ret) 207 dev_err(port->dev, "tx empty not set\n"); 208 209 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 210 211 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 212 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 213 port->icount.tx++; 214 } 215 216 static void stm32_transmit_chars_dma(struct uart_port *port) 217 { 218 struct stm32_port *stm32port = to_stm32_port(port); 219 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 220 struct circ_buf *xmit = &port->state->xmit; 221 struct dma_async_tx_descriptor *desc = NULL; 222 dma_cookie_t cookie; 223 unsigned int count, i; 224 225 if (stm32port->tx_dma_busy) 226 return; 227 228 stm32port->tx_dma_busy = true; 229 230 count = uart_circ_chars_pending(xmit); 231 232 if (count > TX_BUF_L) 233 count = TX_BUF_L; 234 235 if (xmit->tail < xmit->head) { 236 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 237 } else { 238 size_t one = UART_XMIT_SIZE - xmit->tail; 239 size_t two; 240 241 if (one > count) 242 one = count; 243 two = count - one; 244 245 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 246 if (two) 247 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 248 } 249 250 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 251 stm32port->tx_dma_buf, 252 count, 253 DMA_MEM_TO_DEV, 254 DMA_PREP_INTERRUPT); 255 256 if (!desc) { 257 for (i = count; i > 0; i--) 258 stm32_transmit_chars_pio(port); 259 return; 260 } 261 262 desc->callback = stm32_tx_dma_complete; 263 desc->callback_param = port; 264 265 /* Push current DMA TX transaction in the pending queue */ 266 cookie = dmaengine_submit(desc); 267 268 /* Issue pending DMA TX requests */ 269 dma_async_issue_pending(stm32port->tx_ch); 270 271 stm32_clr_bits(port, ofs->isr, USART_SR_TC); 272 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 273 274 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 275 port->icount.tx += count; 276 } 277 278 static void stm32_transmit_chars(struct uart_port *port) 279 { 280 struct stm32_port *stm32_port = to_stm32_port(port); 281 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 282 struct circ_buf *xmit = &port->state->xmit; 283 284 if (port->x_char) { 285 if (stm32_port->tx_dma_busy) 286 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 287 writel_relaxed(port->x_char, port->membase + ofs->tdr); 288 port->x_char = 0; 289 port->icount.tx++; 290 if (stm32_port->tx_dma_busy) 291 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 292 return; 293 } 294 295 if (uart_tx_stopped(port)) { 296 stm32_stop_tx(port); 297 return; 298 } 299 300 if (uart_circ_empty(xmit)) { 301 stm32_stop_tx(port); 302 return; 303 } 304 305 if (stm32_port->tx_ch) 306 stm32_transmit_chars_dma(port); 307 else 308 stm32_transmit_chars_pio(port); 309 310 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 311 uart_write_wakeup(port); 312 313 if (uart_circ_empty(xmit)) 314 stm32_stop_tx(port); 315 } 316 317 static irqreturn_t stm32_interrupt(int irq, void *ptr) 318 { 319 struct uart_port *port = ptr; 320 struct stm32_port *stm32_port = to_stm32_port(port); 321 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 322 u32 sr; 323 324 spin_lock(&port->lock); 325 326 sr = readl_relaxed(port->membase + ofs->isr); 327 328 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 329 stm32_receive_chars(port, false); 330 331 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) 332 stm32_transmit_chars(port); 333 334 spin_unlock(&port->lock); 335 336 if (stm32_port->rx_ch) 337 return IRQ_WAKE_THREAD; 338 else 339 return IRQ_HANDLED; 340 } 341 342 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr) 343 { 344 struct uart_port *port = ptr; 345 struct stm32_port *stm32_port = to_stm32_port(port); 346 347 spin_lock(&port->lock); 348 349 if (stm32_port->rx_ch) 350 stm32_receive_chars(port, true); 351 352 spin_unlock(&port->lock); 353 354 return IRQ_HANDLED; 355 } 356 357 static unsigned int stm32_tx_empty(struct uart_port *port) 358 { 359 struct stm32_port *stm32_port = to_stm32_port(port); 360 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 361 362 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 363 } 364 365 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl) 366 { 367 struct stm32_port *stm32_port = to_stm32_port(port); 368 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 369 370 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 371 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE); 372 else 373 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 374 } 375 376 static unsigned int stm32_get_mctrl(struct uart_port *port) 377 { 378 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 379 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 380 } 381 382 /* Transmit stop */ 383 static void stm32_stop_tx(struct uart_port *port) 384 { 385 struct stm32_port *stm32_port = to_stm32_port(port); 386 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 387 388 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 389 } 390 391 /* There are probably characters waiting to be transmitted. */ 392 static void stm32_start_tx(struct uart_port *port) 393 { 394 struct circ_buf *xmit = &port->state->xmit; 395 396 if (uart_circ_empty(xmit)) 397 return; 398 399 stm32_transmit_chars(port); 400 } 401 402 /* Throttle the remote when input buffer is about to overflow. */ 403 static void stm32_throttle(struct uart_port *port) 404 { 405 struct stm32_port *stm32_port = to_stm32_port(port); 406 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 407 unsigned long flags; 408 409 spin_lock_irqsave(&port->lock, flags); 410 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); 411 spin_unlock_irqrestore(&port->lock, flags); 412 } 413 414 /* Unthrottle the remote, the input buffer can now accept data. */ 415 static void stm32_unthrottle(struct uart_port *port) 416 { 417 struct stm32_port *stm32_port = to_stm32_port(port); 418 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 419 unsigned long flags; 420 421 spin_lock_irqsave(&port->lock, flags); 422 stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE); 423 spin_unlock_irqrestore(&port->lock, flags); 424 } 425 426 /* Receive stop */ 427 static void stm32_stop_rx(struct uart_port *port) 428 { 429 struct stm32_port *stm32_port = to_stm32_port(port); 430 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 431 432 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); 433 } 434 435 /* Handle breaks - ignored by us */ 436 static void stm32_break_ctl(struct uart_port *port, int break_state) 437 { 438 } 439 440 static int stm32_startup(struct uart_port *port) 441 { 442 struct stm32_port *stm32_port = to_stm32_port(port); 443 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 444 const char *name = to_platform_device(port->dev)->name; 445 u32 val; 446 int ret; 447 448 ret = request_threaded_irq(port->irq, stm32_interrupt, 449 stm32_threaded_interrupt, 450 IRQF_NO_SUSPEND, name, port); 451 if (ret) 452 return ret; 453 454 val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; 455 stm32_set_bits(port, ofs->cr1, val); 456 457 return 0; 458 } 459 460 static void stm32_shutdown(struct uart_port *port) 461 { 462 struct stm32_port *stm32_port = to_stm32_port(port); 463 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 464 u32 val; 465 466 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; 467 stm32_clr_bits(port, ofs->cr1, val); 468 469 free_irq(port->irq, port); 470 } 471 472 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, 473 struct ktermios *old) 474 { 475 struct stm32_port *stm32_port = to_stm32_port(port); 476 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 477 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 478 unsigned int baud; 479 u32 usartdiv, mantissa, fraction, oversampling; 480 tcflag_t cflag = termios->c_cflag; 481 u32 cr1, cr2, cr3; 482 unsigned long flags; 483 484 if (!stm32_port->hw_flow_control) 485 cflag &= ~CRTSCTS; 486 487 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 488 489 spin_lock_irqsave(&port->lock, flags); 490 491 /* Stop serial port and reset value */ 492 writel_relaxed(0, port->membase + ofs->cr1); 493 494 cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE; 495 cr1 |= BIT(cfg->uart_enable_bit); 496 cr2 = 0; 497 cr3 = 0; 498 499 if (cflag & CSTOPB) 500 cr2 |= USART_CR2_STOP_2B; 501 502 if (cflag & PARENB) { 503 cr1 |= USART_CR1_PCE; 504 if ((cflag & CSIZE) == CS8) { 505 if (cfg->has_7bits_data) 506 cr1 |= USART_CR1_M0; 507 else 508 cr1 |= USART_CR1_M; 509 } 510 } 511 512 if (cflag & PARODD) 513 cr1 |= USART_CR1_PS; 514 515 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 516 if (cflag & CRTSCTS) { 517 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 518 cr3 |= USART_CR3_CTSE; 519 } 520 521 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 522 523 /* 524 * The USART supports 16 or 8 times oversampling. 525 * By default we prefer 16 times oversampling, so that the receiver 526 * has a better tolerance to clock deviations. 527 * 8 times oversampling is only used to achieve higher speeds. 528 */ 529 if (usartdiv < 16) { 530 oversampling = 8; 531 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8); 532 } else { 533 oversampling = 16; 534 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 535 } 536 537 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 538 fraction = usartdiv % oversampling; 539 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 540 541 uart_update_timeout(port, cflag, baud); 542 543 port->read_status_mask = USART_SR_ORE; 544 if (termios->c_iflag & INPCK) 545 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 546 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 547 port->read_status_mask |= USART_SR_LBD; 548 549 /* Characters to ignore */ 550 port->ignore_status_mask = 0; 551 if (termios->c_iflag & IGNPAR) 552 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 553 if (termios->c_iflag & IGNBRK) { 554 port->ignore_status_mask |= USART_SR_LBD; 555 /* 556 * If we're ignoring parity and break indicators, 557 * ignore overruns too (for real raw support). 558 */ 559 if (termios->c_iflag & IGNPAR) 560 port->ignore_status_mask |= USART_SR_ORE; 561 } 562 563 /* Ignore all characters if CREAD is not set */ 564 if ((termios->c_cflag & CREAD) == 0) 565 port->ignore_status_mask |= USART_SR_DUMMY_RX; 566 567 if (stm32_port->rx_ch) 568 cr3 |= USART_CR3_DMAR; 569 570 writel_relaxed(cr3, port->membase + ofs->cr3); 571 writel_relaxed(cr2, port->membase + ofs->cr2); 572 writel_relaxed(cr1, port->membase + ofs->cr1); 573 574 spin_unlock_irqrestore(&port->lock, flags); 575 } 576 577 static const char *stm32_type(struct uart_port *port) 578 { 579 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 580 } 581 582 static void stm32_release_port(struct uart_port *port) 583 { 584 } 585 586 static int stm32_request_port(struct uart_port *port) 587 { 588 return 0; 589 } 590 591 static void stm32_config_port(struct uart_port *port, int flags) 592 { 593 if (flags & UART_CONFIG_TYPE) 594 port->type = PORT_STM32; 595 } 596 597 static int 598 stm32_verify_port(struct uart_port *port, struct serial_struct *ser) 599 { 600 /* No user changeable parameters */ 601 return -EINVAL; 602 } 603 604 static void stm32_pm(struct uart_port *port, unsigned int state, 605 unsigned int oldstate) 606 { 607 struct stm32_port *stm32port = container_of(port, 608 struct stm32_port, port); 609 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 610 struct stm32_usart_config *cfg = &stm32port->info->cfg; 611 unsigned long flags = 0; 612 613 switch (state) { 614 case UART_PM_STATE_ON: 615 clk_prepare_enable(stm32port->clk); 616 break; 617 case UART_PM_STATE_OFF: 618 spin_lock_irqsave(&port->lock, flags); 619 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 620 spin_unlock_irqrestore(&port->lock, flags); 621 clk_disable_unprepare(stm32port->clk); 622 break; 623 } 624 } 625 626 static const struct uart_ops stm32_uart_ops = { 627 .tx_empty = stm32_tx_empty, 628 .set_mctrl = stm32_set_mctrl, 629 .get_mctrl = stm32_get_mctrl, 630 .stop_tx = stm32_stop_tx, 631 .start_tx = stm32_start_tx, 632 .throttle = stm32_throttle, 633 .unthrottle = stm32_unthrottle, 634 .stop_rx = stm32_stop_rx, 635 .break_ctl = stm32_break_ctl, 636 .startup = stm32_startup, 637 .shutdown = stm32_shutdown, 638 .set_termios = stm32_set_termios, 639 .pm = stm32_pm, 640 .type = stm32_type, 641 .release_port = stm32_release_port, 642 .request_port = stm32_request_port, 643 .config_port = stm32_config_port, 644 .verify_port = stm32_verify_port, 645 }; 646 647 static int stm32_init_port(struct stm32_port *stm32port, 648 struct platform_device *pdev) 649 { 650 struct uart_port *port = &stm32port->port; 651 struct resource *res; 652 int ret; 653 654 port->iotype = UPIO_MEM; 655 port->flags = UPF_BOOT_AUTOCONF; 656 port->ops = &stm32_uart_ops; 657 port->dev = &pdev->dev; 658 port->irq = platform_get_irq(pdev, 0); 659 660 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 661 port->membase = devm_ioremap_resource(&pdev->dev, res); 662 if (IS_ERR(port->membase)) 663 return PTR_ERR(port->membase); 664 port->mapbase = res->start; 665 666 spin_lock_init(&port->lock); 667 668 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 669 if (IS_ERR(stm32port->clk)) 670 return PTR_ERR(stm32port->clk); 671 672 /* Ensure that clk rate is correct by enabling the clk */ 673 ret = clk_prepare_enable(stm32port->clk); 674 if (ret) 675 return ret; 676 677 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 678 if (!stm32port->port.uartclk) 679 ret = -EINVAL; 680 681 return ret; 682 } 683 684 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev) 685 { 686 struct device_node *np = pdev->dev.of_node; 687 int id; 688 689 if (!np) 690 return NULL; 691 692 id = of_alias_get_id(np, "serial"); 693 if (id < 0) 694 id = 0; 695 696 if (WARN_ON(id >= STM32_MAX_PORTS)) 697 return NULL; 698 699 stm32_ports[id].hw_flow_control = of_property_read_bool(np, 700 "st,hw-flow-ctrl"); 701 stm32_ports[id].port.line = id; 702 return &stm32_ports[id]; 703 } 704 705 #ifdef CONFIG_OF 706 static const struct of_device_id stm32_match[] = { 707 { .compatible = "st,stm32-usart", .data = &stm32f4_info}, 708 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 709 { .compatible = "st,stm32f7-usart", .data = &stm32f7_info}, 710 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 711 {}, 712 }; 713 714 MODULE_DEVICE_TABLE(of, stm32_match); 715 #endif 716 717 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port, 718 struct platform_device *pdev) 719 { 720 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 721 struct uart_port *port = &stm32port->port; 722 struct device *dev = &pdev->dev; 723 struct dma_slave_config config; 724 struct dma_async_tx_descriptor *desc = NULL; 725 dma_cookie_t cookie; 726 int ret; 727 728 /* Request DMA RX channel */ 729 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 730 if (!stm32port->rx_ch) { 731 dev_info(dev, "rx dma alloc failed\n"); 732 return -ENODEV; 733 } 734 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 735 &stm32port->rx_dma_buf, 736 GFP_KERNEL); 737 if (!stm32port->rx_buf) { 738 ret = -ENOMEM; 739 goto alloc_err; 740 } 741 742 /* Configure DMA channel */ 743 memset(&config, 0, sizeof(config)); 744 config.src_addr = (dma_addr_t)port->membase + ofs->rdr; 745 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 746 747 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 748 if (ret < 0) { 749 dev_err(dev, "rx dma channel config failed\n"); 750 ret = -ENODEV; 751 goto config_err; 752 } 753 754 /* Prepare a DMA cyclic transaction */ 755 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 756 stm32port->rx_dma_buf, 757 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 758 DMA_PREP_INTERRUPT); 759 if (!desc) { 760 dev_err(dev, "rx dma prep cyclic failed\n"); 761 ret = -ENODEV; 762 goto config_err; 763 } 764 765 /* No callback as dma buffer is drained on usart interrupt */ 766 desc->callback = NULL; 767 desc->callback_param = NULL; 768 769 /* Push current DMA transaction in the pending queue */ 770 cookie = dmaengine_submit(desc); 771 772 /* Issue pending DMA requests */ 773 dma_async_issue_pending(stm32port->rx_ch); 774 775 return 0; 776 777 config_err: 778 dma_free_coherent(&pdev->dev, 779 RX_BUF_L, stm32port->rx_buf, 780 stm32port->rx_dma_buf); 781 782 alloc_err: 783 dma_release_channel(stm32port->rx_ch); 784 stm32port->rx_ch = NULL; 785 786 return ret; 787 } 788 789 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port, 790 struct platform_device *pdev) 791 { 792 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 793 struct uart_port *port = &stm32port->port; 794 struct device *dev = &pdev->dev; 795 struct dma_slave_config config; 796 int ret; 797 798 stm32port->tx_dma_busy = false; 799 800 /* Request DMA TX channel */ 801 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 802 if (!stm32port->tx_ch) { 803 dev_info(dev, "tx dma alloc failed\n"); 804 return -ENODEV; 805 } 806 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 807 &stm32port->tx_dma_buf, 808 GFP_KERNEL); 809 if (!stm32port->tx_buf) { 810 ret = -ENOMEM; 811 goto alloc_err; 812 } 813 814 /* Configure DMA channel */ 815 memset(&config, 0, sizeof(config)); 816 config.dst_addr = (dma_addr_t)port->membase + ofs->tdr; 817 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 818 819 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 820 if (ret < 0) { 821 dev_err(dev, "tx dma channel config failed\n"); 822 ret = -ENODEV; 823 goto config_err; 824 } 825 826 return 0; 827 828 config_err: 829 dma_free_coherent(&pdev->dev, 830 TX_BUF_L, stm32port->tx_buf, 831 stm32port->tx_dma_buf); 832 833 alloc_err: 834 dma_release_channel(stm32port->tx_ch); 835 stm32port->tx_ch = NULL; 836 837 return ret; 838 } 839 840 static int stm32_serial_probe(struct platform_device *pdev) 841 { 842 const struct of_device_id *match; 843 struct stm32_port *stm32port; 844 int ret; 845 846 stm32port = stm32_of_get_stm32_port(pdev); 847 if (!stm32port) 848 return -ENODEV; 849 850 match = of_match_device(stm32_match, &pdev->dev); 851 if (match && match->data) 852 stm32port->info = (struct stm32_usart_info *)match->data; 853 else 854 return -EINVAL; 855 856 ret = stm32_init_port(stm32port, pdev); 857 if (ret) 858 return ret; 859 860 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 861 if (ret) 862 return ret; 863 864 ret = stm32_of_dma_rx_probe(stm32port, pdev); 865 if (ret) 866 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 867 868 ret = stm32_of_dma_tx_probe(stm32port, pdev); 869 if (ret) 870 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 871 872 platform_set_drvdata(pdev, &stm32port->port); 873 874 return 0; 875 } 876 877 static int stm32_serial_remove(struct platform_device *pdev) 878 { 879 struct uart_port *port = platform_get_drvdata(pdev); 880 struct stm32_port *stm32_port = to_stm32_port(port); 881 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 882 883 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 884 885 if (stm32_port->rx_ch) 886 dma_release_channel(stm32_port->rx_ch); 887 888 if (stm32_port->rx_dma_buf) 889 dma_free_coherent(&pdev->dev, 890 RX_BUF_L, stm32_port->rx_buf, 891 stm32_port->rx_dma_buf); 892 893 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 894 895 if (stm32_port->tx_ch) 896 dma_release_channel(stm32_port->tx_ch); 897 898 if (stm32_port->tx_dma_buf) 899 dma_free_coherent(&pdev->dev, 900 TX_BUF_L, stm32_port->tx_buf, 901 stm32_port->tx_dma_buf); 902 903 clk_disable_unprepare(stm32_port->clk); 904 905 return uart_remove_one_port(&stm32_usart_driver, port); 906 } 907 908 909 #ifdef CONFIG_SERIAL_STM32_CONSOLE 910 static void stm32_console_putchar(struct uart_port *port, int ch) 911 { 912 struct stm32_port *stm32_port = to_stm32_port(port); 913 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 914 915 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 916 cpu_relax(); 917 918 writel_relaxed(ch, port->membase + ofs->tdr); 919 } 920 921 static void stm32_console_write(struct console *co, const char *s, unsigned cnt) 922 { 923 struct uart_port *port = &stm32_ports[co->index].port; 924 struct stm32_port *stm32_port = to_stm32_port(port); 925 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 926 unsigned long flags; 927 u32 old_cr1, new_cr1; 928 int locked = 1; 929 930 local_irq_save(flags); 931 if (port->sysrq) 932 locked = 0; 933 else if (oops_in_progress) 934 locked = spin_trylock(&port->lock); 935 else 936 spin_lock(&port->lock); 937 938 /* Save and disable interrupts */ 939 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 940 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 941 writel_relaxed(new_cr1, port->membase + ofs->cr1); 942 943 uart_console_write(port, s, cnt, stm32_console_putchar); 944 945 /* Restore interrupt state */ 946 writel_relaxed(old_cr1, port->membase + ofs->cr1); 947 948 if (locked) 949 spin_unlock(&port->lock); 950 local_irq_restore(flags); 951 } 952 953 static int stm32_console_setup(struct console *co, char *options) 954 { 955 struct stm32_port *stm32port; 956 int baud = 9600; 957 int bits = 8; 958 int parity = 'n'; 959 int flow = 'n'; 960 961 if (co->index >= STM32_MAX_PORTS) 962 return -ENODEV; 963 964 stm32port = &stm32_ports[co->index]; 965 966 /* 967 * This driver does not support early console initialization 968 * (use ARM early printk support instead), so we only expect 969 * this to be called during the uart port registration when the 970 * driver gets probed and the port should be mapped at that point. 971 */ 972 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL) 973 return -ENXIO; 974 975 if (options) 976 uart_parse_options(options, &baud, &parity, &bits, &flow); 977 978 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 979 } 980 981 static struct console stm32_console = { 982 .name = STM32_SERIAL_NAME, 983 .device = uart_console_device, 984 .write = stm32_console_write, 985 .setup = stm32_console_setup, 986 .flags = CON_PRINTBUFFER, 987 .index = -1, 988 .data = &stm32_usart_driver, 989 }; 990 991 #define STM32_SERIAL_CONSOLE (&stm32_console) 992 993 #else 994 #define STM32_SERIAL_CONSOLE NULL 995 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 996 997 static struct uart_driver stm32_usart_driver = { 998 .driver_name = DRIVER_NAME, 999 .dev_name = STM32_SERIAL_NAME, 1000 .major = 0, 1001 .minor = 0, 1002 .nr = STM32_MAX_PORTS, 1003 .cons = STM32_SERIAL_CONSOLE, 1004 }; 1005 1006 static struct platform_driver stm32_serial_driver = { 1007 .probe = stm32_serial_probe, 1008 .remove = stm32_serial_remove, 1009 .driver = { 1010 .name = DRIVER_NAME, 1011 .of_match_table = of_match_ptr(stm32_match), 1012 }, 1013 }; 1014 1015 static int __init usart_init(void) 1016 { 1017 static char banner[] __initdata = "STM32 USART driver initialized"; 1018 int ret; 1019 1020 pr_info("%s\n", banner); 1021 1022 ret = uart_register_driver(&stm32_usart_driver); 1023 if (ret) 1024 return ret; 1025 1026 ret = platform_driver_register(&stm32_serial_driver); 1027 if (ret) 1028 uart_unregister_driver(&stm32_usart_driver); 1029 1030 return ret; 1031 } 1032 1033 static void __exit usart_exit(void) 1034 { 1035 platform_driver_unregister(&stm32_serial_driver); 1036 uart_unregister_driver(&stm32_usart_driver); 1037 } 1038 1039 module_init(usart_init); 1040 module_exit(usart_exit); 1041 1042 MODULE_ALIAS("platform:" DRIVER_NAME); 1043 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1044 MODULE_LICENSE("GPL v2"); 1045