| spi-sun6i.c (794912cff6dba8b5e93948243299bb0b2cb11277) | spi-sun6i.c (719bd6542044efd9b338a53dba1bef45f40ca169) |
|---|---|
| 1/* 2 * Copyright (C) 2012 - 2014 Allwinner Tech 3 * Pan Nan <pannan@allwinnertech.com> 4 * 5 * Copyright (C) 2014 Maxime Ripard 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or --- 139 unchanged lines hidden (view full) --- 148 if (enable) 149 reg |= SUN6I_TFR_CTL_CS_LEVEL; 150 else 151 reg &= ~SUN6I_TFR_CTL_CS_LEVEL; 152 153 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 154} 155 | 1/* 2 * Copyright (C) 2012 - 2014 Allwinner Tech 3 * Pan Nan <pannan@allwinnertech.com> 4 * 5 * Copyright (C) 2014 Maxime Ripard 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or --- 139 unchanged lines hidden (view full) --- 148 if (enable) 149 reg |= SUN6I_TFR_CTL_CS_LEVEL; 150 else 151 reg &= ~SUN6I_TFR_CTL_CS_LEVEL; 152 153 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 154} 155 |
| 156static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) 157{ 158 return SUN6I_FIFO_DEPTH - 1; 159} | |
| 160 161static int sun6i_spi_transfer_one(struct spi_master *master, 162 struct spi_device *spi, 163 struct spi_transfer *tfr) 164{ 165 struct sun6i_spi *sspi = spi_master_get_devdata(master); 166 unsigned int mclk_rate, div, timeout; | 156 157static int sun6i_spi_transfer_one(struct spi_master *master, 158 struct spi_device *spi, 159 struct spi_transfer *tfr) 160{ 161 struct sun6i_spi *sspi = spi_master_get_devdata(master); 162 unsigned int mclk_rate, div, timeout; |
| 163 unsigned int start, end, tx_time; |
|
| 167 unsigned int tx_len = 0; 168 int ret = 0; 169 u32 reg; 170 171 /* We don't support transfer larger than the FIFO */ 172 if (tfr->len > SUN6I_FIFO_DEPTH) 173 return -EINVAL; 174 --- 93 unchanged lines hidden (view full) --- 268 269 /* Enable the interrupts */ 270 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC); 271 272 /* Start the transfer */ 273 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 274 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH); 275 | 164 unsigned int tx_len = 0; 165 int ret = 0; 166 u32 reg; 167 168 /* We don't support transfer larger than the FIFO */ 169 if (tfr->len > SUN6I_FIFO_DEPTH) 170 return -EINVAL; 171 --- 93 unchanged lines hidden (view full) --- 265 266 /* Enable the interrupts */ 267 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC); 268 269 /* Start the transfer */ 270 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 271 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH); 272 |
| 273 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); 274 start = jiffies; |
|
| 276 timeout = wait_for_completion_timeout(&sspi->done, | 275 timeout = wait_for_completion_timeout(&sspi->done, |
| 277 msecs_to_jiffies(1000)); | 276 msecs_to_jiffies(tx_time)); 277 end = jiffies; |
| 278 if (!timeout) { | 278 if (!timeout) { |
| 279 dev_warn(&master->dev, 280 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms", 281 dev_name(&spi->dev), tfr->len, tfr->speed_hz, 282 jiffies_to_msecs(end - start), tx_time); |
|
| 279 ret = -ETIMEDOUT; 280 goto out; 281 } 282 283 sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH); 284 285out: 286 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); --- 105 unchanged lines hidden (view full) --- 392 sspi->master = master; 393 master->set_cs = sun6i_spi_set_cs; 394 master->transfer_one = sun6i_spi_transfer_one; 395 master->num_chipselect = 4; 396 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; 397 master->bits_per_word_mask = SPI_BPW_MASK(8); 398 master->dev.of_node = pdev->dev.of_node; 399 master->auto_runtime_pm = true; | 283 ret = -ETIMEDOUT; 284 goto out; 285 } 286 287 sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH); 288 289out: 290 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); --- 105 unchanged lines hidden (view full) --- 396 sspi->master = master; 397 master->set_cs = sun6i_spi_set_cs; 398 master->transfer_one = sun6i_spi_transfer_one; 399 master->num_chipselect = 4; 400 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; 401 master->bits_per_word_mask = SPI_BPW_MASK(8); 402 master->dev.of_node = pdev->dev.of_node; 403 master->auto_runtime_pm = true; |
| 400 master->max_transfer_size = sun6i_spi_max_transfer_size; | |
| 401 402 sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); 403 if (IS_ERR(sspi->hclk)) { 404 dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); 405 ret = PTR_ERR(sspi->hclk); 406 goto err_free_master; 407 } 408 --- 79 unchanged lines hidden --- | 404 405 sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); 406 if (IS_ERR(sspi->hclk)) { 407 dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); 408 ret = PTR_ERR(sspi->hclk); 409 goto err_free_master; 410 } 411 --- 79 unchanged lines hidden --- |