| spi-sun4i.c (6d9fe44bd73d567d04d3a68a2d2fa521ab9532f2) | spi-sun4i.c (719bd6542044efd9b338a53dba1bef45f40ca169) |
|---|---|
| 1/* 2 * Copyright (C) 2012 - 2014 Allwinner Tech 3 * Pan Nan <pannan@allwinnertech.com> 4 * 5 * Copyright (C) 2014 Maxime Ripard 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or --- 159 unchanged lines hidden (view full) --- 168} 169 170static int sun4i_spi_transfer_one(struct spi_master *master, 171 struct spi_device *spi, 172 struct spi_transfer *tfr) 173{ 174 struct sun4i_spi *sspi = spi_master_get_devdata(master); 175 unsigned int mclk_rate, div, timeout; | 1/* 2 * Copyright (C) 2012 - 2014 Allwinner Tech 3 * Pan Nan <pannan@allwinnertech.com> 4 * 5 * Copyright (C) 2014 Maxime Ripard 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or --- 159 unchanged lines hidden (view full) --- 168} 169 170static int sun4i_spi_transfer_one(struct spi_master *master, 171 struct spi_device *spi, 172 struct spi_transfer *tfr) 173{ 174 struct sun4i_spi *sspi = spi_master_get_devdata(master); 175 unsigned int mclk_rate, div, timeout; |
| 176 unsigned int start, end, tx_time; |
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| 176 unsigned int tx_len = 0; 177 int ret = 0; 178 u32 reg; 179 180 /* We don't support transfer larger than the FIFO */ 181 if (tfr->len > SUN4I_FIFO_DEPTH) 182 return -EMSGSIZE; 183 --- 97 unchanged lines hidden (view full) --- 281 282 /* Enable the interrupts */ 283 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC); 284 285 /* Start the transfer */ 286 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); 287 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH); 288 | 177 unsigned int tx_len = 0; 178 int ret = 0; 179 u32 reg; 180 181 /* We don't support transfer larger than the FIFO */ 182 if (tfr->len > SUN4I_FIFO_DEPTH) 183 return -EMSGSIZE; 184 --- 97 unchanged lines hidden (view full) --- 282 283 /* Enable the interrupts */ 284 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC); 285 286 /* Start the transfer */ 287 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); 288 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH); 289 |
| 290 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); 291 start = jiffies; |
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| 289 timeout = wait_for_completion_timeout(&sspi->done, | 292 timeout = wait_for_completion_timeout(&sspi->done, |
| 290 msecs_to_jiffies(1000)); | 293 msecs_to_jiffies(tx_time)); 294 end = jiffies; |
| 291 if (!timeout) { | 295 if (!timeout) { |
| 296 dev_warn(&master->dev, 297 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms", 298 dev_name(&spi->dev), tfr->len, tfr->speed_hz, 299 jiffies_to_msecs(end - start), tx_time); |
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| 292 ret = -ETIMEDOUT; 293 goto out; 294 } 295 296 sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH); 297 298out: 299 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0); --- 184 unchanged lines hidden --- | 300 ret = -ETIMEDOUT; 301 goto out; 302 } 303 304 sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH); 305 306out: 307 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0); --- 184 unchanged lines hidden --- |