spi-pxa2xx.c (ff36e78fdb251b9fa65028554689806961e011eb) spi-pxa2xx.c (683f65ded66a9a7ff01ed7280804d2132ebfdf7e)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, Intel Corporation
5 */
6
7#include <linux/acpi.h>
8#include <linux/bitops.h>

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65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
66
67#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
68#define LPSS_CS_CONTROL_SW_MODE BIT(0)
69#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
70#define LPSS_CAPS_CS_EN_SHIFT 9
71#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
72
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, Intel Corporation
5 */
6
7#include <linux/acpi.h>
8#include <linux/bitops.h>

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65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
66
67#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
68#define LPSS_CS_CONTROL_SW_MODE BIT(0)
69#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
70#define LPSS_CAPS_CS_EN_SHIFT 9
71#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
72
73#define LPSS_PRIV_CLOCK_GATE 0x38
74#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
75#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
76
73struct lpss_config {
74 /* LPSS offset from drv_data->ioaddr */
75 unsigned offset;
76 /* Register offsets from drv_data->lpss_base or -1 */
77 int reg_general;
78 int reg_ssp;
79 int reg_cs_ctrl;
80 int reg_capabilities;
81 /* FIFO thresholds */
82 u32 rx_threshold;
83 u32 tx_threshold_lo;
84 u32 tx_threshold_hi;
85 /* Chip select control */
86 unsigned cs_sel_shift;
87 unsigned cs_sel_mask;
88 unsigned cs_num;
77struct lpss_config {
78 /* LPSS offset from drv_data->ioaddr */
79 unsigned offset;
80 /* Register offsets from drv_data->lpss_base or -1 */
81 int reg_general;
82 int reg_ssp;
83 int reg_cs_ctrl;
84 int reg_capabilities;
85 /* FIFO thresholds */
86 u32 rx_threshold;
87 u32 tx_threshold_lo;
88 u32 tx_threshold_hi;
89 /* Chip select control */
90 unsigned cs_sel_shift;
91 unsigned cs_sel_mask;
92 unsigned cs_num;
93 /* Quirks */
94 unsigned cs_clk_stays_gated : 1;
89};
90
91/* Keep these sorted with enum pxa_ssp_type */
92static const struct lpss_config lpss_platforms[] = {
93 { /* LPSS_LPT_SSP */
94 .offset = 0x800,
95 .reg_general = 0x08,
96 .reg_ssp = 0x0c,

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151 .reg_ssp = 0x20,
152 .reg_cs_ctrl = 0x24,
153 .reg_capabilities = 0xfc,
154 .rx_threshold = 1,
155 .tx_threshold_lo = 32,
156 .tx_threshold_hi = 56,
157 .cs_sel_shift = 8,
158 .cs_sel_mask = 3 << 8,
95};
96
97/* Keep these sorted with enum pxa_ssp_type */
98static const struct lpss_config lpss_platforms[] = {
99 { /* LPSS_LPT_SSP */
100 .offset = 0x800,
101 .reg_general = 0x08,
102 .reg_ssp = 0x0c,

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157 .reg_ssp = 0x20,
158 .reg_cs_ctrl = 0x24,
159 .reg_capabilities = 0xfc,
160 .rx_threshold = 1,
161 .tx_threshold_lo = 32,
162 .tx_threshold_hi = 56,
163 .cs_sel_shift = 8,
164 .cs_sel_mask = 3 << 8,
165 .cs_clk_stays_gated = true,
159 },
160};
161
162static inline const struct lpss_config
163*lpss_get_config(const struct driver_data *drv_data)
164{
165 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
166}

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378 lpss_ssp_select_cs(spi, config);
379
380 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
381 if (enable)
382 value &= ~LPSS_CS_CONTROL_CS_HIGH;
383 else
384 value |= LPSS_CS_CONTROL_CS_HIGH;
385 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
166 },
167};
168
169static inline const struct lpss_config
170*lpss_get_config(const struct driver_data *drv_data)
171{
172 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
173}

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385 lpss_ssp_select_cs(spi, config);
386
387 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
388 if (enable)
389 value &= ~LPSS_CS_CONTROL_CS_HIGH;
390 else
391 value |= LPSS_CS_CONTROL_CS_HIGH;
392 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
393 if (config->cs_clk_stays_gated) {
394 u32 clkgate;
395
396 /*
397 * Changing CS alone when dynamic clock gating is on won't
398 * actually flip CS at that time. This ruins SPI transfers
399 * that specify delays, or have no data. Toggle the clock mode
400 * to force on briefly to poke the CS pin to move.
401 */
402 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
403 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
404 LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
405
406 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
407 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
408 }
386}
387
388static void cs_assert(struct spi_device *spi)
389{
390 struct chip_data *chip = spi_get_ctldata(spi);
391 struct driver_data *drv_data =
392 spi_controller_get_devdata(spi->controller);
393

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456 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
457 pxa2xx_spi_read(drv_data, SSDR);
458 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
459 write_SSSR_CS(drv_data, SSSR_ROR);
460
461 return limit;
462}
463
409}
410
411static void cs_assert(struct spi_device *spi)
412{
413 struct chip_data *chip = spi_get_ctldata(spi);
414 struct driver_data *drv_data =
415 spi_controller_get_devdata(spi->controller);
416

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479 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
480 pxa2xx_spi_read(drv_data, SSDR);
481 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
482 write_SSSR_CS(drv_data, SSSR_ROR);
483
484 return limit;
485}
486
464static void pxa2xx_spi_off(struct driver_data *drv_data)
465{
466 /* On MMP, disabling SSE seems to corrupt the rx fifo */
467 if (drv_data->ssp_type == MMP2_SSP)
468 return;
469
470 pxa2xx_spi_write(drv_data, SSCR0,
471 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
472}
473
474static int null_writer(struct driver_data *drv_data)
475{
476 u8 n_bytes = drv_data->n_bytes;
477
478 if (pxa2xx_spi_txfifo_full(drv_data)
479 || (drv_data->tx == drv_data->tx_end))
480 return 0;
481

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592static void int_error_stop(struct driver_data *drv_data, const char* msg)
593{
594 /* Stop and reset SSP */
595 write_SSSR_CS(drv_data, drv_data->clear_sr);
596 reset_sccr1(drv_data);
597 if (!pxa25x_ssp_comp(drv_data))
598 pxa2xx_spi_write(drv_data, SSTO, 0);
599 pxa2xx_spi_flush(drv_data);
487static int null_writer(struct driver_data *drv_data)
488{
489 u8 n_bytes = drv_data->n_bytes;
490
491 if (pxa2xx_spi_txfifo_full(drv_data)
492 || (drv_data->tx == drv_data->tx_end))
493 return 0;
494

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605static void int_error_stop(struct driver_data *drv_data, const char* msg)
606{
607 /* Stop and reset SSP */
608 write_SSSR_CS(drv_data, drv_data->clear_sr);
609 reset_sccr1(drv_data);
610 if (!pxa25x_ssp_comp(drv_data))
611 pxa2xx_spi_write(drv_data, SSTO, 0);
612 pxa2xx_spi_flush(drv_data);
600 pxa2xx_spi_off(drv_data);
613 pxa2xx_spi_write(drv_data, SSCR0,
614 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
601
602 dev_err(&drv_data->pdev->dev, "%s\n", msg);
603
604 drv_data->controller->cur_msg->status = -EIO;
605 spi_finalize_current_transfer(drv_data->controller);
606}
607
608static void int_transfer_complete(struct driver_data *drv_data)

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690 }
691
692 /* We did something */
693 return IRQ_HANDLED;
694}
695
696static void handle_bad_msg(struct driver_data *drv_data)
697{
615
616 dev_err(&drv_data->pdev->dev, "%s\n", msg);
617
618 drv_data->controller->cur_msg->status = -EIO;
619 spi_finalize_current_transfer(drv_data->controller);
620}
621
622static void int_transfer_complete(struct driver_data *drv_data)

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704 }
705
706 /* We did something */
707 return IRQ_HANDLED;
708}
709
710static void handle_bad_msg(struct driver_data *drv_data)
711{
698 pxa2xx_spi_off(drv_data);
712 pxa2xx_spi_write(drv_data, SSCR0,
713 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
699 pxa2xx_spi_write(drv_data, SSCR1,
700 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
701 if (!pxa25x_ssp_comp(drv_data))
702 pxa2xx_spi_write(drv_data, SSTO, 0);
703 write_SSSR_CS(drv_data, drv_data->clear_sr);
704
705 dev_err(&drv_data->pdev->dev,
706 "bad message state in interrupt handler\n");

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1065 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1066 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1067
1068 /* see if we need to reload the config registers */
1069 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1070 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1071 != (cr1 & change_mask)) {
1072 /* stop the SSP, and update the other bits */
714 pxa2xx_spi_write(drv_data, SSCR1,
715 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
716 if (!pxa25x_ssp_comp(drv_data))
717 pxa2xx_spi_write(drv_data, SSTO, 0);
718 write_SSSR_CS(drv_data, drv_data->clear_sr);
719
720 dev_err(&drv_data->pdev->dev,
721 "bad message state in interrupt handler\n");

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1080 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1081 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1082
1083 /* see if we need to reload the config registers */
1084 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1085 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1086 != (cr1 & change_mask)) {
1087 /* stop the SSP, and update the other bits */
1073 if (drv_data->ssp_type != MMP2_SSP)
1074 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1088 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1075 if (!pxa25x_ssp_comp(drv_data))
1076 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1077 /* first set CR1 without interrupt and service enables */
1078 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1079 /* restart the SSP */
1080 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1081
1082 } else {

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1122 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1123
1124 /* Stop and reset SSP */
1125 write_SSSR_CS(drv_data, drv_data->clear_sr);
1126 reset_sccr1(drv_data);
1127 if (!pxa25x_ssp_comp(drv_data))
1128 pxa2xx_spi_write(drv_data, SSTO, 0);
1129 pxa2xx_spi_flush(drv_data);
1089 if (!pxa25x_ssp_comp(drv_data))
1090 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1091 /* first set CR1 without interrupt and service enables */
1092 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1093 /* restart the SSP */
1094 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1095
1096 } else {

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1136 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1137
1138 /* Stop and reset SSP */
1139 write_SSSR_CS(drv_data, drv_data->clear_sr);
1140 reset_sccr1(drv_data);
1141 if (!pxa25x_ssp_comp(drv_data))
1142 pxa2xx_spi_write(drv_data, SSTO, 0);
1143 pxa2xx_spi_flush(drv_data);
1130 pxa2xx_spi_off(drv_data);
1144 pxa2xx_spi_write(drv_data, SSCR0,
1145 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1131
1132 dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
1133
1134 drv_data->controller->cur_msg->status = -EINTR;
1135 spi_finalize_current_transfer(drv_data->controller);
1136
1137 return 0;
1138}
1139
1140static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1141 struct spi_message *msg)
1142{
1143 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1144
1145 /* Disable the SSP */
1146
1147 dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
1148
1149 drv_data->controller->cur_msg->status = -EINTR;
1150 spi_finalize_current_transfer(drv_data->controller);
1151
1152 return 0;
1153}
1154
1155static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1156 struct spi_message *msg)
1157{
1158 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1159
1160 /* Disable the SSP */
1146 pxa2xx_spi_off(drv_data);
1161 pxa2xx_spi_write(drv_data, SSCR0,
1162 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1147 /* Clear and disable interrupts and service requests */
1148 write_SSSR_CS(drv_data, drv_data->clear_sr);
1149 pxa2xx_spi_write(drv_data, SSCR1,
1150 pxa2xx_spi_read(drv_data, SSCR1)
1151 & ~(drv_data->int_cr1 | drv_data->dma_cr1));
1152 if (!pxa25x_ssp_comp(drv_data))
1153 pxa2xx_spi_write(drv_data, SSTO, 0);
1154

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1163 pxa2xx_spi_dma_stop(drv_data);
1164}
1165
1166static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1167{
1168 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1169
1170 /* Disable the SSP now */
1163 /* Clear and disable interrupts and service requests */
1164 write_SSSR_CS(drv_data, drv_data->clear_sr);
1165 pxa2xx_spi_write(drv_data, SSCR1,
1166 pxa2xx_spi_read(drv_data, SSCR1)
1167 & ~(drv_data->int_cr1 | drv_data->dma_cr1));
1168 if (!pxa25x_ssp_comp(drv_data))
1169 pxa2xx_spi_write(drv_data, SSTO, 0);
1170

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1179 pxa2xx_spi_dma_stop(drv_data);
1180}
1181
1182static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1183{
1184 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1185
1186 /* Disable the SSP now */
1171 pxa2xx_spi_off(drv_data);
1187 pxa2xx_spi_write(drv_data, SSCR0,
1188 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1172
1173 return 0;
1174}
1175
1176static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1177 struct pxa2xx_spi_chip *chip_info)
1178{
1179 struct driver_data *drv_data =

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1424 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1425 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1426 /* SPT-H */
1427 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1428 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1429 /* KBL-H */
1430 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1431 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1189
1190 return 0;
1191}
1192
1193static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1194 struct pxa2xx_spi_chip *chip_info)
1195{
1196 struct driver_data *drv_data =

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1441 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1442 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1443 /* SPT-H */
1444 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1445 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1446 /* KBL-H */
1447 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1448 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1432 /* CML-V */
1433 { PCI_VDEVICE(INTEL, 0xa3a9), LPSS_SPT_SSP },
1434 { PCI_VDEVICE(INTEL, 0xa3aa), LPSS_SPT_SSP },
1435 /* BXT A-Step */
1436 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1437 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1438 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1439 /* BXT B-Step */
1440 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1441 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1442 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },

--- 557 unchanged lines hidden --- 		1449 /* BXT A-Step */
1450 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1451 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1452 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1453 /* BXT B-Step */
1454 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1455 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1456 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },

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