rtc-sh.c (440fdb53b4ae58602711b5b8c3a139ace2404dbb) rtc-sh.c (ad89f87a84040a57c4a78ca2759b364f72f423ab)
1/*
2 * SuperH On-Chip RTC Support
3 *
1/*
2 * SuperH On-Chip RTC Support
3 *
4 * Copyright (C) 2006 Paul Mundt
4 * Copyright (C) 2006, 2007 Paul Mundt
5 * Copyright (C) 2006 Jamie Lenehan
6 *
7 * Based on the old arch/sh/kernel/cpu/rtc.c by:
8 *
9 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
10 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
11 *
12 * This file is subject to the terms and conditions of the GNU General Public

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18#include <linux/bcd.h>
19#include <linux/rtc.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/seq_file.h>
23#include <linux/interrupt.h>
24#include <linux/spinlock.h>
25#include <linux/io.h>
5 * Copyright (C) 2006 Jamie Lenehan
6 *
7 * Based on the old arch/sh/kernel/cpu/rtc.c by:
8 *
9 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
10 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
11 *
12 * This file is subject to the terms and conditions of the GNU General Public

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18#include <linux/bcd.h>
19#include <linux/rtc.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/seq_file.h>
23#include <linux/interrupt.h>
24#include <linux/spinlock.h>
25#include <linux/io.h>
26#include <asm/rtc.h>
26
27#define DRV_NAME "sh-rtc"
27
28#define DRV_NAME "sh-rtc"
28#define DRV_VERSION "0.1.2"
29#define DRV_VERSION "0.1.3"
29
30#ifdef CONFIG_CPU_SH3
31#define rtc_reg_size sizeof(u16)
32#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */
30
31#ifdef CONFIG_CPU_SH3
32#define rtc_reg_size sizeof(u16)
33#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */
34#define RTC_DEF_CAPABILITIES 0UL
33#elif defined(CONFIG_CPU_SH4)
34#define rtc_reg_size sizeof(u32)
35#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
35#elif defined(CONFIG_CPU_SH4)
36#define rtc_reg_size sizeof(u32)
37#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
38#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
36#endif
37
38#define RTC_REG(r) ((r) * rtc_reg_size)
39
40#define R64CNT RTC_REG(0)
41
42#define RSECCNT RTC_REG(1) /* RTC sec */
43#define RMINCNT RTC_REG(2) /* RTC min */

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75struct sh_rtc {
76 void __iomem *regbase;
77 unsigned long regsize;
78 struct resource *res;
79 unsigned int alarm_irq, periodic_irq, carry_irq;
80 struct rtc_device *rtc_dev;
81 spinlock_t lock;
82 int rearm_aie;
39#endif
40
41#define RTC_REG(r) ((r) * rtc_reg_size)
42
43#define R64CNT RTC_REG(0)
44
45#define RSECCNT RTC_REG(1) /* RTC sec */
46#define RMINCNT RTC_REG(2) /* RTC min */

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78struct sh_rtc {
79 void __iomem *regbase;
80 unsigned long regsize;
81 struct resource *res;
82 unsigned int alarm_irq, periodic_irq, carry_irq;
83 struct rtc_device *rtc_dev;
84 spinlock_t lock;
85 int rearm_aie;
86 unsigned long capabilities; /* See asm-sh/rtc.h for cap bits */
83};
84
85static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
86{
87 struct platform_device *pdev = to_platform_device(dev_id);
88 struct sh_rtc *rtc = platform_get_drvdata(pdev);
89 unsigned int tmp, events = 0;
90

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314
315 tm->tm_sec = BCD2BIN(readb(rtc->regbase + RSECCNT));
316 tm->tm_min = BCD2BIN(readb(rtc->regbase + RMINCNT));
317 tm->tm_hour = BCD2BIN(readb(rtc->regbase + RHRCNT));
318 tm->tm_wday = BCD2BIN(readb(rtc->regbase + RWKCNT));
319 tm->tm_mday = BCD2BIN(readb(rtc->regbase + RDAYCNT));
320 tm->tm_mon = BCD2BIN(readb(rtc->regbase + RMONCNT)) - 1;
321
87};
88
89static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
90{
91 struct platform_device *pdev = to_platform_device(dev_id);
92 struct sh_rtc *rtc = platform_get_drvdata(pdev);
93 unsigned int tmp, events = 0;
94

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318
319 tm->tm_sec = BCD2BIN(readb(rtc->regbase + RSECCNT));
320 tm->tm_min = BCD2BIN(readb(rtc->regbase + RMINCNT));
321 tm->tm_hour = BCD2BIN(readb(rtc->regbase + RHRCNT));
322 tm->tm_wday = BCD2BIN(readb(rtc->regbase + RWKCNT));
323 tm->tm_mday = BCD2BIN(readb(rtc->regbase + RDAYCNT));
324 tm->tm_mon = BCD2BIN(readb(rtc->regbase + RMONCNT)) - 1;
325
322#if defined(CONFIG_CPU_SH4)
323 yr = readw(rtc->regbase + RYRCNT);
324 yr100 = BCD2BIN(yr >> 8);
325 yr &= 0xff;
326#else
327 yr = readb(rtc->regbase + RYRCNT);
328 yr100 = BCD2BIN((yr == 0x99) ? 0x19 : 0x20);
329#endif
326 if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
327 yr = readw(rtc->regbase + RYRCNT);
328 yr100 = BCD2BIN(yr >> 8);
329 yr &= 0xff;
330 } else {
331 yr = readb(rtc->regbase + RYRCNT);
332 yr100 = BCD2BIN((yr == 0x99) ? 0x19 : 0x20);
333 }
330
331 tm->tm_year = (yr100 * 100 + BCD2BIN(yr)) - 1900;
332
333 sec2 = readb(rtc->regbase + R64CNT);
334 cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF;
335
336 spin_unlock_irq(&rtc->lock);
337 } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0);

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370
371 writeb(BIN2BCD(tm->tm_sec), rtc->regbase + RSECCNT);
372 writeb(BIN2BCD(tm->tm_min), rtc->regbase + RMINCNT);
373 writeb(BIN2BCD(tm->tm_hour), rtc->regbase + RHRCNT);
374 writeb(BIN2BCD(tm->tm_wday), rtc->regbase + RWKCNT);
375 writeb(BIN2BCD(tm->tm_mday), rtc->regbase + RDAYCNT);
376 writeb(BIN2BCD(tm->tm_mon + 1), rtc->regbase + RMONCNT);
377
334
335 tm->tm_year = (yr100 * 100 + BCD2BIN(yr)) - 1900;
336
337 sec2 = readb(rtc->regbase + R64CNT);
338 cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF;
339
340 spin_unlock_irq(&rtc->lock);
341 } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0);

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374
375 writeb(BIN2BCD(tm->tm_sec), rtc->regbase + RSECCNT);
376 writeb(BIN2BCD(tm->tm_min), rtc->regbase + RMINCNT);
377 writeb(BIN2BCD(tm->tm_hour), rtc->regbase + RHRCNT);
378 writeb(BIN2BCD(tm->tm_wday), rtc->regbase + RWKCNT);
379 writeb(BIN2BCD(tm->tm_mday), rtc->regbase + RDAYCNT);
380 writeb(BIN2BCD(tm->tm_mon + 1), rtc->regbase + RMONCNT);
381
378#ifdef CONFIG_CPU_SH3
379 year = tm->tm_year % 100;
380 writeb(BIN2BCD(year), rtc->regbase + RYRCNT);
381#else
382 year = (BIN2BCD((tm->tm_year + 1900) / 100) << 8) |
383 BIN2BCD(tm->tm_year % 100);
384 writew(year, rtc->regbase + RYRCNT);
385#endif
382 if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
383 year = (BIN2BCD((tm->tm_year + 1900) / 100) << 8) |
384 BIN2BCD(tm->tm_year % 100);
385 writew(year, rtc->regbase + RYRCNT);
386 } else {
387 year = tm->tm_year % 100;
388 writeb(BIN2BCD(year), rtc->regbase + RYRCNT);
389 }
386
387 /* Start RTC */
388 tmp = readb(rtc->regbase + RCR2);
389 tmp &= ~RCR2_RESET;
390 tmp |= RCR2_RTCEN | RCR2_START;
391 writeb(tmp, rtc->regbase + RCR2);
392
393 spin_unlock_irq(&rtc->lock);

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584
585 rtc->rtc_dev = rtc_device_register("sh", &pdev->dev,
586 &sh_rtc_ops, THIS_MODULE);
587 if (IS_ERR(rtc)) {
588 ret = PTR_ERR(rtc->rtc_dev);
589 goto err_badmap;
590 }
591
390
391 /* Start RTC */
392 tmp = readb(rtc->regbase + RCR2);
393 tmp &= ~RCR2_RESET;
394 tmp |= RCR2_RTCEN | RCR2_START;
395 writeb(tmp, rtc->regbase + RCR2);
396
397 spin_unlock_irq(&rtc->lock);

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588
589 rtc->rtc_dev = rtc_device_register("sh", &pdev->dev,
590 &sh_rtc_ops, THIS_MODULE);
591 if (IS_ERR(rtc)) {
592 ret = PTR_ERR(rtc->rtc_dev);
593 goto err_badmap;
594 }
595
596 rtc->capabilities = RTC_DEF_CAPABILITIES;
597 if (pdev->dev.platform_data) {
598 struct sh_rtc_platform_info *pinfo = pdev->dev.platform_data;
599
600 /*
601 * Some CPUs have special capabilities in addition to the
602 * default set. Add those in here.
603 */
604 rtc->capabilities |= pinfo->capabilities;
605 }
606
592 platform_set_drvdata(pdev, rtc);
593
594 return 0;
595
596err_badmap:
597 release_resource(rtc->res);
598err_badres:
599 kfree(rtc);

--- 48 unchanged lines hidden --- 		607 platform_set_drvdata(pdev, rtc);
608
609 return 0;
610
611err_badmap:
612 release_resource(rtc->res);
613err_badres:
614 kfree(rtc);

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