pinctrl-intel.c (7f36f5d11cda050b118f76d774151427a18d15ef) pinctrl-intel.c (e57725eabf87c9c75bc73bd19ea00e887155e43f)
1/*
2 * Intel pinctrl/GPIO core driver.
3 *
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/gpio/driver.h>
1/*
2 * Intel pinctrl/GPIO core driver.
3 *
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/gpio/driver.h>
16#include <linux/log2.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinconf-generic.h>
21
22#include "../core.h"
23#include "pinctrl-intel.h"
24
25/* Offset from regs */
17#include <linux/platform_device.h>
18#include <linux/pinctrl/pinctrl.h>
19#include <linux/pinctrl/pinmux.h>
20#include <linux/pinctrl/pinconf.h>
21#include <linux/pinctrl/pinconf-generic.h>
22
23#include "../core.h"
24#include "pinctrl-intel.h"
25
26/* Offset from regs */
27#define REVID 0x000
28#define REVID_SHIFT 16
29#define REVID_MASK GENMASK(31, 16)
30
26#define PADBAR 0x00c
27#define GPI_IS 0x100
28#define GPI_GPE_STS 0x140
29#define GPI_GPE_EN 0x160
30
31#define PADOWN_BITS 4
32#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
33#define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
34#define PADOWN_GPP(p) ((p) / 8)
35
36/* Offset from pad_regs */
37#define PADCFG0 0x000
38#define PADCFG0_RXEVCFG_SHIFT 25
39#define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
40#define PADCFG0_RXEVCFG_LEVEL 0
41#define PADCFG0_RXEVCFG_EDGE 1
42#define PADCFG0_RXEVCFG_DISABLED 2
43#define PADCFG0_RXEVCFG_EDGE_BOTH 3
31#define PADBAR 0x00c
32#define GPI_IS 0x100
33#define GPI_GPE_STS 0x140
34#define GPI_GPE_EN 0x160
35
36#define PADOWN_BITS 4
37#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
38#define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
39#define PADOWN_GPP(p) ((p) / 8)
40
41/* Offset from pad_regs */
42#define PADCFG0 0x000
43#define PADCFG0_RXEVCFG_SHIFT 25
44#define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
45#define PADCFG0_RXEVCFG_LEVEL 0
46#define PADCFG0_RXEVCFG_EDGE 1
47#define PADCFG0_RXEVCFG_DISABLED 2
48#define PADCFG0_RXEVCFG_EDGE_BOTH 3
49#define PADCFG0_PREGFRXSEL BIT(24)
44#define PADCFG0_RXINV BIT(23)
45#define PADCFG0_GPIROUTIOXAPIC BIT(20)
46#define PADCFG0_GPIROUTSCI BIT(19)
47#define PADCFG0_GPIROUTSMI BIT(18)
48#define PADCFG0_GPIROUTNMI BIT(17)
49#define PADCFG0_PMODE_SHIFT 10
50#define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
51#define PADCFG0_GPIORXDIS BIT(9)

--- 5 unchanged lines hidden (view full) ---

57#define PADCFG1_TERM_UP BIT(13)
58#define PADCFG1_TERM_SHIFT 10
59#define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
60#define PADCFG1_TERM_20K 4
61#define PADCFG1_TERM_2K 3
62#define PADCFG1_TERM_5K 2
63#define PADCFG1_TERM_1K 1
64
50#define PADCFG0_RXINV BIT(23)
51#define PADCFG0_GPIROUTIOXAPIC BIT(20)
52#define PADCFG0_GPIROUTSCI BIT(19)
53#define PADCFG0_GPIROUTSMI BIT(18)
54#define PADCFG0_GPIROUTNMI BIT(17)
55#define PADCFG0_PMODE_SHIFT 10
56#define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
57#define PADCFG0_GPIORXDIS BIT(9)

--- 5 unchanged lines hidden (view full) ---

63#define PADCFG1_TERM_UP BIT(13)
64#define PADCFG1_TERM_SHIFT 10
65#define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
66#define PADCFG1_TERM_20K 4
67#define PADCFG1_TERM_2K 3
68#define PADCFG1_TERM_5K 2
69#define PADCFG1_TERM_1K 1
70
71#define PADCFG2 0x008
72#define PADCFG2_DEBEN BIT(0)
73#define PADCFG2_DEBOUNCE_SHIFT 1
74#define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
75
76#define DEBOUNCE_PERIOD 31250 /* ns */
77
65struct intel_pad_context {
66 u32 padcfg0;
67 u32 padcfg1;
78struct intel_pad_context {
79 u32 padcfg0;
80 u32 padcfg1;
81 u32 padcfg2;
68};
69
70struct intel_community_context {
71 u32 *intmask;
72};
73
74struct intel_pinctrl_context {
75 struct intel_pad_context *pads;

--- 45 unchanged lines hidden (view full) ---

121 return NULL;
122}
123
124static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
125 unsigned reg)
126{
127 const struct intel_community *community;
128 unsigned padno;
82};
83
84struct intel_community_context {
85 u32 *intmask;
86};
87
88struct intel_pinctrl_context {
89 struct intel_pad_context *pads;

--- 45 unchanged lines hidden (view full) ---

135 return NULL;
136}
137
138static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
139 unsigned reg)
140{
141 const struct intel_community *community;
142 unsigned padno;
143 size_t nregs;
129
130 community = intel_get_community(pctrl, pin);
131 if (!community)
132 return NULL;
133
134 padno = pin_to_padno(community, pin);
144
145 community = intel_get_community(pctrl, pin);
146 if (!community)
147 return NULL;
148
149 padno = pin_to_padno(community, pin);
135 return community->pad_regs + reg + padno * 8;
150 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
151
152 if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
153 return NULL;
154
155 return community->pad_regs + reg + padno * nregs * 4;
136}
137
138static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
139{
140 const struct intel_community *community;
141 unsigned padno, gpp, offset, group;
142 void __iomem *padown;
143

--- 95 unchanged lines hidden (view full) ---

239 *npins = pctrl->soc->groups[group].npins;
240 return 0;
241}
242
243static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
244 unsigned pin)
245{
246 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
156}
157
158static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
159{
160 const struct intel_community *community;
161 unsigned padno, gpp, offset, group;
162 void __iomem *padown;
163

--- 95 unchanged lines hidden (view full) ---

259 *npins = pctrl->soc->groups[group].npins;
260 return 0;
261}
262
263static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
264 unsigned pin)
265{
266 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
267 void __iomem *padcfg;
247 u32 cfg0, cfg1, mode;
248 bool locked, acpi;
249
250 if (!intel_pad_owned_by_host(pctrl, pin)) {
251 seq_puts(s, "not available");
252 return;
253 }
254
255 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
256 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
257
258 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
259 if (!mode)
260 seq_puts(s, "GPIO ");
261 else
262 seq_printf(s, "mode %d ", mode);
263
264 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
265
268 u32 cfg0, cfg1, mode;
269 bool locked, acpi;
270
271 if (!intel_pad_owned_by_host(pctrl, pin)) {
272 seq_puts(s, "not available");
273 return;
274 }
275
276 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
277 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
278
279 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
280 if (!mode)
281 seq_puts(s, "GPIO ");
282 else
283 seq_printf(s, "mode %d ", mode);
284
285 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
286
287 /* Dump the additional PADCFG registers if available */
288 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
289 if (padcfg)
290 seq_printf(s, " 0x%08x", readl(padcfg));
291
266 locked = intel_pad_locked(pctrl, pin);
267 acpi = intel_pad_acpi_mode(pctrl, pin);
268
269 if (locked || acpi) {
270 seq_puts(s, " [");
271 if (locked) {
272 seq_puts(s, "LOCKED");
273 if (acpi)

--- 154 unchanged lines hidden (view full) ---

428};
429
430static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
431 unsigned long *config)
432{
433 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
434 enum pin_config_param param = pinconf_to_config_param(*config);
435 u32 value, term;
292 locked = intel_pad_locked(pctrl, pin);
293 acpi = intel_pad_acpi_mode(pctrl, pin);
294
295 if (locked || acpi) {
296 seq_puts(s, " [");
297 if (locked) {
298 seq_puts(s, "LOCKED");
299 if (acpi)

--- 154 unchanged lines hidden (view full) ---

454};
455
456static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
457 unsigned long *config)
458{
459 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
460 enum pin_config_param param = pinconf_to_config_param(*config);
461 u32 value, term;
436 u16 arg = 0;
462 u32 arg = 0;
437
438 if (!intel_pad_owned_by_host(pctrl, pin))
439 return -ENOTSUPP;
440
441 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
442 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
443
444 switch (param) {

--- 33 unchanged lines hidden (view full) ---

478 break;
479 case PADCFG1_TERM_20K:
480 arg = 20000;
481 break;
482 }
483
484 break;
485
463
464 if (!intel_pad_owned_by_host(pctrl, pin))
465 return -ENOTSUPP;
466
467 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
468 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
469
470 switch (param) {

--- 33 unchanged lines hidden (view full) ---

504 break;
505 case PADCFG1_TERM_20K:
506 arg = 20000;
507 break;
508 }
509
510 break;
511
512 case PIN_CONFIG_INPUT_DEBOUNCE: {
513 void __iomem *padcfg2;
514 u32 v;
515
516 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
517 if (!padcfg2)
518 return -ENOTSUPP;
519
520 v = readl(padcfg2);
521 if (!(v & PADCFG2_DEBEN))
522 return -EINVAL;
523
524 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
525 arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
526
527 break;
528 }
529
486 default:
487 return -ENOTSUPP;
488 }
489
490 *config = pinconf_to_config_packed(param, arg);
491 return 0;
492}
493

--- 61 unchanged lines hidden (view full) ---

555 if (!ret)
556 writel(value, padcfg1);
557
558 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
559
560 return ret;
561}
562
530 default:
531 return -ENOTSUPP;
532 }
533
534 *config = pinconf_to_config_packed(param, arg);
535 return 0;
536}
537

--- 61 unchanged lines hidden (view full) ---

599 if (!ret)
600 writel(value, padcfg1);
601
602 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
603
604 return ret;
605}
606
607static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
608 unsigned debounce)
609{
610 void __iomem *padcfg0, *padcfg2;
611 unsigned long flags;
612 u32 value0, value2;
613 int ret = 0;
614
615 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
616 if (!padcfg2)
617 return -ENOTSUPP;
618
619 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
620
621 raw_spin_lock_irqsave(&pctrl->lock, flags);
622
623 value0 = readl(padcfg0);
624 value2 = readl(padcfg2);
625
626 /* Disable glitch filter and debouncer */
627 value0 &= ~PADCFG0_PREGFRXSEL;
628 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
629
630 if (debounce) {
631 unsigned long v;
632
633 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
634 if (v < 3 || v > 15) {
635 ret = -EINVAL;
636 goto exit_unlock;
637 } else {
638 /* Enable glitch filter and debouncer */
639 value0 |= PADCFG0_PREGFRXSEL;
640 value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
641 value2 |= PADCFG2_DEBEN;
642 }
643 }
644
645 writel(value0, padcfg0);
646 writel(value2, padcfg2);
647
648exit_unlock:
649 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
650
651 return ret;
652}
653
563static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
564 unsigned long *configs, unsigned nconfigs)
565{
566 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
567 int i, ret;
568
569 if (!intel_pad_usable(pctrl, pin))
570 return -ENOTSUPP;
571
572 for (i = 0; i < nconfigs; i++) {
573 switch (pinconf_to_config_param(configs[i])) {
574 case PIN_CONFIG_BIAS_DISABLE:
575 case PIN_CONFIG_BIAS_PULL_UP:
576 case PIN_CONFIG_BIAS_PULL_DOWN:
577 ret = intel_config_set_pull(pctrl, pin, configs[i]);
578 if (ret)
579 return ret;
580 break;
581
654static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
655 unsigned long *configs, unsigned nconfigs)
656{
657 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
658 int i, ret;
659
660 if (!intel_pad_usable(pctrl, pin))
661 return -ENOTSUPP;
662
663 for (i = 0; i < nconfigs; i++) {
664 switch (pinconf_to_config_param(configs[i])) {
665 case PIN_CONFIG_BIAS_DISABLE:
666 case PIN_CONFIG_BIAS_PULL_UP:
667 case PIN_CONFIG_BIAS_PULL_DOWN:
668 ret = intel_config_set_pull(pctrl, pin, configs[i]);
669 if (ret)
670 return ret;
671 break;
672
673 case PIN_CONFIG_INPUT_DEBOUNCE:
674 ret = intel_config_set_debounce(pctrl, pin,
675 pinconf_to_config_argument(configs[i]));
676 if (ret)
677 return ret;
678 break;
679
582 default:
583 return -ENOTSUPP;
584 }
585 }
586
587 return 0;
588}
589

--- 58 unchanged lines hidden (view full) ---

648static const struct gpio_chip intel_gpio_chip = {
649 .owner = THIS_MODULE,
650 .request = gpiochip_generic_request,
651 .free = gpiochip_generic_free,
652 .direction_input = intel_gpio_direction_input,
653 .direction_output = intel_gpio_direction_output,
654 .get = intel_gpio_get,
655 .set = intel_gpio_set,
680 default:
681 return -ENOTSUPP;
682 }
683 }
684
685 return 0;
686}
687

--- 58 unchanged lines hidden (view full) ---

746static const struct gpio_chip intel_gpio_chip = {
747 .owner = THIS_MODULE,
748 .request = gpiochip_generic_request,
749 .free = gpiochip_generic_free,
750 .direction_input = intel_gpio_direction_input,
751 .direction_output = intel_gpio_direction_output,
752 .get = intel_gpio_get,
753 .set = intel_gpio_set,
754 .set_config = gpiochip_generic_config,
656};
657
658static void intel_gpio_irq_ack(struct irq_data *d)
659{
660 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
661 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
662 const struct intel_community *community;
663 unsigned pin = irqd_to_hwirq(d);

--- 339 unchanged lines hidden (view full) ---

1003 *community = pctrl->soc->communities[i];
1004
1005 res = platform_get_resource(pdev, IORESOURCE_MEM,
1006 community->barno);
1007 regs = devm_ioremap_resource(&pdev->dev, res);
1008 if (IS_ERR(regs))
1009 return PTR_ERR(regs);
1010
755};
756
757static void intel_gpio_irq_ack(struct irq_data *d)
758{
759 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
760 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
761 const struct intel_community *community;
762 unsigned pin = irqd_to_hwirq(d);

--- 339 unchanged lines hidden (view full) ---

1102 *community = pctrl->soc->communities[i];
1103
1104 res = platform_get_resource(pdev, IORESOURCE_MEM,
1105 community->barno);
1106 regs = devm_ioremap_resource(&pdev->dev, res);
1107 if (IS_ERR(regs))
1108 return PTR_ERR(regs);
1109
1110 /*
1111 * Determine community features based on the revision if
1112 * not specified already.
1113 */
1114 if (!community->features) {
1115 u32 rev;
1116
1117 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1118 if (rev >= 0x94)
1119 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1120 }
1121
1011 /* Read offset of the pad configuration registers */
1012 padbar = readl(regs + PADBAR);
1013
1014 community->regs = regs;
1015 community->pad_regs = regs + padbar;
1016 community->ngpps = DIV_ROUND_UP(community->npins,
1017 community->gpp_size);
1018 }

--- 57 unchanged lines hidden (view full) ---

1076 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1077 struct intel_community_context *communities;
1078 struct intel_pad_context *pads;
1079 int i;
1080
1081 pads = pctrl->context.pads;
1082 for (i = 0; i < pctrl->soc->npins; i++) {
1083 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1122 /* Read offset of the pad configuration registers */
1123 padbar = readl(regs + PADBAR);
1124
1125 community->regs = regs;
1126 community->pad_regs = regs + padbar;
1127 community->ngpps = DIV_ROUND_UP(community->npins,
1128 community->gpp_size);
1129 }

--- 57 unchanged lines hidden (view full) ---

1187 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1188 struct intel_community_context *communities;
1189 struct intel_pad_context *pads;
1190 int i;
1191
1192 pads = pctrl->context.pads;
1193 for (i = 0; i < pctrl->soc->npins; i++) {
1194 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1195 void __iomem *padcfg;
1084 u32 val;
1085
1086 if (!intel_pinctrl_should_save(pctrl, desc->number))
1087 continue;
1088
1089 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1090 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1091 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1092 pads[i].padcfg1 = val;
1196 u32 val;
1197
1198 if (!intel_pinctrl_should_save(pctrl, desc->number))
1199 continue;
1200
1201 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1202 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1203 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1204 pads[i].padcfg1 = val;
1205
1206 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1207 if (padcfg)
1208 pads[i].padcfg2 = readl(padcfg);
1093 }
1094
1095 communities = pctrl->context.communities;
1096 for (i = 0; i < pctrl->ncommunities; i++) {
1097 struct intel_community *community = &pctrl->communities[i];
1098 void __iomem *base;
1099 unsigned gpp;
1100

--- 56 unchanged lines hidden (view full) ---

1157
1158 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1159 val = readl(padcfg);
1160 if (val != pads[i].padcfg1) {
1161 writel(pads[i].padcfg1, padcfg);
1162 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1163 desc->number, readl(padcfg));
1164 }
1209 }
1210
1211 communities = pctrl->context.communities;
1212 for (i = 0; i < pctrl->ncommunities; i++) {
1213 struct intel_community *community = &pctrl->communities[i];
1214 void __iomem *base;
1215 unsigned gpp;
1216

--- 56 unchanged lines hidden (view full) ---

1273
1274 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1275 val = readl(padcfg);
1276 if (val != pads[i].padcfg1) {
1277 writel(pads[i].padcfg1, padcfg);
1278 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1279 desc->number, readl(padcfg));
1280 }
1281
1282 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1283 if (padcfg) {
1284 val = readl(padcfg);
1285 if (val != pads[i].padcfg2) {
1286 writel(pads[i].padcfg2, padcfg);
1287 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1288 desc->number, readl(padcfg));
1289 }
1290 }
1165 }
1166
1167 communities = pctrl->context.communities;
1168 for (i = 0; i < pctrl->ncommunities; i++) {
1169 struct intel_community *community = &pctrl->communities[i];
1170 void __iomem *base;
1171 unsigned gpp;
1172

--- 17 unchanged lines hidden --- 		1291 }
1292
1293 communities = pctrl->context.communities;
1294 for (i = 0; i < pctrl->ncommunities; i++) {
1295 struct intel_community *community = &pctrl->communities[i];
1296 void __iomem *base;
1297 unsigned gpp;
1298

--- 17 unchanged lines hidden ---