1 /* 2 * Intel pinctrl/GPIO core driver. 3 * 4 * Copyright (C) 2015, Intel Corporation 5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 6 * Mika Westerberg <mika.westerberg@linux.intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/interrupt.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/platform_device.h> 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinmux.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinconf-generic.h> 21 22 #include "../core.h" 23 #include "pinctrl-intel.h" 24 25 /* Offset from regs */ 26 #define PADBAR 0x00c 27 #define GPI_IS 0x100 28 #define GPI_GPE_STS 0x140 29 #define GPI_GPE_EN 0x160 30 31 #define PADOWN_BITS 4 32 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 33 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p)) 34 #define PADOWN_GPP(p) ((p) / 8) 35 36 /* Offset from pad_regs */ 37 #define PADCFG0 0x000 38 #define PADCFG0_RXEVCFG_SHIFT 25 39 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT) 40 #define PADCFG0_RXEVCFG_LEVEL 0 41 #define PADCFG0_RXEVCFG_EDGE 1 42 #define PADCFG0_RXEVCFG_DISABLED 2 43 #define PADCFG0_RXEVCFG_EDGE_BOTH 3 44 #define PADCFG0_RXINV BIT(23) 45 #define PADCFG0_GPIROUTIOXAPIC BIT(20) 46 #define PADCFG0_GPIROUTSCI BIT(19) 47 #define PADCFG0_GPIROUTSMI BIT(18) 48 #define PADCFG0_GPIROUTNMI BIT(17) 49 #define PADCFG0_PMODE_SHIFT 10 50 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT) 51 #define PADCFG0_GPIORXDIS BIT(9) 52 #define PADCFG0_GPIOTXDIS BIT(8) 53 #define PADCFG0_GPIORXSTATE BIT(1) 54 #define PADCFG0_GPIOTXSTATE BIT(0) 55 56 #define PADCFG1 0x004 57 #define PADCFG1_TERM_UP BIT(13) 58 #define PADCFG1_TERM_SHIFT 10 59 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT) 60 #define PADCFG1_TERM_20K 4 61 #define PADCFG1_TERM_2K 3 62 #define PADCFG1_TERM_5K 2 63 #define PADCFG1_TERM_1K 1 64 65 struct intel_pad_context { 66 u32 padcfg0; 67 u32 padcfg1; 68 }; 69 70 struct intel_community_context { 71 u32 *intmask; 72 }; 73 74 struct intel_pinctrl_context { 75 struct intel_pad_context *pads; 76 struct intel_community_context *communities; 77 }; 78 79 /** 80 * struct intel_pinctrl - Intel pinctrl private structure 81 * @dev: Pointer to the device structure 82 * @lock: Lock to serialize register access 83 * @pctldesc: Pin controller description 84 * @pctldev: Pointer to the pin controller device 85 * @chip: GPIO chip in this pin controller 86 * @soc: SoC/PCH specific pin configuration data 87 * @communities: All communities in this pin controller 88 * @ncommunities: Number of communities in this pin controller 89 * @context: Configuration saved over system sleep 90 * @irq: pinctrl/GPIO chip irq number 91 */ 92 struct intel_pinctrl { 93 struct device *dev; 94 raw_spinlock_t lock; 95 struct pinctrl_desc pctldesc; 96 struct pinctrl_dev *pctldev; 97 struct gpio_chip chip; 98 const struct intel_pinctrl_soc_data *soc; 99 struct intel_community *communities; 100 size_t ncommunities; 101 struct intel_pinctrl_context context; 102 int irq; 103 }; 104 105 #define pin_to_padno(c, p) ((p) - (c)->pin_base) 106 107 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, 108 unsigned pin) 109 { 110 struct intel_community *community; 111 int i; 112 113 for (i = 0; i < pctrl->ncommunities; i++) { 114 community = &pctrl->communities[i]; 115 if (pin >= community->pin_base && 116 pin < community->pin_base + community->npins) 117 return community; 118 } 119 120 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 121 return NULL; 122 } 123 124 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, 125 unsigned reg) 126 { 127 const struct intel_community *community; 128 unsigned padno; 129 130 community = intel_get_community(pctrl, pin); 131 if (!community) 132 return NULL; 133 134 padno = pin_to_padno(community, pin); 135 return community->pad_regs + reg + padno * 8; 136 } 137 138 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) 139 { 140 const struct intel_community *community; 141 unsigned padno, gpp, offset, group; 142 void __iomem *padown; 143 144 community = intel_get_community(pctrl, pin); 145 if (!community) 146 return false; 147 if (!community->padown_offset) 148 return true; 149 150 padno = pin_to_padno(community, pin); 151 group = padno / community->gpp_size; 152 gpp = PADOWN_GPP(padno % community->gpp_size); 153 offset = community->padown_offset + 0x10 * group + gpp * 4; 154 padown = community->regs + offset; 155 156 return !(readl(padown) & PADOWN_MASK(padno)); 157 } 158 159 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) 160 { 161 const struct intel_community *community; 162 unsigned padno, gpp, offset; 163 void __iomem *hostown; 164 165 community = intel_get_community(pctrl, pin); 166 if (!community) 167 return true; 168 if (!community->hostown_offset) 169 return false; 170 171 padno = pin_to_padno(community, pin); 172 gpp = padno / community->gpp_size; 173 offset = community->hostown_offset + gpp * 4; 174 hostown = community->regs + offset; 175 176 return !(readl(hostown) & BIT(padno % community->gpp_size)); 177 } 178 179 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) 180 { 181 struct intel_community *community; 182 unsigned padno, gpp, offset; 183 u32 value; 184 185 community = intel_get_community(pctrl, pin); 186 if (!community) 187 return true; 188 if (!community->padcfglock_offset) 189 return false; 190 191 padno = pin_to_padno(community, pin); 192 gpp = padno / community->gpp_size; 193 194 /* 195 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 196 * the pad is considered unlocked. Any other case means that it is 197 * either fully or partially locked and we don't touch it. 198 */ 199 offset = community->padcfglock_offset + gpp * 8; 200 value = readl(community->regs + offset); 201 if (value & BIT(pin % community->gpp_size)) 202 return true; 203 204 offset = community->padcfglock_offset + 4 + gpp * 8; 205 value = readl(community->regs + offset); 206 if (value & BIT(pin % community->gpp_size)) 207 return true; 208 209 return false; 210 } 211 212 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin) 213 { 214 return intel_pad_owned_by_host(pctrl, pin) && 215 !intel_pad_locked(pctrl, pin); 216 } 217 218 static int intel_get_groups_count(struct pinctrl_dev *pctldev) 219 { 220 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 221 222 return pctrl->soc->ngroups; 223 } 224 225 static const char *intel_get_group_name(struct pinctrl_dev *pctldev, 226 unsigned group) 227 { 228 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 229 230 return pctrl->soc->groups[group].name; 231 } 232 233 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 234 const unsigned **pins, unsigned *npins) 235 { 236 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 237 238 *pins = pctrl->soc->groups[group].pins; 239 *npins = pctrl->soc->groups[group].npins; 240 return 0; 241 } 242 243 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 244 unsigned pin) 245 { 246 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 247 u32 cfg0, cfg1, mode; 248 bool locked, acpi; 249 250 if (!intel_pad_owned_by_host(pctrl, pin)) { 251 seq_puts(s, "not available"); 252 return; 253 } 254 255 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 256 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 257 258 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 259 if (!mode) 260 seq_puts(s, "GPIO "); 261 else 262 seq_printf(s, "mode %d ", mode); 263 264 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 265 266 locked = intel_pad_locked(pctrl, pin); 267 acpi = intel_pad_acpi_mode(pctrl, pin); 268 269 if (locked || acpi) { 270 seq_puts(s, " ["); 271 if (locked) { 272 seq_puts(s, "LOCKED"); 273 if (acpi) 274 seq_puts(s, ", "); 275 } 276 if (acpi) 277 seq_puts(s, "ACPI"); 278 seq_puts(s, "]"); 279 } 280 } 281 282 static const struct pinctrl_ops intel_pinctrl_ops = { 283 .get_groups_count = intel_get_groups_count, 284 .get_group_name = intel_get_group_name, 285 .get_group_pins = intel_get_group_pins, 286 .pin_dbg_show = intel_pin_dbg_show, 287 }; 288 289 static int intel_get_functions_count(struct pinctrl_dev *pctldev) 290 { 291 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 292 293 return pctrl->soc->nfunctions; 294 } 295 296 static const char *intel_get_function_name(struct pinctrl_dev *pctldev, 297 unsigned function) 298 { 299 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 300 301 return pctrl->soc->functions[function].name; 302 } 303 304 static int intel_get_function_groups(struct pinctrl_dev *pctldev, 305 unsigned function, 306 const char * const **groups, 307 unsigned * const ngroups) 308 { 309 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 310 311 *groups = pctrl->soc->functions[function].groups; 312 *ngroups = pctrl->soc->functions[function].ngroups; 313 return 0; 314 } 315 316 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, 317 unsigned group) 318 { 319 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 320 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 321 unsigned long flags; 322 int i; 323 324 raw_spin_lock_irqsave(&pctrl->lock, flags); 325 326 /* 327 * All pins in the groups needs to be accessible and writable 328 * before we can enable the mux for this group. 329 */ 330 for (i = 0; i < grp->npins; i++) { 331 if (!intel_pad_usable(pctrl, grp->pins[i])) { 332 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 333 return -EBUSY; 334 } 335 } 336 337 /* Now enable the mux setting for each pin in the group */ 338 for (i = 0; i < grp->npins; i++) { 339 void __iomem *padcfg0; 340 u32 value; 341 342 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); 343 value = readl(padcfg0); 344 345 value &= ~PADCFG0_PMODE_MASK; 346 value |= grp->mode << PADCFG0_PMODE_SHIFT; 347 348 writel(value, padcfg0); 349 } 350 351 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 352 353 return 0; 354 } 355 356 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) 357 { 358 u32 value; 359 360 value = readl(padcfg0); 361 if (input) { 362 value &= ~PADCFG0_GPIORXDIS; 363 value |= PADCFG0_GPIOTXDIS; 364 } else { 365 value &= ~PADCFG0_GPIOTXDIS; 366 value |= PADCFG0_GPIORXDIS; 367 } 368 writel(value, padcfg0); 369 } 370 371 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 372 struct pinctrl_gpio_range *range, 373 unsigned pin) 374 { 375 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 376 void __iomem *padcfg0; 377 unsigned long flags; 378 u32 value; 379 380 raw_spin_lock_irqsave(&pctrl->lock, flags); 381 382 if (!intel_pad_usable(pctrl, pin)) { 383 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 384 return -EBUSY; 385 } 386 387 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 388 /* Put the pad into GPIO mode */ 389 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK; 390 /* Disable SCI/SMI/NMI generation */ 391 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 392 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 393 writel(value, padcfg0); 394 395 /* Disable TX buffer and enable RX (this will be input) */ 396 __intel_gpio_set_direction(padcfg0, true); 397 398 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 399 400 return 0; 401 } 402 403 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 404 struct pinctrl_gpio_range *range, 405 unsigned pin, bool input) 406 { 407 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 408 void __iomem *padcfg0; 409 unsigned long flags; 410 411 raw_spin_lock_irqsave(&pctrl->lock, flags); 412 413 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 414 __intel_gpio_set_direction(padcfg0, input); 415 416 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 417 418 return 0; 419 } 420 421 static const struct pinmux_ops intel_pinmux_ops = { 422 .get_functions_count = intel_get_functions_count, 423 .get_function_name = intel_get_function_name, 424 .get_function_groups = intel_get_function_groups, 425 .set_mux = intel_pinmux_set_mux, 426 .gpio_request_enable = intel_gpio_request_enable, 427 .gpio_set_direction = intel_gpio_set_direction, 428 }; 429 430 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin, 431 unsigned long *config) 432 { 433 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 434 enum pin_config_param param = pinconf_to_config_param(*config); 435 u32 value, term; 436 u16 arg = 0; 437 438 if (!intel_pad_owned_by_host(pctrl, pin)) 439 return -ENOTSUPP; 440 441 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 442 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 443 444 switch (param) { 445 case PIN_CONFIG_BIAS_DISABLE: 446 if (term) 447 return -EINVAL; 448 break; 449 450 case PIN_CONFIG_BIAS_PULL_UP: 451 if (!term || !(value & PADCFG1_TERM_UP)) 452 return -EINVAL; 453 454 switch (term) { 455 case PADCFG1_TERM_1K: 456 arg = 1000; 457 break; 458 case PADCFG1_TERM_2K: 459 arg = 2000; 460 break; 461 case PADCFG1_TERM_5K: 462 arg = 5000; 463 break; 464 case PADCFG1_TERM_20K: 465 arg = 20000; 466 break; 467 } 468 469 break; 470 471 case PIN_CONFIG_BIAS_PULL_DOWN: 472 if (!term || value & PADCFG1_TERM_UP) 473 return -EINVAL; 474 475 switch (term) { 476 case PADCFG1_TERM_5K: 477 arg = 5000; 478 break; 479 case PADCFG1_TERM_20K: 480 arg = 20000; 481 break; 482 } 483 484 break; 485 486 default: 487 return -ENOTSUPP; 488 } 489 490 *config = pinconf_to_config_packed(param, arg); 491 return 0; 492 } 493 494 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin, 495 unsigned long config) 496 { 497 unsigned param = pinconf_to_config_param(config); 498 unsigned arg = pinconf_to_config_argument(config); 499 void __iomem *padcfg1; 500 unsigned long flags; 501 int ret = 0; 502 u32 value; 503 504 raw_spin_lock_irqsave(&pctrl->lock, flags); 505 506 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 507 value = readl(padcfg1); 508 509 switch (param) { 510 case PIN_CONFIG_BIAS_DISABLE: 511 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); 512 break; 513 514 case PIN_CONFIG_BIAS_PULL_UP: 515 value &= ~PADCFG1_TERM_MASK; 516 517 value |= PADCFG1_TERM_UP; 518 519 switch (arg) { 520 case 20000: 521 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 522 break; 523 case 5000: 524 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 525 break; 526 case 2000: 527 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT; 528 break; 529 case 1000: 530 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 531 break; 532 default: 533 ret = -EINVAL; 534 } 535 536 break; 537 538 case PIN_CONFIG_BIAS_PULL_DOWN: 539 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); 540 541 switch (arg) { 542 case 20000: 543 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 544 break; 545 case 5000: 546 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 547 break; 548 default: 549 ret = -EINVAL; 550 } 551 552 break; 553 } 554 555 if (!ret) 556 writel(value, padcfg1); 557 558 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 559 560 return ret; 561 } 562 563 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin, 564 unsigned long *configs, unsigned nconfigs) 565 { 566 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 567 int i, ret; 568 569 if (!intel_pad_usable(pctrl, pin)) 570 return -ENOTSUPP; 571 572 for (i = 0; i < nconfigs; i++) { 573 switch (pinconf_to_config_param(configs[i])) { 574 case PIN_CONFIG_BIAS_DISABLE: 575 case PIN_CONFIG_BIAS_PULL_UP: 576 case PIN_CONFIG_BIAS_PULL_DOWN: 577 ret = intel_config_set_pull(pctrl, pin, configs[i]); 578 if (ret) 579 return ret; 580 break; 581 582 default: 583 return -ENOTSUPP; 584 } 585 } 586 587 return 0; 588 } 589 590 static const struct pinconf_ops intel_pinconf_ops = { 591 .is_generic = true, 592 .pin_config_get = intel_config_get, 593 .pin_config_set = intel_config_set, 594 }; 595 596 static const struct pinctrl_desc intel_pinctrl_desc = { 597 .pctlops = &intel_pinctrl_ops, 598 .pmxops = &intel_pinmux_ops, 599 .confops = &intel_pinconf_ops, 600 .owner = THIS_MODULE, 601 }; 602 603 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) 604 { 605 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 606 void __iomem *reg; 607 608 reg = intel_get_padcfg(pctrl, offset, PADCFG0); 609 if (!reg) 610 return -EINVAL; 611 612 return !!(readl(reg) & PADCFG0_GPIORXSTATE); 613 } 614 615 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 616 { 617 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 618 void __iomem *reg; 619 620 reg = intel_get_padcfg(pctrl, offset, PADCFG0); 621 if (reg) { 622 unsigned long flags; 623 u32 padcfg0; 624 625 raw_spin_lock_irqsave(&pctrl->lock, flags); 626 padcfg0 = readl(reg); 627 if (value) 628 padcfg0 |= PADCFG0_GPIOTXSTATE; 629 else 630 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 631 writel(padcfg0, reg); 632 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 633 } 634 } 635 636 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 637 { 638 return pinctrl_gpio_direction_input(chip->base + offset); 639 } 640 641 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 642 int value) 643 { 644 intel_gpio_set(chip, offset, value); 645 return pinctrl_gpio_direction_output(chip->base + offset); 646 } 647 648 static const struct gpio_chip intel_gpio_chip = { 649 .owner = THIS_MODULE, 650 .request = gpiochip_generic_request, 651 .free = gpiochip_generic_free, 652 .direction_input = intel_gpio_direction_input, 653 .direction_output = intel_gpio_direction_output, 654 .get = intel_gpio_get, 655 .set = intel_gpio_set, 656 }; 657 658 static void intel_gpio_irq_ack(struct irq_data *d) 659 { 660 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 661 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 662 const struct intel_community *community; 663 unsigned pin = irqd_to_hwirq(d); 664 665 raw_spin_lock(&pctrl->lock); 666 667 community = intel_get_community(pctrl, pin); 668 if (community) { 669 unsigned padno = pin_to_padno(community, pin); 670 unsigned gpp_offset = padno % community->gpp_size; 671 unsigned gpp = padno / community->gpp_size; 672 673 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); 674 } 675 676 raw_spin_unlock(&pctrl->lock); 677 } 678 679 static void intel_gpio_irq_enable(struct irq_data *d) 680 { 681 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 682 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 683 const struct intel_community *community; 684 unsigned pin = irqd_to_hwirq(d); 685 unsigned long flags; 686 687 raw_spin_lock_irqsave(&pctrl->lock, flags); 688 689 community = intel_get_community(pctrl, pin); 690 if (community) { 691 unsigned padno = pin_to_padno(community, pin); 692 unsigned gpp_size = community->gpp_size; 693 unsigned gpp_offset = padno % gpp_size; 694 unsigned gpp = padno / gpp_size; 695 u32 value; 696 697 /* Clear interrupt status first to avoid unexpected interrupt */ 698 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); 699 700 value = readl(community->regs + community->ie_offset + gpp * 4); 701 value |= BIT(gpp_offset); 702 writel(value, community->regs + community->ie_offset + gpp * 4); 703 } 704 705 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 706 } 707 708 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 709 { 710 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 711 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 712 const struct intel_community *community; 713 unsigned pin = irqd_to_hwirq(d); 714 unsigned long flags; 715 716 raw_spin_lock_irqsave(&pctrl->lock, flags); 717 718 community = intel_get_community(pctrl, pin); 719 if (community) { 720 unsigned padno = pin_to_padno(community, pin); 721 unsigned gpp_offset = padno % community->gpp_size; 722 unsigned gpp = padno / community->gpp_size; 723 void __iomem *reg; 724 u32 value; 725 726 reg = community->regs + community->ie_offset + gpp * 4; 727 value = readl(reg); 728 if (mask) 729 value &= ~BIT(gpp_offset); 730 else 731 value |= BIT(gpp_offset); 732 writel(value, reg); 733 } 734 735 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 736 } 737 738 static void intel_gpio_irq_mask(struct irq_data *d) 739 { 740 intel_gpio_irq_mask_unmask(d, true); 741 } 742 743 static void intel_gpio_irq_unmask(struct irq_data *d) 744 { 745 intel_gpio_irq_mask_unmask(d, false); 746 } 747 748 static int intel_gpio_irq_type(struct irq_data *d, unsigned type) 749 { 750 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 751 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 752 unsigned pin = irqd_to_hwirq(d); 753 unsigned long flags; 754 void __iomem *reg; 755 u32 value; 756 757 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 758 if (!reg) 759 return -EINVAL; 760 761 /* 762 * If the pin is in ACPI mode it is still usable as a GPIO but it 763 * cannot be used as IRQ because GPI_IS status bit will not be 764 * updated by the host controller hardware. 765 */ 766 if (intel_pad_acpi_mode(pctrl, pin)) { 767 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 768 return -EPERM; 769 } 770 771 raw_spin_lock_irqsave(&pctrl->lock, flags); 772 773 value = readl(reg); 774 775 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); 776 777 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 778 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; 779 } else if (type & IRQ_TYPE_EDGE_FALLING) { 780 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 781 value |= PADCFG0_RXINV; 782 } else if (type & IRQ_TYPE_EDGE_RISING) { 783 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 784 } else if (type & IRQ_TYPE_LEVEL_MASK) { 785 if (type & IRQ_TYPE_LEVEL_LOW) 786 value |= PADCFG0_RXINV; 787 } else { 788 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; 789 } 790 791 writel(value, reg); 792 793 if (type & IRQ_TYPE_EDGE_BOTH) 794 irq_set_handler_locked(d, handle_edge_irq); 795 else if (type & IRQ_TYPE_LEVEL_MASK) 796 irq_set_handler_locked(d, handle_level_irq); 797 798 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 799 800 return 0; 801 } 802 803 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 804 { 805 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 806 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 807 unsigned pin = irqd_to_hwirq(d); 808 809 if (on) 810 enable_irq_wake(pctrl->irq); 811 else 812 disable_irq_wake(pctrl->irq); 813 814 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); 815 return 0; 816 } 817 818 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, 819 const struct intel_community *community) 820 { 821 struct gpio_chip *gc = &pctrl->chip; 822 irqreturn_t ret = IRQ_NONE; 823 int gpp; 824 825 for (gpp = 0; gpp < community->ngpps; gpp++) { 826 unsigned long pending, enabled, gpp_offset; 827 828 pending = readl(community->regs + GPI_IS + gpp * 4); 829 enabled = readl(community->regs + community->ie_offset + 830 gpp * 4); 831 832 /* Only interrupts that are enabled */ 833 pending &= enabled; 834 835 for_each_set_bit(gpp_offset, &pending, community->gpp_size) { 836 unsigned padno, irq; 837 838 /* 839 * The last group in community can have less pins 840 * than NPADS_IN_GPP. 841 */ 842 padno = gpp_offset + gpp * community->gpp_size; 843 if (padno >= community->npins) 844 break; 845 846 irq = irq_find_mapping(gc->irqdomain, 847 community->pin_base + padno); 848 generic_handle_irq(irq); 849 850 ret |= IRQ_HANDLED; 851 } 852 } 853 854 return ret; 855 } 856 857 static irqreturn_t intel_gpio_irq(int irq, void *data) 858 { 859 const struct intel_community *community; 860 struct intel_pinctrl *pctrl = data; 861 irqreturn_t ret = IRQ_NONE; 862 int i; 863 864 /* Need to check all communities for pending interrupts */ 865 for (i = 0; i < pctrl->ncommunities; i++) { 866 community = &pctrl->communities[i]; 867 ret |= intel_gpio_community_irq_handler(pctrl, community); 868 } 869 870 return ret; 871 } 872 873 static struct irq_chip intel_gpio_irqchip = { 874 .name = "intel-gpio", 875 .irq_enable = intel_gpio_irq_enable, 876 .irq_ack = intel_gpio_irq_ack, 877 .irq_mask = intel_gpio_irq_mask, 878 .irq_unmask = intel_gpio_irq_unmask, 879 .irq_set_type = intel_gpio_irq_type, 880 .irq_set_wake = intel_gpio_irq_wake, 881 }; 882 883 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 884 { 885 int ret; 886 887 pctrl->chip = intel_gpio_chip; 888 889 pctrl->chip.ngpio = pctrl->soc->npins; 890 pctrl->chip.label = dev_name(pctrl->dev); 891 pctrl->chip.parent = pctrl->dev; 892 pctrl->chip.base = -1; 893 pctrl->irq = irq; 894 895 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); 896 if (ret) { 897 dev_err(pctrl->dev, "failed to register gpiochip\n"); 898 return ret; 899 } 900 901 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 902 0, 0, pctrl->soc->npins); 903 if (ret) { 904 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 905 return ret; 906 } 907 908 /* 909 * We need to request the interrupt here (instead of providing chip 910 * to the irq directly) because on some platforms several GPIO 911 * controllers share the same interrupt line. 912 */ 913 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, 914 IRQF_SHARED | IRQF_NO_THREAD, 915 dev_name(pctrl->dev), pctrl); 916 if (ret) { 917 dev_err(pctrl->dev, "failed to request interrupt\n"); 918 return ret; 919 } 920 921 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, 922 handle_bad_irq, IRQ_TYPE_NONE); 923 if (ret) { 924 dev_err(pctrl->dev, "failed to add irqchip\n"); 925 return ret; 926 } 927 928 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, 929 NULL); 930 return 0; 931 } 932 933 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 934 { 935 #ifdef CONFIG_PM_SLEEP 936 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 937 struct intel_community_context *communities; 938 struct intel_pad_context *pads; 939 int i; 940 941 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 942 if (!pads) 943 return -ENOMEM; 944 945 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 946 sizeof(*communities), GFP_KERNEL); 947 if (!communities) 948 return -ENOMEM; 949 950 951 for (i = 0; i < pctrl->ncommunities; i++) { 952 struct intel_community *community = &pctrl->communities[i]; 953 u32 *intmask; 954 955 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 956 sizeof(*intmask), GFP_KERNEL); 957 if (!intmask) 958 return -ENOMEM; 959 960 communities[i].intmask = intmask; 961 } 962 963 pctrl->context.pads = pads; 964 pctrl->context.communities = communities; 965 #endif 966 967 return 0; 968 } 969 970 int intel_pinctrl_probe(struct platform_device *pdev, 971 const struct intel_pinctrl_soc_data *soc_data) 972 { 973 struct intel_pinctrl *pctrl; 974 int i, ret, irq; 975 976 if (!soc_data) 977 return -EINVAL; 978 979 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 980 if (!pctrl) 981 return -ENOMEM; 982 983 pctrl->dev = &pdev->dev; 984 pctrl->soc = soc_data; 985 raw_spin_lock_init(&pctrl->lock); 986 987 /* 988 * Make a copy of the communities which we can use to hold pointers 989 * to the registers. 990 */ 991 pctrl->ncommunities = pctrl->soc->ncommunities; 992 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, 993 sizeof(*pctrl->communities), GFP_KERNEL); 994 if (!pctrl->communities) 995 return -ENOMEM; 996 997 for (i = 0; i < pctrl->ncommunities; i++) { 998 struct intel_community *community = &pctrl->communities[i]; 999 struct resource *res; 1000 void __iomem *regs; 1001 u32 padbar; 1002 1003 *community = pctrl->soc->communities[i]; 1004 1005 res = platform_get_resource(pdev, IORESOURCE_MEM, 1006 community->barno); 1007 regs = devm_ioremap_resource(&pdev->dev, res); 1008 if (IS_ERR(regs)) 1009 return PTR_ERR(regs); 1010 1011 /* Read offset of the pad configuration registers */ 1012 padbar = readl(regs + PADBAR); 1013 1014 community->regs = regs; 1015 community->pad_regs = regs + padbar; 1016 community->ngpps = DIV_ROUND_UP(community->npins, 1017 community->gpp_size); 1018 } 1019 1020 irq = platform_get_irq(pdev, 0); 1021 if (irq < 0) { 1022 dev_err(&pdev->dev, "failed to get interrupt number\n"); 1023 return irq; 1024 } 1025 1026 ret = intel_pinctrl_pm_init(pctrl); 1027 if (ret) 1028 return ret; 1029 1030 pctrl->pctldesc = intel_pinctrl_desc; 1031 pctrl->pctldesc.name = dev_name(&pdev->dev); 1032 pctrl->pctldesc.pins = pctrl->soc->pins; 1033 pctrl->pctldesc.npins = pctrl->soc->npins; 1034 1035 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 1036 pctrl); 1037 if (IS_ERR(pctrl->pctldev)) { 1038 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1039 return PTR_ERR(pctrl->pctldev); 1040 } 1041 1042 ret = intel_gpio_probe(pctrl, irq); 1043 if (ret) 1044 return ret; 1045 1046 platform_set_drvdata(pdev, pctrl); 1047 1048 return 0; 1049 } 1050 EXPORT_SYMBOL_GPL(intel_pinctrl_probe); 1051 1052 #ifdef CONFIG_PM_SLEEP 1053 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin) 1054 { 1055 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); 1056 1057 if (!pd || !intel_pad_usable(pctrl, pin)) 1058 return false; 1059 1060 /* 1061 * Only restore the pin if it is actually in use by the kernel (or 1062 * by userspace). It is possible that some pins are used by the 1063 * BIOS during resume and those are not always locked down so leave 1064 * them alone. 1065 */ 1066 if (pd->mux_owner || pd->gpio_owner || 1067 gpiochip_line_is_irq(&pctrl->chip, pin)) 1068 return true; 1069 1070 return false; 1071 } 1072 1073 int intel_pinctrl_suspend(struct device *dev) 1074 { 1075 struct platform_device *pdev = to_platform_device(dev); 1076 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1077 struct intel_community_context *communities; 1078 struct intel_pad_context *pads; 1079 int i; 1080 1081 pads = pctrl->context.pads; 1082 for (i = 0; i < pctrl->soc->npins; i++) { 1083 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1084 u32 val; 1085 1086 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1087 continue; 1088 1089 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1090 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1091 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1092 pads[i].padcfg1 = val; 1093 } 1094 1095 communities = pctrl->context.communities; 1096 for (i = 0; i < pctrl->ncommunities; i++) { 1097 struct intel_community *community = &pctrl->communities[i]; 1098 void __iomem *base; 1099 unsigned gpp; 1100 1101 base = community->regs + community->ie_offset; 1102 for (gpp = 0; gpp < community->ngpps; gpp++) 1103 communities[i].intmask[gpp] = readl(base + gpp * 4); 1104 } 1105 1106 return 0; 1107 } 1108 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend); 1109 1110 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1111 { 1112 size_t i; 1113 1114 for (i = 0; i < pctrl->ncommunities; i++) { 1115 const struct intel_community *community; 1116 void __iomem *base; 1117 unsigned gpp; 1118 1119 community = &pctrl->communities[i]; 1120 base = community->regs; 1121 1122 for (gpp = 0; gpp < community->ngpps; gpp++) { 1123 /* Mask and clear all interrupts */ 1124 writel(0, base + community->ie_offset + gpp * 4); 1125 writel(0xffff, base + GPI_IS + gpp * 4); 1126 } 1127 } 1128 } 1129 1130 int intel_pinctrl_resume(struct device *dev) 1131 { 1132 struct platform_device *pdev = to_platform_device(dev); 1133 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1134 const struct intel_community_context *communities; 1135 const struct intel_pad_context *pads; 1136 int i; 1137 1138 /* Mask all interrupts */ 1139 intel_gpio_irq_init(pctrl); 1140 1141 pads = pctrl->context.pads; 1142 for (i = 0; i < pctrl->soc->npins; i++) { 1143 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1144 void __iomem *padcfg; 1145 u32 val; 1146 1147 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1148 continue; 1149 1150 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); 1151 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; 1152 if (val != pads[i].padcfg0) { 1153 writel(pads[i].padcfg0, padcfg); 1154 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", 1155 desc->number, readl(padcfg)); 1156 } 1157 1158 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1); 1159 val = readl(padcfg); 1160 if (val != pads[i].padcfg1) { 1161 writel(pads[i].padcfg1, padcfg); 1162 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", 1163 desc->number, readl(padcfg)); 1164 } 1165 } 1166 1167 communities = pctrl->context.communities; 1168 for (i = 0; i < pctrl->ncommunities; i++) { 1169 struct intel_community *community = &pctrl->communities[i]; 1170 void __iomem *base; 1171 unsigned gpp; 1172 1173 base = community->regs + community->ie_offset; 1174 for (gpp = 0; gpp < community->ngpps; gpp++) { 1175 writel(communities[i].intmask[gpp], base + gpp * 4); 1176 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, 1177 readl(base + gpp * 4)); 1178 } 1179 } 1180 1181 return 0; 1182 } 1183 EXPORT_SYMBOL_GPL(intel_pinctrl_resume); 1184 #endif 1185 1186 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1187 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1188 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1189 MODULE_LICENSE("GPL v2"); 1190