pci.c (67ebd8140dc8923c65451fa0f6a8eee003c4dcd3) pci.c (d92a208d086063ecc785b4588f74ab42268cbc4b)
1/*
2 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */

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3162 csr &= ~PCI_PM_CTRL_STATE_MASK;
3163 csr |= PCI_D0;
3164 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3165 pci_dev_d3_sleep(dev);
3166
3167 return 0;
3168}
3169
1/*
2 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */

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3162 csr &= ~PCI_PM_CTRL_STATE_MASK;
3163 csr |= PCI_D0;
3164 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3165 pci_dev_d3_sleep(dev);
3166
3167 return 0;
3168}
3169
3170/**
3171 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3172 * @dev: Bridge device
3173 *
3174 * Use the bridge control register to assert reset on the secondary bus.
3175 * Devices on the secondary bus are left in power-on state.
3176 */
3177void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3170void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
3178{
3179 u16 ctrl;
3180
3181 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3182 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3183 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3184 /*
3185 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double

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3194 * Trhfa for conventional PCI is 2^25 clock cycles.
3195 * Assuming a minimum 33MHz clock this results in a 1s
3196 * delay before we can consider subordinate devices to
3197 * be re-initialized. PCIe has some ways to shorten this,
3198 * but we don't make use of them yet.
3199 */
3200 ssleep(1);
3201}
3171{
3172 u16 ctrl;
3173
3174 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3175 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3176 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3177 /*
3178 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double

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3187 * Trhfa for conventional PCI is 2^25 clock cycles.
3188 * Assuming a minimum 33MHz clock this results in a 1s
3189 * delay before we can consider subordinate devices to
3190 * be re-initialized. PCIe has some ways to shorten this,
3191 * but we don't make use of them yet.
3192 */
3193 ssleep(1);
3194}
3195
3196/**
3197 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3198 * @dev: Bridge device
3199 *
3200 * Use the bridge control register to assert reset on the secondary bus.
3201 * Devices on the secondary bus are left in power-on state.
3202 */
3203void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3204{
3205 pcibios_reset_secondary_bus(dev);
3206}
3202EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3203
3204static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3205{
3206 struct pci_dev *pdev;
3207
3208 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
3209 return -ENOTTY;

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4120int pci_set_vga_state(struct pci_dev *dev, bool decode,
4121 unsigned int command_bits, u32 flags)
4122{
4123 struct pci_bus *bus;
4124 struct pci_dev *bridge;
4125 u16 cmd;
4126 int rc;
4127
3207EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3208
3209static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3210{
3211 struct pci_dev *pdev;
3212
3213 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
3214 return -ENOTTY;

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4125int pci_set_vga_state(struct pci_dev *dev, bool decode,
4126 unsigned int command_bits, u32 flags)
4127{
4128 struct pci_bus *bus;
4129 struct pci_dev *bridge;
4130 u16 cmd;
4131 int rc;
4132
4128 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4133 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4129
4130 /* ARCH specific VGA enables */
4131 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4132 if (rc)
4133 return rc;
4134
4135 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4136 pci_read_config_word(dev, PCI_COMMAND, &cmd);

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4135 /* ARCH specific VGA enables */
4136 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4137 if (rc)
4138 return rc;
4139
4140 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4141 pci_read_config_word(dev, PCI_COMMAND, &cmd);

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