sba_iommu.c (1b240f415f42204ff5a885c1c552b26a2ee780a1) sba_iommu.c (1790cf9111f61d360d861901b97eba4de3b5414c)
1/*
2** System Bus Adapter (SBA) I/O MMU manager
3**
4** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
5** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
6** (c) Copyright 2000-2004 Hewlett-Packard Company
7**
8** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)

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33#include <asm/io.h>
34#include <asm/dma.h> /* for DMA_CHUNK_SIZE */
35
36#include <asm/hardware.h> /* for register_parisc_driver() stuff */
37
38#include <linux/proc_fs.h>
39#include <linux/seq_file.h>
40
1/*
2** System Bus Adapter (SBA) I/O MMU manager
3**
4** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
5** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
6** (c) Copyright 2000-2004 Hewlett-Packard Company
7**
8** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)

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33#include <asm/io.h>
34#include <asm/dma.h> /* for DMA_CHUNK_SIZE */
35
36#include <asm/hardware.h> /* for register_parisc_driver() stuff */
37
38#include <linux/proc_fs.h>
39#include <linux/seq_file.h>
40
41#include <asm/ropes.h>
41#include <asm/mckinley.h> /* for proc_mckinley_root */
42#include <asm/runway.h> /* for proc_runway_root */
43#include <asm/pdc.h> /* for PDC_MODEL_* */
44#include <asm/pdcpat.h> /* for is_pdc_pat() */
45#include <asm/parisc-device.h>
46
47#define MODULE_NAME "SBA"
48
42#include <asm/mckinley.h> /* for proc_mckinley_root */
43#include <asm/runway.h> /* for proc_runway_root */
44#include <asm/pdc.h> /* for PDC_MODEL_* */
45#include <asm/pdcpat.h> /* for is_pdc_pat() */
46#include <asm/parisc-device.h>
47
48#define MODULE_NAME "SBA"
49
49#ifdef CONFIG_PROC_FS
50/* depends on proc fs support. But costs CPU performance */
51#undef SBA_COLLECT_STATS
52#endif
53
54/*
55** The number of debug flags is a clue - this code is fragile.
56** Don't even think about messing with it unless you have
57** plenty of 710's to sacrifice to the computer gods. :^)
58*/
59#undef DEBUG_SBA_INIT
60#undef DEBUG_SBA_RUN
61#undef DEBUG_SBA_RUN_SG

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84
85
86#ifdef DEBUG_SBA_RESOURCE
87#define DBG_RES(x...) printk(x)
88#else
89#define DBG_RES(x...)
90#endif
91
50/*
51** The number of debug flags is a clue - this code is fragile.
52** Don't even think about messing with it unless you have
53** plenty of 710's to sacrifice to the computer gods. :^)
54*/
55#undef DEBUG_SBA_INIT
56#undef DEBUG_SBA_RUN
57#undef DEBUG_SBA_RUN_SG

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80
81
82#ifdef DEBUG_SBA_RESOURCE
83#define DBG_RES(x...) printk(x)
84#else
85#define DBG_RES(x...)
86#endif
87
92#if defined(CONFIG_64BIT)
93/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
94#define ZX1_SUPPORT
95#endif
96
97#define SBA_INLINE __inline__
98
88#define SBA_INLINE __inline__
89
99
100/*
101** The number of pdir entries to "free" before issueing
102** a read to PCOM register to flush out PCOM writes.
103** Interacts with allocation granularity (ie 4 or 8 entries
104** allocated and free'd/purged at a time might make this
105** less interesting).
106*/
107#define DELAYED_RESOURCE_CNT 16
108
109#define DEFAULT_DMA_HINT_REG 0
110
90#define DEFAULT_DMA_HINT_REG 0
91
111#define ASTRO_RUNWAY_PORT 0x582
112#define IKE_MERCED_PORT 0x803
113#define REO_MERCED_PORT 0x804
114#define REOG_MERCED_PORT 0x805
115#define PLUTO_MCKINLEY_PORT 0x880
116
117#define SBA_FUNC_ID 0x0000 /* function id */
118#define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
119
92#define SBA_FUNC_ID 0x0000 /* function id */
93#define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
94
120static inline int IS_ASTRO(struct parisc_device *d) {
121 return d->id.hversion == ASTRO_RUNWAY_PORT;
122}
123
124static inline int IS_IKE(struct parisc_device *d) {
125 return d->id.hversion == IKE_MERCED_PORT;
126}
127
128static inline int IS_PLUTO(struct parisc_device *d) {
129 return d->id.hversion == PLUTO_MCKINLEY_PORT;
130}
131
132#define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
133
134#define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
135#define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
136/* Ike's IOC's occupy functions 2 and 3 */
137#define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
138
139#define IOC_CTRL 0x8 /* IOC_CTRL offset */
140#define IOC_CTRL_TC (1 << 0) /* TOC Enable */
141#define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */
142#define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
143#define IOC_CTRL_RM (1 << 8) /* Real Mode */
144#define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
145#define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
146#define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
147
95#define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
96
97#define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
98#define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
99/* Ike's IOC's occupy functions 2 and 3 */
100#define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
101
102#define IOC_CTRL 0x8 /* IOC_CTRL offset */
103#define IOC_CTRL_TC (1 << 0) /* TOC Enable */
104#define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */
105#define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
106#define IOC_CTRL_RM (1 << 8) /* Real Mode */
107#define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
108#define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
109#define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
110
148#define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
149
111
150#define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
151
152
153/*
154** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
155** Firmware programs this stuff. Don't touch it.
156*/
157#define LMMIO_DIRECT0_BASE 0x300
158#define LMMIO_DIRECT0_MASK 0x308
159#define LMMIO_DIRECT0_ROUTE 0x310
160

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191
192
193#define IOC_IBASE 0x300 /* IO TLB */
194#define IOC_IMASK 0x308
195#define IOC_PCOM 0x310
196#define IOC_TCNFG 0x318
197#define IOC_PDIR_BASE 0x320
198
112/*
113** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
114** Firmware programs this stuff. Don't touch it.
115*/
116#define LMMIO_DIRECT0_BASE 0x300
117#define LMMIO_DIRECT0_MASK 0x308
118#define LMMIO_DIRECT0_ROUTE 0x310
119

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150
151
152#define IOC_IBASE 0x300 /* IO TLB */
153#define IOC_IMASK 0x308
154#define IOC_PCOM 0x310
155#define IOC_TCNFG 0x318
156#define IOC_PDIR_BASE 0x320
157
199/* AGP GART driver looks for this */
200#define SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
201
158
202
203/*
204** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
205** It's safer (avoid memory corruption) to keep DMA page mappings
206** equivalently sized to VM PAGE_SIZE.
207**
208** We really can't avoid generating a new mapping for each
209** page since the Virtual Coherence Index has to be generated
210** and updated for each page.

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223/*
224** Offsets into PCI Performance Counters (functions 12 and 13)
225** Controlled by PERF registers in function 2 & 3 respectively.
226*/
227#define SBA_PERF_CNT1 0x200
228#define SBA_PERF_CNT2 0x208
229#define SBA_PERF_CNT3 0x210
230
159/*
160** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
161** It's safer (avoid memory corruption) to keep DMA page mappings
162** equivalently sized to VM PAGE_SIZE.
163**
164** We really can't avoid generating a new mapping for each
165** page since the Virtual Coherence Index has to be generated
166** and updated for each page.

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179/*
180** Offsets into PCI Performance Counters (functions 12 and 13)
181** Controlled by PERF registers in function 2 & 3 respectively.
182*/
183#define SBA_PERF_CNT1 0x200
184#define SBA_PERF_CNT2 0x208
185#define SBA_PERF_CNT3 0x210
186
231
232struct ioc {
233 void __iomem *ioc_hpa; /* I/O MMU base address */
234 char *res_map; /* resource map, bit == pdir entry */
235 u64 *pdir_base; /* physical base address */
236 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
237 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
238#ifdef ZX1_SUPPORT
239 unsigned long iovp_mask; /* help convert IOVA to IOVP */
240#endif
241 unsigned long *res_hint; /* next avail IOVP - circular search */
242 spinlock_t res_lock;
243 unsigned int res_bitshift; /* from the LEFT! */
244 unsigned int res_size; /* size of resource map in bytes */
245#ifdef SBA_HINT_SUPPORT
246/* FIXME : DMA HINTs not used */
247 unsigned long hint_mask_pdir; /* bits used for DMA hints */
248 unsigned int hint_shift_pdir;
249#endif
250#if DELAYED_RESOURCE_CNT > 0
251 int saved_cnt;
252 struct sba_dma_pair {
253 dma_addr_t iova;
254 size_t size;
255 } saved[DELAYED_RESOURCE_CNT];
256#endif
257
258#ifdef SBA_COLLECT_STATS
259#define SBA_SEARCH_SAMPLE 0x100
260 unsigned long avg_search[SBA_SEARCH_SAMPLE];
261 unsigned long avg_idx; /* current index into avg_search */
262 unsigned long used_pages;
263 unsigned long msingle_calls;
264 unsigned long msingle_pages;
265 unsigned long msg_calls;
266 unsigned long msg_pages;
267 unsigned long usingle_calls;
268 unsigned long usingle_pages;
269 unsigned long usg_calls;
270 unsigned long usg_pages;
271#endif
272
273 /* STUFF We don't need in performance path */
274 unsigned int pdir_size; /* in bytes, determined by IOV Space size */
275};
276
277struct sba_device {
278 struct sba_device *next; /* list of SBA's in system */
279 struct parisc_device *dev; /* dev found in bus walk */
280 const char *name;
281 void __iomem *sba_hpa; /* base address */
282 spinlock_t sba_lock;
283 unsigned int flags; /* state/functionality enabled */
284 unsigned int hw_rev; /* HW revision of chip */
285
286 struct resource chip_resv; /* MMIO reserved for chip */
287 struct resource iommu_resv; /* MMIO reserved for iommu */
288
289 unsigned int num_ioc; /* number of on-board IOC's */
290 struct ioc ioc[MAX_IOC];
291};
292
293
294static struct sba_device *sba_list;
295
296static unsigned long ioc_needs_fdc = 0;
297
298/* global count of IOMMUs in the system */
299static unsigned int global_ioc_cnt = 0;
300
301/* PA8700 (Piranha 2.2) bug workaround */

--- 1959 unchanged lines hidden --- 		187static struct sba_device *sba_list;
188
189static unsigned long ioc_needs_fdc = 0;
190
191/* global count of IOMMUs in the system */
192static unsigned int global_ioc_cnt = 0;
193
194/* PA8700 (Piranha 2.2) bug workaround */

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