1 /* 2 ** System Bus Adapter (SBA) I/O MMU manager 3 ** 4 ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org> 5 ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com> 6 ** (c) Copyright 2000-2004 Hewlett-Packard Company 7 ** 8 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code) 9 ** 10 ** This program is free software; you can redistribute it and/or modify 11 ** it under the terms of the GNU General Public License as published by 12 ** the Free Software Foundation; either version 2 of the License, or 13 ** (at your option) any later version. 14 ** 15 ** 16 ** This module initializes the IOC (I/O Controller) found on B1000/C3000/ 17 ** J5000/J7000/N-class/L-class machines and their successors. 18 ** 19 ** FIXME: add DMA hint support programming in both sba and lba modules. 20 */ 21 22 #include <linux/types.h> 23 #include <linux/kernel.h> 24 #include <linux/spinlock.h> 25 #include <linux/slab.h> 26 #include <linux/init.h> 27 28 #include <linux/mm.h> 29 #include <linux/string.h> 30 #include <linux/pci.h> 31 32 #include <asm/byteorder.h> 33 #include <asm/io.h> 34 #include <asm/dma.h> /* for DMA_CHUNK_SIZE */ 35 36 #include <asm/hardware.h> /* for register_parisc_driver() stuff */ 37 38 #include <linux/proc_fs.h> 39 #include <linux/seq_file.h> 40 41 #include <asm/ropes.h> 42 #include <asm/mckinley.h> /* for proc_mckinley_root */ 43 #include <asm/runway.h> /* for proc_runway_root */ 44 #include <asm/pdc.h> /* for PDC_MODEL_* */ 45 #include <asm/pdcpat.h> /* for is_pdc_pat() */ 46 #include <asm/parisc-device.h> 47 48 #define MODULE_NAME "SBA" 49 50 /* 51 ** The number of debug flags is a clue - this code is fragile. 52 ** Don't even think about messing with it unless you have 53 ** plenty of 710's to sacrifice to the computer gods. :^) 54 */ 55 #undef DEBUG_SBA_INIT 56 #undef DEBUG_SBA_RUN 57 #undef DEBUG_SBA_RUN_SG 58 #undef DEBUG_SBA_RESOURCE 59 #undef ASSERT_PDIR_SANITY 60 #undef DEBUG_LARGE_SG_ENTRIES 61 #undef DEBUG_DMB_TRAP 62 63 #ifdef DEBUG_SBA_INIT 64 #define DBG_INIT(x...) printk(x) 65 #else 66 #define DBG_INIT(x...) 67 #endif 68 69 #ifdef DEBUG_SBA_RUN 70 #define DBG_RUN(x...) printk(x) 71 #else 72 #define DBG_RUN(x...) 73 #endif 74 75 #ifdef DEBUG_SBA_RUN_SG 76 #define DBG_RUN_SG(x...) printk(x) 77 #else 78 #define DBG_RUN_SG(x...) 79 #endif 80 81 82 #ifdef DEBUG_SBA_RESOURCE 83 #define DBG_RES(x...) printk(x) 84 #else 85 #define DBG_RES(x...) 86 #endif 87 88 #define SBA_INLINE __inline__ 89 90 #define DEFAULT_DMA_HINT_REG 0 91 92 #define SBA_FUNC_ID 0x0000 /* function id */ 93 #define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */ 94 95 #define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */ 96 97 #define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE) 98 #define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE) 99 /* Ike's IOC's occupy functions 2 and 3 */ 100 #define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE) 101 102 #define IOC_CTRL 0x8 /* IOC_CTRL offset */ 103 #define IOC_CTRL_TC (1 << 0) /* TOC Enable */ 104 #define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */ 105 #define IOC_CTRL_DE (1 << 2) /* Dillon Enable */ 106 #define IOC_CTRL_RM (1 << 8) /* Real Mode */ 107 #define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */ 108 #define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */ 109 #define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */ 110 111 112 /* 113 ** Offsets into MBIB (Function 0 on Ike and hopefully Astro) 114 ** Firmware programs this stuff. Don't touch it. 115 */ 116 #define LMMIO_DIRECT0_BASE 0x300 117 #define LMMIO_DIRECT0_MASK 0x308 118 #define LMMIO_DIRECT0_ROUTE 0x310 119 120 #define LMMIO_DIST_BASE 0x360 121 #define LMMIO_DIST_MASK 0x368 122 #define LMMIO_DIST_ROUTE 0x370 123 124 #define IOS_DIST_BASE 0x390 125 #define IOS_DIST_MASK 0x398 126 #define IOS_DIST_ROUTE 0x3A0 127 128 #define IOS_DIRECT_BASE 0x3C0 129 #define IOS_DIRECT_MASK 0x3C8 130 #define IOS_DIRECT_ROUTE 0x3D0 131 132 /* 133 ** Offsets into I/O TLB (Function 2 and 3 on Ike) 134 */ 135 #define ROPE0_CTL 0x200 /* "regbus pci0" */ 136 #define ROPE1_CTL 0x208 137 #define ROPE2_CTL 0x210 138 #define ROPE3_CTL 0x218 139 #define ROPE4_CTL 0x220 140 #define ROPE5_CTL 0x228 141 #define ROPE6_CTL 0x230 142 #define ROPE7_CTL 0x238 143 144 #define IOC_ROPE0_CFG 0x500 /* pluto only */ 145 #define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */ 146 147 148 149 #define HF_ENABLE 0x40 150 151 152 #define IOC_IBASE 0x300 /* IO TLB */ 153 #define IOC_IMASK 0x308 154 #define IOC_PCOM 0x310 155 #define IOC_TCNFG 0x318 156 #define IOC_PDIR_BASE 0x320 157 158 159 /* 160 ** IOC supports 4/8/16/64KB page sizes (see TCNFG register) 161 ** It's safer (avoid memory corruption) to keep DMA page mappings 162 ** equivalently sized to VM PAGE_SIZE. 163 ** 164 ** We really can't avoid generating a new mapping for each 165 ** page since the Virtual Coherence Index has to be generated 166 ** and updated for each page. 167 ** 168 ** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse. 169 */ 170 #define IOVP_SIZE PAGE_SIZE 171 #define IOVP_SHIFT PAGE_SHIFT 172 #define IOVP_MASK PAGE_MASK 173 174 #define SBA_PERF_CFG 0x708 /* Performance Counter stuff */ 175 #define SBA_PERF_MASK1 0x718 176 #define SBA_PERF_MASK2 0x730 177 178 179 /* 180 ** Offsets into PCI Performance Counters (functions 12 and 13) 181 ** Controlled by PERF registers in function 2 & 3 respectively. 182 */ 183 #define SBA_PERF_CNT1 0x200 184 #define SBA_PERF_CNT2 0x208 185 #define SBA_PERF_CNT3 0x210 186 187 static struct sba_device *sba_list; 188 189 static unsigned long ioc_needs_fdc = 0; 190 191 /* global count of IOMMUs in the system */ 192 static unsigned int global_ioc_cnt = 0; 193 194 /* PA8700 (Piranha 2.2) bug workaround */ 195 static unsigned long piranha_bad_128k = 0; 196 197 /* Looks nice and keeps the compiler happy */ 198 #define SBA_DEV(d) ((struct sba_device *) (d)) 199 200 #ifdef SBA_AGP_SUPPORT 201 static int reserve_sba_gart = 1; 202 #endif 203 204 #define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1)) 205 206 207 /************************************ 208 ** SBA register read and write support 209 ** 210 ** BE WARNED: register writes are posted. 211 ** (ie follow writes which must reach HW with a read) 212 ** 213 ** Superdome (in particular, REO) allows only 64-bit CSR accesses. 214 */ 215 #define READ_REG32(addr) readl(addr) 216 #define READ_REG64(addr) readq(addr) 217 #define WRITE_REG32(val, addr) writel((val), (addr)) 218 #define WRITE_REG64(val, addr) writeq((val), (addr)) 219 220 #ifdef CONFIG_64BIT 221 #define READ_REG(addr) READ_REG64(addr) 222 #define WRITE_REG(value, addr) WRITE_REG64(value, addr) 223 #else 224 #define READ_REG(addr) READ_REG32(addr) 225 #define WRITE_REG(value, addr) WRITE_REG32(value, addr) 226 #endif 227 228 #ifdef DEBUG_SBA_INIT 229 230 /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */ 231 232 /** 233 * sba_dump_ranges - debugging only - print ranges assigned to this IOA 234 * @hpa: base address of the sba 235 * 236 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO 237 * IO Adapter (aka Bus Converter). 238 */ 239 static void 240 sba_dump_ranges(void __iomem *hpa) 241 { 242 DBG_INIT("SBA at 0x%p\n", hpa); 243 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE)); 244 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK)); 245 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE)); 246 DBG_INIT("\n"); 247 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE)); 248 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK)); 249 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE)); 250 } 251 252 /** 253 * sba_dump_tlb - debugging only - print IOMMU operating parameters 254 * @hpa: base address of the IOMMU 255 * 256 * Print the size/location of the IO MMU PDIR. 257 */ 258 static void sba_dump_tlb(void __iomem *hpa) 259 { 260 DBG_INIT("IO TLB at 0x%p\n", hpa); 261 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE)); 262 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK)); 263 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG)); 264 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE)); 265 DBG_INIT("\n"); 266 } 267 #else 268 #define sba_dump_ranges(x) 269 #define sba_dump_tlb(x) 270 #endif /* DEBUG_SBA_INIT */ 271 272 273 #ifdef ASSERT_PDIR_SANITY 274 275 /** 276 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry 277 * @ioc: IO MMU structure which owns the pdir we are interested in. 278 * @msg: text to print ont the output line. 279 * @pide: pdir index. 280 * 281 * Print one entry of the IO MMU PDIR in human readable form. 282 */ 283 static void 284 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide) 285 { 286 /* start printing from lowest pde in rval */ 287 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]); 288 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]); 289 uint rcnt; 290 291 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n", 292 msg, 293 rptr, pide & (BITS_PER_LONG - 1), *rptr); 294 295 rcnt = 0; 296 while (rcnt < BITS_PER_LONG) { 297 printk(KERN_DEBUG "%s %2d %p %016Lx\n", 298 (rcnt == (pide & (BITS_PER_LONG - 1))) 299 ? " -->" : " ", 300 rcnt, ptr, *ptr ); 301 rcnt++; 302 ptr++; 303 } 304 printk(KERN_DEBUG "%s", msg); 305 } 306 307 308 /** 309 * sba_check_pdir - debugging only - consistency checker 310 * @ioc: IO MMU structure which owns the pdir we are interested in. 311 * @msg: text to print ont the output line. 312 * 313 * Verify the resource map and pdir state is consistent 314 */ 315 static int 316 sba_check_pdir(struct ioc *ioc, char *msg) 317 { 318 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]); 319 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */ 320 u64 *pptr = ioc->pdir_base; /* pdir ptr */ 321 uint pide = 0; 322 323 while (rptr < rptr_end) { 324 u32 rval = *rptr; 325 int rcnt = 32; /* number of bits we might check */ 326 327 while (rcnt) { 328 /* Get last byte and highest bit from that */ 329 u32 pde = ((u32) (((char *)pptr)[7])) << 24; 330 if ((rval ^ pde) & 0x80000000) 331 { 332 /* 333 ** BUMMER! -- res_map != pdir -- 334 ** Dump rval and matching pdir entries 335 */ 336 sba_dump_pdir_entry(ioc, msg, pide); 337 return(1); 338 } 339 rcnt--; 340 rval <<= 1; /* try the next bit */ 341 pptr++; 342 pide++; 343 } 344 rptr++; /* look at next word of res_map */ 345 } 346 /* It'd be nice if we always got here :^) */ 347 return 0; 348 } 349 350 351 /** 352 * sba_dump_sg - debugging only - print Scatter-Gather list 353 * @ioc: IO MMU structure which owns the pdir we are interested in. 354 * @startsg: head of the SG list 355 * @nents: number of entries in SG list 356 * 357 * print the SG list so we can verify it's correct by hand. 358 */ 359 static void 360 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents) 361 { 362 while (nents-- > 0) { 363 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n", 364 nents, 365 (unsigned long) sg_dma_address(startsg), 366 sg_dma_len(startsg), 367 sg_virt_addr(startsg), startsg->length); 368 startsg++; 369 } 370 } 371 372 #endif /* ASSERT_PDIR_SANITY */ 373 374 375 376 377 /************************************************************** 378 * 379 * I/O Pdir Resource Management 380 * 381 * Bits set in the resource map are in use. 382 * Each bit can represent a number of pages. 383 * LSbs represent lower addresses (IOVA's). 384 * 385 ***************************************************************/ 386 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */ 387 388 /* Convert from IOVP to IOVA and vice versa. */ 389 390 #ifdef ZX1_SUPPORT 391 /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */ 392 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset)) 393 #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask) 394 #else 395 /* only support Astro and ancestors. Saves a few cycles in key places */ 396 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset)) 397 #define SBA_IOVP(ioc,iova) (iova) 398 #endif 399 400 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT) 401 402 #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n))) 403 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1) 404 405 406 /** 407 * sba_search_bitmap - find free space in IO PDIR resource bitmap 408 * @ioc: IO MMU structure which owns the pdir we are interested in. 409 * @bits_wanted: number of entries we need. 410 * 411 * Find consecutive free bits in resource bitmap. 412 * Each bit represents one entry in the IO Pdir. 413 * Cool perf optimization: search for log2(size) bits at a time. 414 */ 415 static SBA_INLINE unsigned long 416 sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted) 417 { 418 unsigned long *res_ptr = ioc->res_hint; 419 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]); 420 unsigned long pide = ~0UL; 421 422 if (bits_wanted > (BITS_PER_LONG/2)) { 423 /* Search word at a time - no mask needed */ 424 for(; res_ptr < res_end; ++res_ptr) { 425 if (*res_ptr == 0) { 426 *res_ptr = RESMAP_MASK(bits_wanted); 427 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map); 428 pide <<= 3; /* convert to bit address */ 429 break; 430 } 431 } 432 /* point to the next word on next pass */ 433 res_ptr++; 434 ioc->res_bitshift = 0; 435 } else { 436 /* 437 ** Search the resource bit map on well-aligned values. 438 ** "o" is the alignment. 439 ** We need the alignment to invalidate I/O TLB using 440 ** SBA HW features in the unmap path. 441 */ 442 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT); 443 uint bitshiftcnt = ROUNDUP(ioc->res_bitshift, o); 444 unsigned long mask; 445 446 if (bitshiftcnt >= BITS_PER_LONG) { 447 bitshiftcnt = 0; 448 res_ptr++; 449 } 450 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt; 451 452 DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr); 453 while(res_ptr < res_end) 454 { 455 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr); 456 WARN_ON(mask == 0); 457 if(((*res_ptr) & mask) == 0) { 458 *res_ptr |= mask; /* mark resources busy! */ 459 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map); 460 pide <<= 3; /* convert to bit address */ 461 pide += bitshiftcnt; 462 break; 463 } 464 mask >>= o; 465 bitshiftcnt += o; 466 if (mask == 0) { 467 mask = RESMAP_MASK(bits_wanted); 468 bitshiftcnt=0; 469 res_ptr++; 470 } 471 } 472 /* look in the same word on the next pass */ 473 ioc->res_bitshift = bitshiftcnt + bits_wanted; 474 } 475 476 /* wrapped ? */ 477 if (res_end <= res_ptr) { 478 ioc->res_hint = (unsigned long *) ioc->res_map; 479 ioc->res_bitshift = 0; 480 } else { 481 ioc->res_hint = res_ptr; 482 } 483 return (pide); 484 } 485 486 487 /** 488 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap 489 * @ioc: IO MMU structure which owns the pdir we are interested in. 490 * @size: number of bytes to create a mapping for 491 * 492 * Given a size, find consecutive unmarked and then mark those bits in the 493 * resource bit map. 494 */ 495 static int 496 sba_alloc_range(struct ioc *ioc, size_t size) 497 { 498 unsigned int pages_needed = size >> IOVP_SHIFT; 499 #ifdef SBA_COLLECT_STATS 500 unsigned long cr_start = mfctl(16); 501 #endif 502 unsigned long pide; 503 504 pide = sba_search_bitmap(ioc, pages_needed); 505 if (pide >= (ioc->res_size << 3)) { 506 pide = sba_search_bitmap(ioc, pages_needed); 507 if (pide >= (ioc->res_size << 3)) 508 panic("%s: I/O MMU @ %p is out of mapping resources\n", 509 __FILE__, ioc->ioc_hpa); 510 } 511 512 #ifdef ASSERT_PDIR_SANITY 513 /* verify the first enable bit is clear */ 514 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) { 515 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide); 516 } 517 #endif 518 519 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n", 520 __FUNCTION__, size, pages_needed, pide, 521 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map), 522 ioc->res_bitshift ); 523 524 #ifdef SBA_COLLECT_STATS 525 { 526 unsigned long cr_end = mfctl(16); 527 unsigned long tmp = cr_end - cr_start; 528 /* check for roll over */ 529 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp); 530 } 531 ioc->avg_search[ioc->avg_idx++] = cr_start; 532 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1; 533 534 ioc->used_pages += pages_needed; 535 #endif 536 537 return (pide); 538 } 539 540 541 /** 542 * sba_free_range - unmark bits in IO PDIR resource bitmap 543 * @ioc: IO MMU structure which owns the pdir we are interested in. 544 * @iova: IO virtual address which was previously allocated. 545 * @size: number of bytes to create a mapping for 546 * 547 * clear bits in the ioc's resource map 548 */ 549 static SBA_INLINE void 550 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size) 551 { 552 unsigned long iovp = SBA_IOVP(ioc, iova); 553 unsigned int pide = PDIR_INDEX(iovp); 554 unsigned int ridx = pide >> 3; /* convert bit to byte address */ 555 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]); 556 557 int bits_not_wanted = size >> IOVP_SHIFT; 558 559 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */ 560 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1)); 561 562 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n", 563 __FUNCTION__, (uint) iova, size, 564 bits_not_wanted, m, pide, res_ptr, *res_ptr); 565 566 #ifdef SBA_COLLECT_STATS 567 ioc->used_pages -= bits_not_wanted; 568 #endif 569 570 *res_ptr &= ~m; 571 } 572 573 574 /************************************************************** 575 * 576 * "Dynamic DMA Mapping" support (aka "Coherent I/O") 577 * 578 ***************************************************************/ 579 580 #ifdef SBA_HINT_SUPPORT 581 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir) 582 #endif 583 584 typedef unsigned long space_t; 585 #define KERNEL_SPACE 0 586 587 /** 588 * sba_io_pdir_entry - fill in one IO PDIR entry 589 * @pdir_ptr: pointer to IO PDIR entry 590 * @sid: process Space ID - currently only support KERNEL_SPACE 591 * @vba: Virtual CPU address of buffer to map 592 * @hint: DMA hint set to use for this mapping 593 * 594 * SBA Mapping Routine 595 * 596 * Given a virtual address (vba, arg2) and space id, (sid, arg1) 597 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by 598 * pdir_ptr (arg0). 599 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry 600 * for Astro/Ike looks like: 601 * 602 * 603 * 0 19 51 55 63 604 * +-+---------------------+----------------------------------+----+--------+ 605 * |V| U | PPN[43:12] | U | VI | 606 * +-+---------------------+----------------------------------+----+--------+ 607 * 608 * Pluto is basically identical, supports fewer physical address bits: 609 * 610 * 0 23 51 55 63 611 * +-+------------------------+-------------------------------+----+--------+ 612 * |V| U | PPN[39:12] | U | VI | 613 * +-+------------------------+-------------------------------+----+--------+ 614 * 615 * V == Valid Bit (Most Significant Bit is bit 0) 616 * U == Unused 617 * PPN == Physical Page Number 618 * VI == Virtual Index (aka Coherent Index) 619 * 620 * LPA instruction output is put into PPN field. 621 * LCI (Load Coherence Index) instruction provides the "VI" bits. 622 * 623 * We pre-swap the bytes since PCX-W is Big Endian and the 624 * IOMMU uses little endian for the pdir. 625 */ 626 627 void SBA_INLINE 628 sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba, 629 unsigned long hint) 630 { 631 u64 pa; /* physical address */ 632 register unsigned ci; /* coherent index */ 633 634 pa = virt_to_phys(vba); 635 pa &= IOVP_MASK; 636 637 mtsp(sid,1); 638 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba)); 639 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */ 640 641 pa |= 0x8000000000000000ULL; /* set "valid" bit */ 642 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */ 643 644 /* 645 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set 646 * (bit #61, big endian), we have to flush and sync every time 647 * IO-PDIR is changed in Ike/Astro. 648 */ 649 if (ioc_needs_fdc) 650 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); 651 } 652 653 654 /** 655 * sba_mark_invalid - invalidate one or more IO PDIR entries 656 * @ioc: IO MMU structure which owns the pdir we are interested in. 657 * @iova: IO Virtual Address mapped earlier 658 * @byte_cnt: number of bytes this mapping covers. 659 * 660 * Marking the IO PDIR entry(ies) as Invalid and invalidate 661 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register) 662 * is to purge stale entries in the IO TLB when unmapping entries. 663 * 664 * The PCOM register supports purging of multiple pages, with a minium 665 * of 1 page and a maximum of 2GB. Hardware requires the address be 666 * aligned to the size of the range being purged. The size of the range 667 * must be a power of 2. The "Cool perf optimization" in the 668 * allocation routine helps keep that true. 669 */ 670 static SBA_INLINE void 671 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) 672 { 673 u32 iovp = (u32) SBA_IOVP(ioc,iova); 674 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)]; 675 676 #ifdef ASSERT_PDIR_SANITY 677 /* Assert first pdir entry is set. 678 ** 679 ** Even though this is a big-endian machine, the entries 680 ** in the iopdir are little endian. That's why we look at 681 ** the byte at +7 instead of at +0. 682 */ 683 if (0x80 != (((u8 *) pdir_ptr)[7])) { 684 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp)); 685 } 686 #endif 687 688 if (byte_cnt > IOVP_SIZE) 689 { 690 #if 0 691 unsigned long entries_per_cacheline = ioc_needs_fdc ? 692 L1_CACHE_ALIGN(((unsigned long) pdir_ptr)) 693 - (unsigned long) pdir_ptr; 694 : 262144; 695 #endif 696 697 /* set "size" field for PCOM */ 698 iovp |= get_order(byte_cnt) + PAGE_SHIFT; 699 700 do { 701 /* clear I/O Pdir entry "valid" bit first */ 702 ((u8 *) pdir_ptr)[7] = 0; 703 if (ioc_needs_fdc) { 704 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); 705 #if 0 706 entries_per_cacheline = L1_CACHE_SHIFT - 3; 707 #endif 708 } 709 pdir_ptr++; 710 byte_cnt -= IOVP_SIZE; 711 } while (byte_cnt > IOVP_SIZE); 712 } else 713 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */ 714 715 /* 716 ** clear I/O PDIR entry "valid" bit. 717 ** We have to R/M/W the cacheline regardless how much of the 718 ** pdir entry that we clobber. 719 ** The rest of the entry would be useful for debugging if we 720 ** could dump core on HPMC. 721 */ 722 ((u8 *) pdir_ptr)[7] = 0; 723 if (ioc_needs_fdc) 724 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); 725 726 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM); 727 } 728 729 /** 730 * sba_dma_supported - PCI driver can query DMA support 731 * @dev: instance of PCI owned by the driver that's asking 732 * @mask: number of address bits this PCI device can handle 733 * 734 * See Documentation/DMA-mapping.txt 735 */ 736 static int sba_dma_supported( struct device *dev, u64 mask) 737 { 738 struct ioc *ioc; 739 740 if (dev == NULL) { 741 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n"); 742 BUG(); 743 return(0); 744 } 745 746 /* Documentation/DMA-mapping.txt tells drivers to try 64-bit first, 747 * then fall back to 32-bit if that fails. 748 * We are just "encouraging" 32-bit DMA masks here since we can 749 * never allow IOMMU bypass unless we add special support for ZX1. 750 */ 751 if (mask > ~0U) 752 return 0; 753 754 ioc = GET_IOC(dev); 755 756 /* 757 * check if mask is >= than the current max IO Virt Address 758 * The max IO Virt address will *always* < 30 bits. 759 */ 760 return((int)(mask >= (ioc->ibase - 1 + 761 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) ))); 762 } 763 764 765 /** 766 * sba_map_single - map one buffer and return IOVA for DMA 767 * @dev: instance of PCI owned by the driver that's asking. 768 * @addr: driver buffer to map. 769 * @size: number of bytes to map in driver buffer. 770 * @direction: R/W or both. 771 * 772 * See Documentation/DMA-mapping.txt 773 */ 774 static dma_addr_t 775 sba_map_single(struct device *dev, void *addr, size_t size, 776 enum dma_data_direction direction) 777 { 778 struct ioc *ioc; 779 unsigned long flags; 780 dma_addr_t iovp; 781 dma_addr_t offset; 782 u64 *pdir_start; 783 int pide; 784 785 ioc = GET_IOC(dev); 786 787 /* save offset bits */ 788 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK; 789 790 /* round up to nearest IOVP_SIZE */ 791 size = (size + offset + ~IOVP_MASK) & IOVP_MASK; 792 793 spin_lock_irqsave(&ioc->res_lock, flags); 794 #ifdef ASSERT_PDIR_SANITY 795 sba_check_pdir(ioc,"Check before sba_map_single()"); 796 #endif 797 798 #ifdef SBA_COLLECT_STATS 799 ioc->msingle_calls++; 800 ioc->msingle_pages += size >> IOVP_SHIFT; 801 #endif 802 pide = sba_alloc_range(ioc, size); 803 iovp = (dma_addr_t) pide << IOVP_SHIFT; 804 805 DBG_RUN("%s() 0x%p -> 0x%lx\n", 806 __FUNCTION__, addr, (long) iovp | offset); 807 808 pdir_start = &(ioc->pdir_base[pide]); 809 810 while (size > 0) { 811 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0); 812 813 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n", 814 pdir_start, 815 (u8) (((u8 *) pdir_start)[7]), 816 (u8) (((u8 *) pdir_start)[6]), 817 (u8) (((u8 *) pdir_start)[5]), 818 (u8) (((u8 *) pdir_start)[4]), 819 (u8) (((u8 *) pdir_start)[3]), 820 (u8) (((u8 *) pdir_start)[2]), 821 (u8) (((u8 *) pdir_start)[1]), 822 (u8) (((u8 *) pdir_start)[0]) 823 ); 824 825 addr += IOVP_SIZE; 826 size -= IOVP_SIZE; 827 pdir_start++; 828 } 829 830 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ 831 if (ioc_needs_fdc) 832 asm volatile("sync" : : ); 833 834 #ifdef ASSERT_PDIR_SANITY 835 sba_check_pdir(ioc,"Check after sba_map_single()"); 836 #endif 837 spin_unlock_irqrestore(&ioc->res_lock, flags); 838 839 /* form complete address */ 840 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG); 841 } 842 843 844 /** 845 * sba_unmap_single - unmap one IOVA and free resources 846 * @dev: instance of PCI owned by the driver that's asking. 847 * @iova: IOVA of driver buffer previously mapped. 848 * @size: number of bytes mapped in driver buffer. 849 * @direction: R/W or both. 850 * 851 * See Documentation/DMA-mapping.txt 852 */ 853 static void 854 sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size, 855 enum dma_data_direction direction) 856 { 857 struct ioc *ioc; 858 #if DELAYED_RESOURCE_CNT > 0 859 struct sba_dma_pair *d; 860 #endif 861 unsigned long flags; 862 dma_addr_t offset; 863 864 DBG_RUN("%s() iovp 0x%lx/%x\n", __FUNCTION__, (long) iova, size); 865 866 ioc = GET_IOC(dev); 867 offset = iova & ~IOVP_MASK; 868 iova ^= offset; /* clear offset bits */ 869 size += offset; 870 size = ROUNDUP(size, IOVP_SIZE); 871 872 spin_lock_irqsave(&ioc->res_lock, flags); 873 874 #ifdef SBA_COLLECT_STATS 875 ioc->usingle_calls++; 876 ioc->usingle_pages += size >> IOVP_SHIFT; 877 #endif 878 879 sba_mark_invalid(ioc, iova, size); 880 881 #if DELAYED_RESOURCE_CNT > 0 882 /* Delaying when we re-use a IO Pdir entry reduces the number 883 * of MMIO reads needed to flush writes to the PCOM register. 884 */ 885 d = &(ioc->saved[ioc->saved_cnt]); 886 d->iova = iova; 887 d->size = size; 888 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) { 889 int cnt = ioc->saved_cnt; 890 while (cnt--) { 891 sba_free_range(ioc, d->iova, d->size); 892 d--; 893 } 894 ioc->saved_cnt = 0; 895 896 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ 897 } 898 #else /* DELAYED_RESOURCE_CNT == 0 */ 899 sba_free_range(ioc, iova, size); 900 901 /* If fdc's were issued, force fdc's to be visible now */ 902 if (ioc_needs_fdc) 903 asm volatile("sync" : : ); 904 905 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ 906 #endif /* DELAYED_RESOURCE_CNT == 0 */ 907 908 spin_unlock_irqrestore(&ioc->res_lock, flags); 909 910 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support. 911 ** For Astro based systems this isn't a big deal WRT performance. 912 ** As long as 2.4 kernels copyin/copyout data from/to userspace, 913 ** we don't need the syncdma. The issue here is I/O MMU cachelines 914 ** are *not* coherent in all cases. May be hwrev dependent. 915 ** Need to investigate more. 916 asm volatile("syncdma"); 917 */ 918 } 919 920 921 /** 922 * sba_alloc_consistent - allocate/map shared mem for DMA 923 * @hwdev: instance of PCI owned by the driver that's asking. 924 * @size: number of bytes mapped in driver buffer. 925 * @dma_handle: IOVA of new buffer. 926 * 927 * See Documentation/DMA-mapping.txt 928 */ 929 static void *sba_alloc_consistent(struct device *hwdev, size_t size, 930 dma_addr_t *dma_handle, gfp_t gfp) 931 { 932 void *ret; 933 934 if (!hwdev) { 935 /* only support PCI */ 936 *dma_handle = 0; 937 return 0; 938 } 939 940 ret = (void *) __get_free_pages(gfp, get_order(size)); 941 942 if (ret) { 943 memset(ret, 0, size); 944 *dma_handle = sba_map_single(hwdev, ret, size, 0); 945 } 946 947 return ret; 948 } 949 950 951 /** 952 * sba_free_consistent - free/unmap shared mem for DMA 953 * @hwdev: instance of PCI owned by the driver that's asking. 954 * @size: number of bytes mapped in driver buffer. 955 * @vaddr: virtual address IOVA of "consistent" buffer. 956 * @dma_handler: IO virtual address of "consistent" buffer. 957 * 958 * See Documentation/DMA-mapping.txt 959 */ 960 static void 961 sba_free_consistent(struct device *hwdev, size_t size, void *vaddr, 962 dma_addr_t dma_handle) 963 { 964 sba_unmap_single(hwdev, dma_handle, size, 0); 965 free_pages((unsigned long) vaddr, get_order(size)); 966 } 967 968 969 /* 970 ** Since 0 is a valid pdir_base index value, can't use that 971 ** to determine if a value is valid or not. Use a flag to indicate 972 ** the SG list entry contains a valid pdir index. 973 */ 974 #define PIDE_FLAG 0x80000000UL 975 976 #ifdef SBA_COLLECT_STATS 977 #define IOMMU_MAP_STATS 978 #endif 979 #include "iommu-helpers.h" 980 981 #ifdef DEBUG_LARGE_SG_ENTRIES 982 int dump_run_sg = 0; 983 #endif 984 985 986 /** 987 * sba_map_sg - map Scatter/Gather list 988 * @dev: instance of PCI owned by the driver that's asking. 989 * @sglist: array of buffer/length pairs 990 * @nents: number of entries in list 991 * @direction: R/W or both. 992 * 993 * See Documentation/DMA-mapping.txt 994 */ 995 static int 996 sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents, 997 enum dma_data_direction direction) 998 { 999 struct ioc *ioc; 1000 int coalesced, filled = 0; 1001 unsigned long flags; 1002 1003 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents); 1004 1005 ioc = GET_IOC(dev); 1006 1007 /* Fast path single entry scatterlists. */ 1008 if (nents == 1) { 1009 sg_dma_address(sglist) = sba_map_single(dev, 1010 (void *)sg_virt_addr(sglist), 1011 sglist->length, direction); 1012 sg_dma_len(sglist) = sglist->length; 1013 return 1; 1014 } 1015 1016 spin_lock_irqsave(&ioc->res_lock, flags); 1017 1018 #ifdef ASSERT_PDIR_SANITY 1019 if (sba_check_pdir(ioc,"Check before sba_map_sg()")) 1020 { 1021 sba_dump_sg(ioc, sglist, nents); 1022 panic("Check before sba_map_sg()"); 1023 } 1024 #endif 1025 1026 #ifdef SBA_COLLECT_STATS 1027 ioc->msg_calls++; 1028 #endif 1029 1030 /* 1031 ** First coalesce the chunks and allocate I/O pdir space 1032 ** 1033 ** If this is one DMA stream, we can properly map using the 1034 ** correct virtual address associated with each DMA page. 1035 ** w/o this association, we wouldn't have coherent DMA! 1036 ** Access to the virtual address is what forces a two pass algorithm. 1037 */ 1038 coalesced = iommu_coalesce_chunks(ioc, sglist, nents, sba_alloc_range); 1039 1040 /* 1041 ** Program the I/O Pdir 1042 ** 1043 ** map the virtual addresses to the I/O Pdir 1044 ** o dma_address will contain the pdir index 1045 ** o dma_len will contain the number of bytes to map 1046 ** o address contains the virtual address. 1047 */ 1048 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry); 1049 1050 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ 1051 if (ioc_needs_fdc) 1052 asm volatile("sync" : : ); 1053 1054 #ifdef ASSERT_PDIR_SANITY 1055 if (sba_check_pdir(ioc,"Check after sba_map_sg()")) 1056 { 1057 sba_dump_sg(ioc, sglist, nents); 1058 panic("Check after sba_map_sg()\n"); 1059 } 1060 #endif 1061 1062 spin_unlock_irqrestore(&ioc->res_lock, flags); 1063 1064 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled); 1065 1066 return filled; 1067 } 1068 1069 1070 /** 1071 * sba_unmap_sg - unmap Scatter/Gather list 1072 * @dev: instance of PCI owned by the driver that's asking. 1073 * @sglist: array of buffer/length pairs 1074 * @nents: number of entries in list 1075 * @direction: R/W or both. 1076 * 1077 * See Documentation/DMA-mapping.txt 1078 */ 1079 static void 1080 sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents, 1081 enum dma_data_direction direction) 1082 { 1083 struct ioc *ioc; 1084 #ifdef ASSERT_PDIR_SANITY 1085 unsigned long flags; 1086 #endif 1087 1088 DBG_RUN_SG("%s() START %d entries, %p,%x\n", 1089 __FUNCTION__, nents, sg_virt_addr(sglist), sglist->length); 1090 1091 ioc = GET_IOC(dev); 1092 1093 #ifdef SBA_COLLECT_STATS 1094 ioc->usg_calls++; 1095 #endif 1096 1097 #ifdef ASSERT_PDIR_SANITY 1098 spin_lock_irqsave(&ioc->res_lock, flags); 1099 sba_check_pdir(ioc,"Check before sba_unmap_sg()"); 1100 spin_unlock_irqrestore(&ioc->res_lock, flags); 1101 #endif 1102 1103 while (sg_dma_len(sglist) && nents--) { 1104 1105 sba_unmap_single(dev, sg_dma_address(sglist), sg_dma_len(sglist), direction); 1106 #ifdef SBA_COLLECT_STATS 1107 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT; 1108 ioc->usingle_calls--; /* kluge since call is unmap_sg() */ 1109 #endif 1110 ++sglist; 1111 } 1112 1113 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents); 1114 1115 #ifdef ASSERT_PDIR_SANITY 1116 spin_lock_irqsave(&ioc->res_lock, flags); 1117 sba_check_pdir(ioc,"Check after sba_unmap_sg()"); 1118 spin_unlock_irqrestore(&ioc->res_lock, flags); 1119 #endif 1120 1121 } 1122 1123 static struct hppa_dma_ops sba_ops = { 1124 .dma_supported = sba_dma_supported, 1125 .alloc_consistent = sba_alloc_consistent, 1126 .alloc_noncoherent = sba_alloc_consistent, 1127 .free_consistent = sba_free_consistent, 1128 .map_single = sba_map_single, 1129 .unmap_single = sba_unmap_single, 1130 .map_sg = sba_map_sg, 1131 .unmap_sg = sba_unmap_sg, 1132 .dma_sync_single_for_cpu = NULL, 1133 .dma_sync_single_for_device = NULL, 1134 .dma_sync_sg_for_cpu = NULL, 1135 .dma_sync_sg_for_device = NULL, 1136 }; 1137 1138 1139 /************************************************************************** 1140 ** 1141 ** SBA PAT PDC support 1142 ** 1143 ** o call pdc_pat_cell_module() 1144 ** o store ranges in PCI "resource" structures 1145 ** 1146 **************************************************************************/ 1147 1148 static void 1149 sba_get_pat_resources(struct sba_device *sba_dev) 1150 { 1151 #if 0 1152 /* 1153 ** TODO/REVISIT/FIXME: support for directed ranges requires calls to 1154 ** PAT PDC to program the SBA/LBA directed range registers...this 1155 ** burden may fall on the LBA code since it directly supports the 1156 ** PCI subsystem. It's not clear yet. - ggg 1157 */ 1158 PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp); 1159 FIXME : ??? 1160 PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp); 1161 Tells where the dvi bits are located in the address. 1162 PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp); 1163 FIXME : ??? 1164 #endif 1165 } 1166 1167 1168 /************************************************************** 1169 * 1170 * Initialization and claim 1171 * 1172 ***************************************************************/ 1173 #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */ 1174 #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */ 1175 static void * 1176 sba_alloc_pdir(unsigned int pdir_size) 1177 { 1178 unsigned long pdir_base; 1179 unsigned long pdir_order = get_order(pdir_size); 1180 1181 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order); 1182 if (NULL == (void *) pdir_base) { 1183 panic("%s() could not allocate I/O Page Table\n", 1184 __FUNCTION__); 1185 } 1186 1187 /* If this is not PA8700 (PCX-W2) 1188 ** OR newer than ver 2.2 1189 ** OR in a system that doesn't need VINDEX bits from SBA, 1190 ** 1191 ** then we aren't exposed to the HW bug. 1192 */ 1193 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13 1194 || (boot_cpu_data.pdc.versions > 0x202) 1195 || (boot_cpu_data.pdc.capabilities & 0x08L) ) 1196 return (void *) pdir_base; 1197 1198 /* 1199 * PA8700 (PCX-W2, aka piranha) silent data corruption fix 1200 * 1201 * An interaction between PA8700 CPU (Ver 2.2 or older) and 1202 * Ike/Astro can cause silent data corruption. This is only 1203 * a problem if the I/O PDIR is located in memory such that 1204 * (little-endian) bits 17 and 18 are on and bit 20 is off. 1205 * 1206 * Since the max IO Pdir size is 2MB, by cleverly allocating the 1207 * right physical address, we can either avoid (IOPDIR <= 1MB) 1208 * or minimize (2MB IO Pdir) the problem if we restrict the 1209 * IO Pdir to a maximum size of 2MB-128K (1902K). 1210 * 1211 * Because we always allocate 2^N sized IO pdirs, either of the 1212 * "bad" regions will be the last 128K if at all. That's easy 1213 * to test for. 1214 * 1215 */ 1216 if (pdir_order <= (19-12)) { 1217 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) { 1218 /* allocate a new one on 512k alignment */ 1219 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12)); 1220 /* release original */ 1221 free_pages(pdir_base, pdir_order); 1222 1223 pdir_base = new_pdir; 1224 1225 /* release excess */ 1226 while (pdir_order < (19-12)) { 1227 new_pdir += pdir_size; 1228 free_pages(new_pdir, pdir_order); 1229 pdir_order +=1; 1230 pdir_size <<=1; 1231 } 1232 } 1233 } else { 1234 /* 1235 ** 1MB or 2MB Pdir 1236 ** Needs to be aligned on an "odd" 1MB boundary. 1237 */ 1238 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */ 1239 1240 /* release original */ 1241 free_pages( pdir_base, pdir_order); 1242 1243 /* release first 1MB */ 1244 free_pages(new_pdir, 20-12); 1245 1246 pdir_base = new_pdir + 1024*1024; 1247 1248 if (pdir_order > (20-12)) { 1249 /* 1250 ** 2MB Pdir. 1251 ** 1252 ** Flag tells init_bitmap() to mark bad 128k as used 1253 ** and to reduce the size by 128k. 1254 */ 1255 piranha_bad_128k = 1; 1256 1257 new_pdir += 3*1024*1024; 1258 /* release last 1MB */ 1259 free_pages(new_pdir, 20-12); 1260 1261 /* release unusable 128KB */ 1262 free_pages(new_pdir - 128*1024 , 17-12); 1263 1264 pdir_size -= 128*1024; 1265 } 1266 } 1267 1268 memset((void *) pdir_base, 0, pdir_size); 1269 return (void *) pdir_base; 1270 } 1271 1272 static struct device *next_device(struct klist_iter *i) 1273 { 1274 struct klist_node * n = klist_next(i); 1275 return n ? container_of(n, struct device, knode_parent) : NULL; 1276 } 1277 1278 /* setup Mercury or Elroy IBASE/IMASK registers. */ 1279 static void 1280 setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1281 { 1282 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */ 1283 extern void lba_set_iregs(struct parisc_device *, u32, u32); 1284 struct device *dev; 1285 struct klist_iter i; 1286 1287 klist_iter_init(&sba->dev.klist_children, &i); 1288 while ((dev = next_device(&i))) { 1289 struct parisc_device *lba = to_parisc_device(dev); 1290 int rope_num = (lba->hpa.start >> 13) & 0xf; 1291 if (rope_num >> 3 == ioc_num) 1292 lba_set_iregs(lba, ioc->ibase, ioc->imask); 1293 } 1294 klist_iter_exit(&i); 1295 } 1296 1297 static void 1298 sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1299 { 1300 u32 iova_space_mask; 1301 u32 iova_space_size; 1302 int iov_order, tcnfg; 1303 #ifdef SBA_AGP_SUPPORT 1304 int agp_found = 0; 1305 #endif 1306 /* 1307 ** Firmware programs the base and size of a "safe IOVA space" 1308 ** (one that doesn't overlap memory or LMMIO space) in the 1309 ** IBASE and IMASK registers. 1310 */ 1311 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE); 1312 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1; 1313 1314 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) { 1315 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n"); 1316 iova_space_size /= 2; 1317 } 1318 1319 /* 1320 ** iov_order is always based on a 1GB IOVA space since we want to 1321 ** turn on the other half for AGP GART. 1322 */ 1323 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT)); 1324 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64); 1325 1326 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n", 1327 __FUNCTION__, ioc->ioc_hpa, iova_space_size >> 20, 1328 iov_order + PAGE_SHIFT); 1329 1330 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL, 1331 get_order(ioc->pdir_size)); 1332 if (!ioc->pdir_base) 1333 panic("Couldn't allocate I/O Page Table\n"); 1334 1335 memset(ioc->pdir_base, 0, ioc->pdir_size); 1336 1337 DBG_INIT("%s() pdir %p size %x\n", 1338 __FUNCTION__, ioc->pdir_base, ioc->pdir_size); 1339 1340 #ifdef SBA_HINT_SUPPORT 1341 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; 1342 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); 1343 1344 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", 1345 ioc->hint_shift_pdir, ioc->hint_mask_pdir); 1346 #endif 1347 1348 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base); 1349 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1350 1351 /* build IMASK for IOC and Elroy */ 1352 iova_space_mask = 0xffffffff; 1353 iova_space_mask <<= (iov_order + PAGE_SHIFT); 1354 ioc->imask = iova_space_mask; 1355 #ifdef ZX1_SUPPORT 1356 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); 1357 #endif 1358 sba_dump_tlb(ioc->ioc_hpa); 1359 1360 setup_ibase_imask(sba, ioc, ioc_num); 1361 1362 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK); 1363 1364 #ifdef CONFIG_64BIT 1365 /* 1366 ** Setting the upper bits makes checking for bypass addresses 1367 ** a little faster later on. 1368 */ 1369 ioc->imask |= 0xFFFFFFFF00000000UL; 1370 #endif 1371 1372 /* Set I/O PDIR Page size to system page size */ 1373 switch (PAGE_SHIFT) { 1374 case 12: tcnfg = 0; break; /* 4K */ 1375 case 13: tcnfg = 1; break; /* 8K */ 1376 case 14: tcnfg = 2; break; /* 16K */ 1377 case 16: tcnfg = 3; break; /* 64K */ 1378 default: 1379 panic(__FILE__ "Unsupported system page size %d", 1380 1 << PAGE_SHIFT); 1381 break; 1382 } 1383 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG); 1384 1385 /* 1386 ** Program the IOC's ibase and enable IOVA translation 1387 ** Bit zero == enable bit. 1388 */ 1389 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE); 1390 1391 /* 1392 ** Clear I/O TLB of any possible entries. 1393 ** (Yes. This is a bit paranoid...but so what) 1394 */ 1395 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM); 1396 1397 #ifdef SBA_AGP_SUPPORT 1398 /* 1399 ** If an AGP device is present, only use half of the IOV space 1400 ** for PCI DMA. Unfortunately we can't know ahead of time 1401 ** whether GART support will actually be used, for now we 1402 ** can just key on any AGP device found in the system. 1403 ** We program the next pdir index after we stop w/ a key for 1404 ** the GART code to handshake on. 1405 */ 1406 device=NULL; 1407 for (lba = sba->child; lba; lba = lba->sibling) { 1408 if (IS_QUICKSILVER(lba)) 1409 break; 1410 } 1411 1412 if (lba) { 1413 DBG_INIT("%s: Reserving half of IOVA space for AGP GART support\n", __FUNCTION__); 1414 ioc->pdir_size /= 2; 1415 ((u64 *)ioc->pdir_base)[PDIR_INDEX(iova_space_size/2)] = SBA_IOMMU_COOKIE; 1416 } else { 1417 DBG_INIT("%s: No GART needed - no AGP controller found\n", __FUNCTION__); 1418 } 1419 #endif /* 0 */ 1420 1421 } 1422 1423 static void 1424 sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1425 { 1426 u32 iova_space_size, iova_space_mask; 1427 unsigned int pdir_size, iov_order; 1428 1429 /* 1430 ** Determine IOVA Space size from memory size. 1431 ** 1432 ** Ideally, PCI drivers would register the maximum number 1433 ** of DMA they can have outstanding for each device they 1434 ** own. Next best thing would be to guess how much DMA 1435 ** can be outstanding based on PCI Class/sub-class. Both 1436 ** methods still require some "extra" to support PCI 1437 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD). 1438 ** 1439 ** While we have 32-bits "IOVA" space, top two 2 bits are used 1440 ** for DMA hints - ergo only 30 bits max. 1441 */ 1442 1443 iova_space_size = (u32) (num_physpages/global_ioc_cnt); 1444 1445 /* limit IOVA space size to 1MB-1GB */ 1446 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) { 1447 iova_space_size = 1 << (20 - PAGE_SHIFT); 1448 } 1449 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) { 1450 iova_space_size = 1 << (30 - PAGE_SHIFT); 1451 } 1452 1453 /* 1454 ** iova space must be log2() in size. 1455 ** thus, pdir/res_map will also be log2(). 1456 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced) 1457 */ 1458 iov_order = get_order(iova_space_size << PAGE_SHIFT); 1459 1460 /* iova_space_size is now bytes, not pages */ 1461 iova_space_size = 1 << (iov_order + PAGE_SHIFT); 1462 1463 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64); 1464 1465 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n", 1466 __FUNCTION__, 1467 ioc->ioc_hpa, 1468 (unsigned long) num_physpages >> (20 - PAGE_SHIFT), 1469 iova_space_size>>20, 1470 iov_order + PAGE_SHIFT); 1471 1472 ioc->pdir_base = sba_alloc_pdir(pdir_size); 1473 1474 DBG_INIT("%s() pdir %p size %x\n", 1475 __FUNCTION__, ioc->pdir_base, pdir_size); 1476 1477 #ifdef SBA_HINT_SUPPORT 1478 /* FIXME : DMA HINTs not used */ 1479 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; 1480 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); 1481 1482 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", 1483 ioc->hint_shift_pdir, ioc->hint_mask_pdir); 1484 #endif 1485 1486 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1487 1488 /* build IMASK for IOC and Elroy */ 1489 iova_space_mask = 0xffffffff; 1490 iova_space_mask <<= (iov_order + PAGE_SHIFT); 1491 1492 /* 1493 ** On C3000 w/512MB mem, HP-UX 10.20 reports: 1494 ** ibase=0, imask=0xFE000000, size=0x2000000. 1495 */ 1496 ioc->ibase = 0; 1497 ioc->imask = iova_space_mask; /* save it */ 1498 #ifdef ZX1_SUPPORT 1499 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); 1500 #endif 1501 1502 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n", 1503 __FUNCTION__, ioc->ibase, ioc->imask); 1504 1505 /* 1506 ** FIXME: Hint registers are programmed with default hint 1507 ** values during boot, so hints should be sane even if we 1508 ** can't reprogram them the way drivers want. 1509 */ 1510 1511 setup_ibase_imask(sba, ioc, ioc_num); 1512 1513 /* 1514 ** Program the IOC's ibase and enable IOVA translation 1515 */ 1516 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE); 1517 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK); 1518 1519 /* Set I/O PDIR Page size to 4K */ 1520 WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG); 1521 1522 /* 1523 ** Clear I/O TLB of any possible entries. 1524 ** (Yes. This is a bit paranoid...but so what) 1525 */ 1526 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM); 1527 1528 ioc->ibase = 0; /* used by SBA_IOVA and related macros */ 1529 1530 DBG_INIT("%s() DONE\n", __FUNCTION__); 1531 } 1532 1533 1534 1535 /************************************************************************** 1536 ** 1537 ** SBA initialization code (HW and SW) 1538 ** 1539 ** o identify SBA chip itself 1540 ** o initialize SBA chip modes (HardFail) 1541 ** o initialize SBA chip modes (HardFail) 1542 ** o FIXME: initialize DMA hints for reasonable defaults 1543 ** 1544 **************************************************************************/ 1545 1546 static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset) 1547 { 1548 return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE); 1549 } 1550 1551 static void sba_hw_init(struct sba_device *sba_dev) 1552 { 1553 int i; 1554 int num_ioc; 1555 u64 ioc_ctl; 1556 1557 if (!is_pdc_pat()) { 1558 /* Shutdown the USB controller on Astro-based workstations. 1559 ** Once we reprogram the IOMMU, the next DMA performed by 1560 ** USB will HPMC the box. USB is only enabled if a 1561 ** keyboard is present and found. 1562 ** 1563 ** With serial console, j6k v5.0 firmware says: 1564 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7 1565 ** 1566 ** FIXME: Using GFX+USB console at power up but direct 1567 ** linux to serial console is still broken. 1568 ** USB could generate DMA so we must reset USB. 1569 ** The proper sequence would be: 1570 ** o block console output 1571 ** o reset USB device 1572 ** o reprogram serial port 1573 ** o unblock console output 1574 */ 1575 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) { 1576 pdc_io_reset_devices(); 1577 } 1578 1579 } 1580 1581 1582 #if 0 1583 printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa, 1584 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class); 1585 1586 /* 1587 ** Need to deal with DMA from LAN. 1588 ** Maybe use page zero boot device as a handle to talk 1589 ** to PDC about which device to shutdown. 1590 ** 1591 ** Netbooting, j6k v5.0 firmware says: 1592 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002 1593 ** ARGH! invalid class. 1594 */ 1595 if ((PAGE0->mem_boot.cl_class != CL_RANDOM) 1596 && (PAGE0->mem_boot.cl_class != CL_SEQU)) { 1597 pdc_io_reset(); 1598 } 1599 #endif 1600 1601 if (!IS_PLUTO(sba_dev->dev)) { 1602 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL); 1603 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->", 1604 __FUNCTION__, sba_dev->sba_hpa, ioc_ctl); 1605 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE); 1606 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC; 1607 /* j6700 v1.6 firmware sets 0x294f */ 1608 /* A500 firmware sets 0x4d */ 1609 1610 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL); 1611 1612 #ifdef DEBUG_SBA_INIT 1613 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL); 1614 DBG_INIT(" 0x%Lx\n", ioc_ctl); 1615 #endif 1616 } /* if !PLUTO */ 1617 1618 if (IS_ASTRO(sba_dev->dev)) { 1619 int err; 1620 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET); 1621 num_ioc = 1; 1622 1623 sba_dev->chip_resv.name = "Astro Intr Ack"; 1624 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL; 1625 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ; 1626 err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); 1627 BUG_ON(err < 0); 1628 1629 } else if (IS_PLUTO(sba_dev->dev)) { 1630 int err; 1631 1632 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET); 1633 num_ioc = 1; 1634 1635 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA"; 1636 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL; 1637 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1); 1638 err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); 1639 WARN_ON(err < 0); 1640 1641 sba_dev->iommu_resv.name = "IOVA Space"; 1642 sba_dev->iommu_resv.start = 0x40000000UL; 1643 sba_dev->iommu_resv.end = 0x50000000UL - 1; 1644 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv)); 1645 WARN_ON(err < 0); 1646 } else { 1647 /* IKE, REO */ 1648 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0)); 1649 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1)); 1650 num_ioc = 2; 1651 1652 /* TODO - LOOKUP Ike/Stretch chipset mem map */ 1653 } 1654 /* XXX: What about Reo Grande? */ 1655 1656 sba_dev->num_ioc = num_ioc; 1657 for (i = 0; i < num_ioc; i++) { 1658 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa; 1659 unsigned int j; 1660 1661 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) { 1662 1663 /* 1664 * Clear ROPE(N)_CONFIG AO bit. 1665 * Disables "NT Ordering" (~= !"Relaxed Ordering") 1666 * Overrides bit 1 in DMA Hint Sets. 1667 * Improves netperf UDP_STREAM by ~10% for bcm5701. 1668 */ 1669 if (IS_PLUTO(sba_dev->dev)) { 1670 void __iomem *rope_cfg; 1671 unsigned long cfg_val; 1672 1673 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j; 1674 cfg_val = READ_REG(rope_cfg); 1675 cfg_val &= ~IOC_ROPE_AO; 1676 WRITE_REG(cfg_val, rope_cfg); 1677 } 1678 1679 /* 1680 ** Make sure the box crashes on rope errors. 1681 */ 1682 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j); 1683 } 1684 1685 /* flush out the last writes */ 1686 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL); 1687 1688 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n", 1689 i, 1690 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40), 1691 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50) 1692 ); 1693 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n", 1694 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108), 1695 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400) 1696 ); 1697 1698 if (IS_PLUTO(sba_dev->dev)) { 1699 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i); 1700 } else { 1701 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i); 1702 } 1703 } 1704 } 1705 1706 static void 1707 sba_common_init(struct sba_device *sba_dev) 1708 { 1709 int i; 1710 1711 /* add this one to the head of the list (order doesn't matter) 1712 ** This will be useful for debugging - especially if we get coredumps 1713 */ 1714 sba_dev->next = sba_list; 1715 sba_list = sba_dev; 1716 1717 for(i=0; i< sba_dev->num_ioc; i++) { 1718 int res_size; 1719 #ifdef DEBUG_DMB_TRAP 1720 extern void iterate_pages(unsigned long , unsigned long , 1721 void (*)(pte_t * , unsigned long), 1722 unsigned long ); 1723 void set_data_memory_break(pte_t * , unsigned long); 1724 #endif 1725 /* resource map size dictated by pdir_size */ 1726 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */ 1727 1728 /* Second part of PIRANHA BUG */ 1729 if (piranha_bad_128k) { 1730 res_size -= (128*1024)/sizeof(u64); 1731 } 1732 1733 res_size >>= 3; /* convert bit count to byte count */ 1734 DBG_INIT("%s() res_size 0x%x\n", 1735 __FUNCTION__, res_size); 1736 1737 sba_dev->ioc[i].res_size = res_size; 1738 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size)); 1739 1740 #ifdef DEBUG_DMB_TRAP 1741 iterate_pages( sba_dev->ioc[i].res_map, res_size, 1742 set_data_memory_break, 0); 1743 #endif 1744 1745 if (NULL == sba_dev->ioc[i].res_map) 1746 { 1747 panic("%s:%s() could not allocate resource map\n", 1748 __FILE__, __FUNCTION__ ); 1749 } 1750 1751 memset(sba_dev->ioc[i].res_map, 0, res_size); 1752 /* next available IOVP - circular search */ 1753 sba_dev->ioc[i].res_hint = (unsigned long *) 1754 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]); 1755 1756 #ifdef ASSERT_PDIR_SANITY 1757 /* Mark first bit busy - ie no IOVA 0 */ 1758 sba_dev->ioc[i].res_map[0] = 0x80; 1759 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL; 1760 #endif 1761 1762 /* Third (and last) part of PIRANHA BUG */ 1763 if (piranha_bad_128k) { 1764 /* region from +1408K to +1536 is un-usable. */ 1765 1766 int idx_start = (1408*1024/sizeof(u64)) >> 3; 1767 int idx_end = (1536*1024/sizeof(u64)) >> 3; 1768 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]); 1769 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]); 1770 1771 /* mark that part of the io pdir busy */ 1772 while (p_start < p_end) 1773 *p_start++ = -1; 1774 1775 } 1776 1777 #ifdef DEBUG_DMB_TRAP 1778 iterate_pages( sba_dev->ioc[i].res_map, res_size, 1779 set_data_memory_break, 0); 1780 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size, 1781 set_data_memory_break, 0); 1782 #endif 1783 1784 DBG_INIT("%s() %d res_map %x %p\n", 1785 __FUNCTION__, i, res_size, sba_dev->ioc[i].res_map); 1786 } 1787 1788 spin_lock_init(&sba_dev->sba_lock); 1789 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC; 1790 1791 #ifdef DEBUG_SBA_INIT 1792 /* 1793 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set 1794 * (bit #61, big endian), we have to flush and sync every time 1795 * IO-PDIR is changed in Ike/Astro. 1796 */ 1797 if (ioc_needs_fdc) { 1798 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n"); 1799 } else { 1800 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n"); 1801 } 1802 #endif 1803 } 1804 1805 #ifdef CONFIG_PROC_FS 1806 static int sba_proc_info(struct seq_file *m, void *p) 1807 { 1808 struct sba_device *sba_dev = sba_list; 1809 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ 1810 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */ 1811 #ifdef SBA_COLLECT_STATS 1812 unsigned long avg = 0, min, max; 1813 #endif 1814 int i, len = 0; 1815 1816 len += seq_printf(m, "%s rev %d.%d\n", 1817 sba_dev->name, 1818 (sba_dev->hw_rev & 0x7) + 1, 1819 (sba_dev->hw_rev & 0x18) >> 3 1820 ); 1821 len += seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n", 1822 (int) ((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */ 1823 total_pages); 1824 1825 len += seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n", 1826 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */ 1827 1828 len += seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n", 1829 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE), 1830 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK), 1831 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE) 1832 ); 1833 1834 for (i=0; i<4; i++) 1835 len += seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", i, 1836 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18), 1837 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18), 1838 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18) 1839 ); 1840 1841 #ifdef SBA_COLLECT_STATS 1842 len += seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n", 1843 total_pages - ioc->used_pages, ioc->used_pages, 1844 (int) (ioc->used_pages * 100 / total_pages)); 1845 1846 min = max = ioc->avg_search[0]; 1847 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) { 1848 avg += ioc->avg_search[i]; 1849 if (ioc->avg_search[i] > max) max = ioc->avg_search[i]; 1850 if (ioc->avg_search[i] < min) min = ioc->avg_search[i]; 1851 } 1852 avg /= SBA_SEARCH_SAMPLE; 1853 len += seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n", 1854 min, avg, max); 1855 1856 len += seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n", 1857 ioc->msingle_calls, ioc->msingle_pages, 1858 (int) ((ioc->msingle_pages * 1000)/ioc->msingle_calls)); 1859 1860 /* KLUGE - unmap_sg calls unmap_single for each mapped page */ 1861 min = ioc->usingle_calls; 1862 max = ioc->usingle_pages - ioc->usg_pages; 1863 len += seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n", 1864 min, max, (int) ((max * 1000)/min)); 1865 1866 len += seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n", 1867 ioc->msg_calls, ioc->msg_pages, 1868 (int) ((ioc->msg_pages * 1000)/ioc->msg_calls)); 1869 1870 len += seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n", 1871 ioc->usg_calls, ioc->usg_pages, 1872 (int) ((ioc->usg_pages * 1000)/ioc->usg_calls)); 1873 #endif 1874 1875 return 0; 1876 } 1877 1878 static int 1879 sba_proc_open(struct inode *i, struct file *f) 1880 { 1881 return single_open(f, &sba_proc_info, NULL); 1882 } 1883 1884 static struct file_operations sba_proc_fops = { 1885 .owner = THIS_MODULE, 1886 .open = sba_proc_open, 1887 .read = seq_read, 1888 .llseek = seq_lseek, 1889 .release = single_release, 1890 }; 1891 1892 static int 1893 sba_proc_bitmap_info(struct seq_file *m, void *p) 1894 { 1895 struct sba_device *sba_dev = sba_list; 1896 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ 1897 unsigned int *res_ptr = (unsigned int *)ioc->res_map; 1898 int i, len = 0; 1899 1900 for (i = 0; i < (ioc->res_size/sizeof(unsigned int)); ++i, ++res_ptr) { 1901 if ((i & 7) == 0) 1902 len += seq_printf(m, "\n "); 1903 len += seq_printf(m, " %08x", *res_ptr); 1904 } 1905 len += seq_printf(m, "\n"); 1906 1907 return 0; 1908 } 1909 1910 static int 1911 sba_proc_bitmap_open(struct inode *i, struct file *f) 1912 { 1913 return single_open(f, &sba_proc_bitmap_info, NULL); 1914 } 1915 1916 static struct file_operations sba_proc_bitmap_fops = { 1917 .owner = THIS_MODULE, 1918 .open = sba_proc_bitmap_open, 1919 .read = seq_read, 1920 .llseek = seq_lseek, 1921 .release = single_release, 1922 }; 1923 #endif /* CONFIG_PROC_FS */ 1924 1925 static struct parisc_device_id sba_tbl[] = { 1926 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb }, 1927 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc }, 1928 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc }, 1929 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc }, 1930 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc }, 1931 { 0, } 1932 }; 1933 1934 int sba_driver_callback(struct parisc_device *); 1935 1936 static struct parisc_driver sba_driver = { 1937 .name = MODULE_NAME, 1938 .id_table = sba_tbl, 1939 .probe = sba_driver_callback, 1940 }; 1941 1942 /* 1943 ** Determine if sba should claim this chip (return 0) or not (return 1). 1944 ** If so, initialize the chip and tell other partners in crime they 1945 ** have work to do. 1946 */ 1947 int 1948 sba_driver_callback(struct parisc_device *dev) 1949 { 1950 struct sba_device *sba_dev; 1951 u32 func_class; 1952 int i; 1953 char *version; 1954 void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE); 1955 struct proc_dir_entry *info_entry, *bitmap_entry, *root; 1956 1957 sba_dump_ranges(sba_addr); 1958 1959 /* Read HW Rev First */ 1960 func_class = READ_REG(sba_addr + SBA_FCLASS); 1961 1962 if (IS_ASTRO(dev)) { 1963 unsigned long fclass; 1964 static char astro_rev[]="Astro ?.?"; 1965 1966 /* Astro is broken...Read HW Rev First */ 1967 fclass = READ_REG(sba_addr); 1968 1969 astro_rev[6] = '1' + (char) (fclass & 0x7); 1970 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3); 1971 version = astro_rev; 1972 1973 } else if (IS_IKE(dev)) { 1974 static char ike_rev[] = "Ike rev ?"; 1975 ike_rev[8] = '0' + (char) (func_class & 0xff); 1976 version = ike_rev; 1977 } else if (IS_PLUTO(dev)) { 1978 static char pluto_rev[]="Pluto ?.?"; 1979 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4); 1980 pluto_rev[8] = '0' + (char) (func_class & 0x0f); 1981 version = pluto_rev; 1982 } else { 1983 static char reo_rev[] = "REO rev ?"; 1984 reo_rev[8] = '0' + (char) (func_class & 0xff); 1985 version = reo_rev; 1986 } 1987 1988 if (!global_ioc_cnt) { 1989 global_ioc_cnt = count_parisc_driver(&sba_driver); 1990 1991 /* Astro and Pluto have one IOC per SBA */ 1992 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev))) 1993 global_ioc_cnt *= 2; 1994 } 1995 1996 printk(KERN_INFO "%s found %s at 0x%lx\n", 1997 MODULE_NAME, version, dev->hpa.start); 1998 1999 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL); 2000 if (!sba_dev) { 2001 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n"); 2002 return -ENOMEM; 2003 } 2004 2005 parisc_set_drvdata(dev, sba_dev); 2006 2007 for(i=0; i<MAX_IOC; i++) 2008 spin_lock_init(&(sba_dev->ioc[i].res_lock)); 2009 2010 sba_dev->dev = dev; 2011 sba_dev->hw_rev = func_class; 2012 sba_dev->name = dev->name; 2013 sba_dev->sba_hpa = sba_addr; 2014 2015 sba_get_pat_resources(sba_dev); 2016 sba_hw_init(sba_dev); 2017 sba_common_init(sba_dev); 2018 2019 hppa_dma_ops = &sba_ops; 2020 2021 #ifdef CONFIG_PROC_FS 2022 switch (dev->id.hversion) { 2023 case PLUTO_MCKINLEY_PORT: 2024 root = proc_mckinley_root; 2025 break; 2026 case ASTRO_RUNWAY_PORT: 2027 case IKE_MERCED_PORT: 2028 default: 2029 root = proc_runway_root; 2030 break; 2031 } 2032 2033 info_entry = create_proc_entry("sba_iommu", 0, root); 2034 bitmap_entry = create_proc_entry("sba_iommu-bitmap", 0, root); 2035 2036 if (info_entry) 2037 info_entry->proc_fops = &sba_proc_fops; 2038 2039 if (bitmap_entry) 2040 bitmap_entry->proc_fops = &sba_proc_bitmap_fops; 2041 #endif 2042 2043 parisc_vmerge_boundary = IOVP_SIZE; 2044 parisc_vmerge_max_size = IOVP_SIZE * BITS_PER_LONG; 2045 parisc_has_iommu(); 2046 return 0; 2047 } 2048 2049 /* 2050 ** One time initialization to let the world know the SBA was found. 2051 ** This is the only routine which is NOT static. 2052 ** Must be called exactly once before pci_init(). 2053 */ 2054 void __init sba_init(void) 2055 { 2056 register_parisc_driver(&sba_driver); 2057 } 2058 2059 2060 /** 2061 * sba_get_iommu - Assign the iommu pointer for the pci bus controller. 2062 * @dev: The parisc device. 2063 * 2064 * Returns the appropriate IOMMU data for the given parisc PCI controller. 2065 * This is cached and used later for PCI DMA Mapping. 2066 */ 2067 void * sba_get_iommu(struct parisc_device *pci_hba) 2068 { 2069 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2070 struct sba_device *sba = sba_dev->dev.driver_data; 2071 char t = sba_dev->id.hw_type; 2072 int iocnum = (pci_hba->hw_path >> 3); /* rope # */ 2073 2074 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT)); 2075 2076 return &(sba->ioc[iocnum]); 2077 } 2078 2079 2080 /** 2081 * sba_directed_lmmio - return first directed LMMIO range routed to rope 2082 * @pa_dev: The parisc device. 2083 * @r: resource PCI host controller wants start/end fields assigned. 2084 * 2085 * For the given parisc PCI controller, determine if any direct ranges 2086 * are routed down the corresponding rope. 2087 */ 2088 void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r) 2089 { 2090 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2091 struct sba_device *sba = sba_dev->dev.driver_data; 2092 char t = sba_dev->id.hw_type; 2093 int i; 2094 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ 2095 2096 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); 2097 2098 r->start = r->end = 0; 2099 2100 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */ 2101 for (i=0; i<4; i++) { 2102 int base, size; 2103 void __iomem *reg = sba->sba_hpa + i*0x18; 2104 2105 base = READ_REG32(reg + LMMIO_DIRECT0_BASE); 2106 if ((base & 1) == 0) 2107 continue; /* not enabled */ 2108 2109 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE); 2110 2111 if ((size & (ROPES_PER_IOC-1)) != rope) 2112 continue; /* directed down different rope */ 2113 2114 r->start = (base & ~1UL) | PCI_F_EXTEND; 2115 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK); 2116 r->end = r->start + size; 2117 } 2118 } 2119 2120 2121 /** 2122 * sba_distributed_lmmio - return portion of distributed LMMIO range 2123 * @pa_dev: The parisc device. 2124 * @r: resource PCI host controller wants start/end fields assigned. 2125 * 2126 * For the given parisc PCI controller, return portion of distributed LMMIO 2127 * range. The distributed LMMIO is always present and it's just a question 2128 * of the base address and size of the range. 2129 */ 2130 void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r ) 2131 { 2132 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2133 struct sba_device *sba = sba_dev->dev.driver_data; 2134 char t = sba_dev->id.hw_type; 2135 int base, size; 2136 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ 2137 2138 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); 2139 2140 r->start = r->end = 0; 2141 2142 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE); 2143 if ((base & 1) == 0) { 2144 BUG(); /* Gah! Distr Range wasn't enabled! */ 2145 return; 2146 } 2147 2148 r->start = (base & ~1UL) | PCI_F_EXTEND; 2149 2150 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC; 2151 r->start += rope * (size + 1); /* adjust base for this rope */ 2152 r->end = r->start + size; 2153 } 2154