main.c (73395a79df00c3e0101bd7a0229dbbcc065b606a) main.c (16ea4733210d741eeb5413acd261e675a12f980e)
1/*
2 * This file is part of wl18xx
3 *
4 * Copyright (C) 2011 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.

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506 .srf_state = 0x00,
507 .io_configuration = 0x01,
508 .sdio_configuration = 0x00,
509 .settings = 0x00,
510 .enable_clpc = 0x00,
511 .enable_tx_low_pwr_on_siso_rdl = 0x00,
512 .rx_profile = 0x00,
513 .pwr_limit_reference_11_abg = 0xc8,
1/*
2 * This file is part of wl18xx
3 *
4 * Copyright (C) 2011 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.

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506 .srf_state = 0x00,
507 .io_configuration = 0x01,
508 .sdio_configuration = 0x00,
509 .settings = 0x00,
510 .enable_clpc = 0x00,
511 .enable_tx_low_pwr_on_siso_rdl = 0x00,
512 .rx_profile = 0x00,
513 .pwr_limit_reference_11_abg = 0xc8,
514 .psat = 0,
515 .low_power_val = 0x00,
516 .med_power_val = 0x0a,
517 .high_power_val = 0x1e,
514 },
515};
516
517static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
518 [PART_TOP_PRCM_ELP_SOC] = {
519 .mem = { .start = 0x00A02000, .size = 0x00010000 },
520 .reg = { .start = 0x00807000, .size = 0x00005000 },
521 .mem2 = { .start = 0x00800000, .size = 0x0000B000 },

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708 tmp = wl1271_read32(wl, WL18XX_SCR_PAD2);
709}
710
711static void wl18xx_set_mac_and_phy(struct wl1271 *wl)
712{
713 struct wl18xx_priv *priv = wl->priv;
714 struct wl18xx_conf_phy *phy = &priv->conf.phy;
715 struct wl18xx_mac_and_phy_params params;
518 },
519};
520
521static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
522 [PART_TOP_PRCM_ELP_SOC] = {
523 .mem = { .start = 0x00A02000, .size = 0x00010000 },
524 .reg = { .start = 0x00807000, .size = 0x00005000 },
525 .mem2 = { .start = 0x00800000, .size = 0x0000B000 },

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712 tmp = wl1271_read32(wl, WL18XX_SCR_PAD2);
713}
714
715static void wl18xx_set_mac_and_phy(struct wl1271 *wl)
716{
717 struct wl18xx_priv *priv = wl->priv;
718 struct wl18xx_conf_phy *phy = &priv->conf.phy;
719 struct wl18xx_mac_and_phy_params params;
720 size_t len;
716
717 memset(&params, 0, sizeof(params));
718
719 params.phy_standalone = phy->phy_standalone;
720 params.rdl = phy->rdl;
721 params.enable_clpc = phy->enable_clpc;
722 params.enable_tx_low_pwr_on_siso_rdl =
723 phy->enable_tx_low_pwr_on_siso_rdl;

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747 phy->clock_valid_on_wake_up;
748 params.secondary_clock_setting_time =
749 phy->secondary_clock_setting_time;
750 params.pwr_limit_reference_11_abg =
751 phy->pwr_limit_reference_11_abg;
752
753 params.board_type = priv->board_type;
754
721
722 memset(&params, 0, sizeof(params));
723
724 params.phy_standalone = phy->phy_standalone;
725 params.rdl = phy->rdl;
726 params.enable_clpc = phy->enable_clpc;
727 params.enable_tx_low_pwr_on_siso_rdl =
728 phy->enable_tx_low_pwr_on_siso_rdl;

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752 phy->clock_valid_on_wake_up;
753 params.secondary_clock_setting_time =
754 phy->secondary_clock_setting_time;
755 params.pwr_limit_reference_11_abg =
756 phy->pwr_limit_reference_11_abg;
757
758 params.board_type = priv->board_type;
759
760 /* for PG2 only */
761 params.psat = phy->psat;
762 params.low_power_val = phy->low_power_val;
763 params.med_power_val = phy->med_power_val;
764 params.high_power_val = phy->high_power_val;
765
766 /* the parameters struct is smaller for PG1 */
767 if (wl->chip.id == CHIP_ID_185x_PG10)
768 len = offsetof(struct wl18xx_mac_and_phy_params, psat) + 1;
769 else
770 len = sizeof(params);
771
755 wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
756 wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)&params,
772 wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
773 wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)&params,
757 sizeof(params), false);
774 len, false);
758}
759
760static void wl18xx_enable_interrupts(struct wl1271 *wl)
761{
762 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_ALL_EVENTS_VECTOR);
763
764 wlcore_enable_interrupts(wl);
765 wlcore_write_reg(wl, REG_INTERRUPT_MASK,

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776
777static void wl18xx_enable_interrupts(struct wl1271 *wl)
778{
779 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_ALL_EVENTS_VECTOR);
780
781 wlcore_enable_interrupts(wl);
782 wlcore_write_reg(wl, REG_INTERRUPT_MASK,

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