1 /* 2 * This file is part of wl18xx 3 * 4 * Copyright (C) 2011 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 18 * 02110-1301 USA 19 * 20 */ 21 22 #include <linux/module.h> 23 #include <linux/platform_device.h> 24 #include <linux/ip.h> 25 26 #include "../wlcore/wlcore.h" 27 #include "../wlcore/debug.h" 28 #include "../wlcore/io.h" 29 #include "../wlcore/acx.h" 30 #include "../wlcore/tx.h" 31 #include "../wlcore/rx.h" 32 #include "../wlcore/io.h" 33 #include "../wlcore/boot.h" 34 35 #include "reg.h" 36 #include "conf.h" 37 #include "acx.h" 38 #include "tx.h" 39 #include "wl18xx.h" 40 #include "io.h" 41 #include "debugfs.h" 42 43 #define WL18XX_RX_CHECKSUM_MASK 0x40 44 45 static char *ht_mode_param = "wide"; 46 static char *board_type_param = "hdk"; 47 static bool dc2dc_param = false; 48 static int n_antennas_2_param = 1; 49 static int n_antennas_5_param = 1; 50 static bool checksum_param = false; 51 static bool enable_11a_param = true; 52 static int low_band_component = -1; 53 static int low_band_component_type = -1; 54 static int high_band_component = -1; 55 static int high_band_component_type = -1; 56 static int pwr_limit_reference_11_abg = -1; 57 58 static const u8 wl18xx_rate_to_idx_2ghz[] = { 59 /* MCS rates are used only with 11n */ 60 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */ 61 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */ 62 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */ 63 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */ 64 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */ 65 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */ 66 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */ 67 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */ 68 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */ 69 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */ 70 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */ 71 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */ 72 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */ 73 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */ 74 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */ 75 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */ 76 77 11, /* WL18XX_CONF_HW_RXTX_RATE_54 */ 78 10, /* WL18XX_CONF_HW_RXTX_RATE_48 */ 79 9, /* WL18XX_CONF_HW_RXTX_RATE_36 */ 80 8, /* WL18XX_CONF_HW_RXTX_RATE_24 */ 81 82 /* TI-specific rate */ 83 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */ 84 85 7, /* WL18XX_CONF_HW_RXTX_RATE_18 */ 86 6, /* WL18XX_CONF_HW_RXTX_RATE_12 */ 87 3, /* WL18XX_CONF_HW_RXTX_RATE_11 */ 88 5, /* WL18XX_CONF_HW_RXTX_RATE_9 */ 89 4, /* WL18XX_CONF_HW_RXTX_RATE_6 */ 90 2, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */ 91 1, /* WL18XX_CONF_HW_RXTX_RATE_2 */ 92 0 /* WL18XX_CONF_HW_RXTX_RATE_1 */ 93 }; 94 95 static const u8 wl18xx_rate_to_idx_5ghz[] = { 96 /* MCS rates are used only with 11n */ 97 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */ 98 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */ 99 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */ 100 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */ 101 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */ 102 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */ 103 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */ 104 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */ 105 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */ 106 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */ 107 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */ 108 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */ 109 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */ 110 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */ 111 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */ 112 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */ 113 114 7, /* WL18XX_CONF_HW_RXTX_RATE_54 */ 115 6, /* WL18XX_CONF_HW_RXTX_RATE_48 */ 116 5, /* WL18XX_CONF_HW_RXTX_RATE_36 */ 117 4, /* WL18XX_CONF_HW_RXTX_RATE_24 */ 118 119 /* TI-specific rate */ 120 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */ 121 122 3, /* WL18XX_CONF_HW_RXTX_RATE_18 */ 123 2, /* WL18XX_CONF_HW_RXTX_RATE_12 */ 124 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11 */ 125 1, /* WL18XX_CONF_HW_RXTX_RATE_9 */ 126 0, /* WL18XX_CONF_HW_RXTX_RATE_6 */ 127 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */ 128 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2 */ 129 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1 */ 130 }; 131 132 static const u8 *wl18xx_band_rate_to_idx[] = { 133 [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz, 134 [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz 135 }; 136 137 enum wl18xx_hw_rates { 138 WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0, 139 WL18XX_CONF_HW_RXTX_RATE_MCS14, 140 WL18XX_CONF_HW_RXTX_RATE_MCS13, 141 WL18XX_CONF_HW_RXTX_RATE_MCS12, 142 WL18XX_CONF_HW_RXTX_RATE_MCS11, 143 WL18XX_CONF_HW_RXTX_RATE_MCS10, 144 WL18XX_CONF_HW_RXTX_RATE_MCS9, 145 WL18XX_CONF_HW_RXTX_RATE_MCS8, 146 WL18XX_CONF_HW_RXTX_RATE_MCS7, 147 WL18XX_CONF_HW_RXTX_RATE_MCS6, 148 WL18XX_CONF_HW_RXTX_RATE_MCS5, 149 WL18XX_CONF_HW_RXTX_RATE_MCS4, 150 WL18XX_CONF_HW_RXTX_RATE_MCS3, 151 WL18XX_CONF_HW_RXTX_RATE_MCS2, 152 WL18XX_CONF_HW_RXTX_RATE_MCS1, 153 WL18XX_CONF_HW_RXTX_RATE_MCS0, 154 WL18XX_CONF_HW_RXTX_RATE_54, 155 WL18XX_CONF_HW_RXTX_RATE_48, 156 WL18XX_CONF_HW_RXTX_RATE_36, 157 WL18XX_CONF_HW_RXTX_RATE_24, 158 WL18XX_CONF_HW_RXTX_RATE_22, 159 WL18XX_CONF_HW_RXTX_RATE_18, 160 WL18XX_CONF_HW_RXTX_RATE_12, 161 WL18XX_CONF_HW_RXTX_RATE_11, 162 WL18XX_CONF_HW_RXTX_RATE_9, 163 WL18XX_CONF_HW_RXTX_RATE_6, 164 WL18XX_CONF_HW_RXTX_RATE_5_5, 165 WL18XX_CONF_HW_RXTX_RATE_2, 166 WL18XX_CONF_HW_RXTX_RATE_1, 167 WL18XX_CONF_HW_RXTX_RATE_MAX, 168 }; 169 170 static struct wlcore_conf wl18xx_conf = { 171 .sg = { 172 .params = { 173 [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10, 174 [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180, 175 [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10, 176 [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180, 177 [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10, 178 [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80, 179 [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10, 180 [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80, 181 [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8, 182 [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8, 183 [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20, 184 [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20, 185 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20, 186 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35, 187 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16, 188 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35, 189 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32, 190 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50, 191 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28, 192 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50, 193 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10, 194 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20, 195 [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75, 196 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15, 197 [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27, 198 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17, 199 /* active scan params */ 200 [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170, 201 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50, 202 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100, 203 /* passive scan params */ 204 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800, 205 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200, 206 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200, 207 /* passive scan in dual antenna params */ 208 [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0, 209 [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0, 210 [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0, 211 /* general params */ 212 [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1, 213 [CONF_SG_ANTENNA_CONFIGURATION] = 0, 214 [CONF_SG_BEACON_MISS_PERCENT] = 60, 215 [CONF_SG_DHCP_TIME] = 5000, 216 [CONF_SG_RXT] = 1200, 217 [CONF_SG_TXT] = 1000, 218 [CONF_SG_ADAPTIVE_RXT_TXT] = 1, 219 [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3, 220 [CONF_SG_HV3_MAX_SERVED] = 6, 221 [CONF_SG_PS_POLL_TIMEOUT] = 10, 222 [CONF_SG_UPSD_TIMEOUT] = 10, 223 [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2, 224 [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5, 225 [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30, 226 /* AP params */ 227 [CONF_AP_BEACON_MISS_TX] = 3, 228 [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10, 229 [CONF_AP_BEACON_WINDOW_INTERVAL] = 2, 230 [CONF_AP_CONNECTION_PROTECTION_TIME] = 0, 231 [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25, 232 [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25, 233 /* CTS Diluting params */ 234 [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0, 235 [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0, 236 }, 237 .state = CONF_SG_PROTECTIVE, 238 }, 239 .rx = { 240 .rx_msdu_life_time = 512000, 241 .packet_detection_threshold = 0, 242 .ps_poll_timeout = 15, 243 .upsd_timeout = 15, 244 .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD, 245 .rx_cca_threshold = 0, 246 .irq_blk_threshold = 0xFFFF, 247 .irq_pkt_threshold = 0, 248 .irq_timeout = 600, 249 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY, 250 }, 251 .tx = { 252 .tx_energy_detection = 0, 253 .sta_rc_conf = { 254 .enabled_rates = 0, 255 .short_retry_limit = 10, 256 .long_retry_limit = 10, 257 .aflags = 0, 258 }, 259 .ac_conf_count = 4, 260 .ac_conf = { 261 [CONF_TX_AC_BE] = { 262 .ac = CONF_TX_AC_BE, 263 .cw_min = 15, 264 .cw_max = 63, 265 .aifsn = 3, 266 .tx_op_limit = 0, 267 }, 268 [CONF_TX_AC_BK] = { 269 .ac = CONF_TX_AC_BK, 270 .cw_min = 15, 271 .cw_max = 63, 272 .aifsn = 7, 273 .tx_op_limit = 0, 274 }, 275 [CONF_TX_AC_VI] = { 276 .ac = CONF_TX_AC_VI, 277 .cw_min = 15, 278 .cw_max = 63, 279 .aifsn = CONF_TX_AIFS_PIFS, 280 .tx_op_limit = 3008, 281 }, 282 [CONF_TX_AC_VO] = { 283 .ac = CONF_TX_AC_VO, 284 .cw_min = 15, 285 .cw_max = 63, 286 .aifsn = CONF_TX_AIFS_PIFS, 287 .tx_op_limit = 1504, 288 }, 289 }, 290 .max_tx_retries = 100, 291 .ap_aging_period = 300, 292 .tid_conf_count = 4, 293 .tid_conf = { 294 [CONF_TX_AC_BE] = { 295 .queue_id = CONF_TX_AC_BE, 296 .channel_type = CONF_CHANNEL_TYPE_EDCF, 297 .tsid = CONF_TX_AC_BE, 298 .ps_scheme = CONF_PS_SCHEME_LEGACY, 299 .ack_policy = CONF_ACK_POLICY_LEGACY, 300 .apsd_conf = {0, 0}, 301 }, 302 [CONF_TX_AC_BK] = { 303 .queue_id = CONF_TX_AC_BK, 304 .channel_type = CONF_CHANNEL_TYPE_EDCF, 305 .tsid = CONF_TX_AC_BK, 306 .ps_scheme = CONF_PS_SCHEME_LEGACY, 307 .ack_policy = CONF_ACK_POLICY_LEGACY, 308 .apsd_conf = {0, 0}, 309 }, 310 [CONF_TX_AC_VI] = { 311 .queue_id = CONF_TX_AC_VI, 312 .channel_type = CONF_CHANNEL_TYPE_EDCF, 313 .tsid = CONF_TX_AC_VI, 314 .ps_scheme = CONF_PS_SCHEME_LEGACY, 315 .ack_policy = CONF_ACK_POLICY_LEGACY, 316 .apsd_conf = {0, 0}, 317 }, 318 [CONF_TX_AC_VO] = { 319 .queue_id = CONF_TX_AC_VO, 320 .channel_type = CONF_CHANNEL_TYPE_EDCF, 321 .tsid = CONF_TX_AC_VO, 322 .ps_scheme = CONF_PS_SCHEME_LEGACY, 323 .ack_policy = CONF_ACK_POLICY_LEGACY, 324 .apsd_conf = {0, 0}, 325 }, 326 }, 327 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD, 328 .tx_compl_timeout = 350, 329 .tx_compl_threshold = 10, 330 .basic_rate = CONF_HW_BIT_RATE_1MBPS, 331 .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS, 332 .tmpl_short_retry_limit = 10, 333 .tmpl_long_retry_limit = 10, 334 .tx_watchdog_timeout = 5000, 335 }, 336 .conn = { 337 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM, 338 .listen_interval = 1, 339 .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM, 340 .suspend_listen_interval = 3, 341 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED, 342 .bcn_filt_ie_count = 3, 343 .bcn_filt_ie = { 344 [0] = { 345 .ie = WLAN_EID_CHANNEL_SWITCH, 346 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE, 347 }, 348 [1] = { 349 .ie = WLAN_EID_HT_OPERATION, 350 .rule = CONF_BCN_RULE_PASS_ON_CHANGE, 351 }, 352 [2] = { 353 .ie = WLAN_EID_ERP_INFO, 354 .rule = CONF_BCN_RULE_PASS_ON_CHANGE, 355 }, 356 }, 357 .synch_fail_thold = 12, 358 .bss_lose_timeout = 400, 359 .beacon_rx_timeout = 10000, 360 .broadcast_timeout = 20000, 361 .rx_broadcast_in_ps = 1, 362 .ps_poll_threshold = 10, 363 .bet_enable = CONF_BET_MODE_ENABLE, 364 .bet_max_consecutive = 50, 365 .psm_entry_retries = 8, 366 .psm_exit_retries = 16, 367 .psm_entry_nullfunc_retries = 3, 368 .dynamic_ps_timeout = 200, 369 .forced_ps = false, 370 .keep_alive_interval = 55000, 371 .max_listen_interval = 20, 372 }, 373 .itrim = { 374 .enable = false, 375 .timeout = 50000, 376 }, 377 .pm_config = { 378 .host_clk_settling_time = 5000, 379 .host_fast_wakeup_support = false 380 }, 381 .roam_trigger = { 382 .trigger_pacing = 1, 383 .avg_weight_rssi_beacon = 20, 384 .avg_weight_rssi_data = 10, 385 .avg_weight_snr_beacon = 20, 386 .avg_weight_snr_data = 10, 387 }, 388 .scan = { 389 .min_dwell_time_active = 7500, 390 .max_dwell_time_active = 30000, 391 .min_dwell_time_passive = 100000, 392 .max_dwell_time_passive = 100000, 393 .num_probe_reqs = 2, 394 .split_scan_timeout = 50000, 395 }, 396 .sched_scan = { 397 /* 398 * Values are in TU/1000 but since sched scan FW command 399 * params are in TUs rounding up may occur. 400 */ 401 .base_dwell_time = 7500, 402 .max_dwell_time_delta = 22500, 403 /* based on 250bits per probe @1Mbps */ 404 .dwell_time_delta_per_probe = 2000, 405 /* based on 250bits per probe @6Mbps (plus a bit more) */ 406 .dwell_time_delta_per_probe_5 = 350, 407 .dwell_time_passive = 100000, 408 .dwell_time_dfs = 150000, 409 .num_probe_reqs = 2, 410 .rssi_threshold = -90, 411 .snr_threshold = 0, 412 }, 413 .ht = { 414 .rx_ba_win_size = 10, 415 .tx_ba_win_size = 64, 416 .inactivity_timeout = 10000, 417 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP, 418 }, 419 .mem = { 420 .num_stations = 1, 421 .ssid_profiles = 1, 422 .rx_block_num = 40, 423 .tx_min_block_num = 40, 424 .dynamic_memory = 1, 425 .min_req_tx_blocks = 45, 426 .min_req_rx_blocks = 22, 427 .tx_min = 27, 428 }, 429 .fm_coex = { 430 .enable = true, 431 .swallow_period = 5, 432 .n_divider_fref_set_1 = 0xff, /* default */ 433 .n_divider_fref_set_2 = 12, 434 .m_divider_fref_set_1 = 0xffff, 435 .m_divider_fref_set_2 = 148, /* default */ 436 .coex_pll_stabilization_time = 0xffffffff, /* default */ 437 .ldo_stabilization_time = 0xffff, /* default */ 438 .fm_disturbed_band_margin = 0xff, /* default */ 439 .swallow_clk_diff = 0xff, /* default */ 440 }, 441 .rx_streaming = { 442 .duration = 150, 443 .queues = 0x1, 444 .interval = 20, 445 .always = 0, 446 }, 447 .fwlog = { 448 .mode = WL12XX_FWLOG_ON_DEMAND, 449 .mem_blocks = 2, 450 .severity = 0, 451 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED, 452 .output = WL12XX_FWLOG_OUTPUT_HOST, 453 .threshold = 0, 454 }, 455 .rate = { 456 .rate_retry_score = 32000, 457 .per_add = 8192, 458 .per_th1 = 2048, 459 .per_th2 = 4096, 460 .max_per = 8100, 461 .inverse_curiosity_factor = 5, 462 .tx_fail_low_th = 4, 463 .tx_fail_high_th = 10, 464 .per_alpha_shift = 4, 465 .per_add_shift = 13, 466 .per_beta1_shift = 10, 467 .per_beta2_shift = 8, 468 .rate_check_up = 2, 469 .rate_check_down = 12, 470 .rate_retry_policy = { 471 0x00, 0x00, 0x00, 0x00, 0x00, 472 0x00, 0x00, 0x00, 0x00, 0x00, 473 0x00, 0x00, 0x00, 474 }, 475 }, 476 .hangover = { 477 .recover_time = 0, 478 .hangover_period = 20, 479 .dynamic_mode = 1, 480 .early_termination_mode = 1, 481 .max_period = 20, 482 .min_period = 1, 483 .increase_delta = 1, 484 .decrease_delta = 2, 485 .quiet_time = 4, 486 .increase_time = 1, 487 .window_size = 16, 488 }, 489 }; 490 491 static struct wl18xx_priv_conf wl18xx_default_priv_conf = { 492 .phy = { 493 .phy_standalone = 0x00, 494 .primary_clock_setting_time = 0x05, 495 .clock_valid_on_wake_up = 0x00, 496 .secondary_clock_setting_time = 0x05, 497 .rdl = 0x01, 498 .auto_detect = 0x00, 499 .dedicated_fem = FEM_NONE, 500 .low_band_component = COMPONENT_2_WAY_SWITCH, 501 .low_band_component_type = 0x05, 502 .high_band_component = COMPONENT_2_WAY_SWITCH, 503 .high_band_component_type = 0x09, 504 .tcxo_ldo_voltage = 0x00, 505 .xtal_itrim_val = 0x04, 506 .srf_state = 0x00, 507 .io_configuration = 0x01, 508 .sdio_configuration = 0x00, 509 .settings = 0x00, 510 .enable_clpc = 0x00, 511 .enable_tx_low_pwr_on_siso_rdl = 0x00, 512 .rx_profile = 0x00, 513 .pwr_limit_reference_11_abg = 0xc8, 514 }, 515 }; 516 517 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = { 518 [PART_TOP_PRCM_ELP_SOC] = { 519 .mem = { .start = 0x00A02000, .size = 0x00010000 }, 520 .reg = { .start = 0x00807000, .size = 0x00005000 }, 521 .mem2 = { .start = 0x00800000, .size = 0x0000B000 }, 522 .mem3 = { .start = 0x00000000, .size = 0x00000000 }, 523 }, 524 [PART_DOWN] = { 525 .mem = { .start = 0x00000000, .size = 0x00014000 }, 526 .reg = { .start = 0x00810000, .size = 0x0000BFFF }, 527 .mem2 = { .start = 0x00000000, .size = 0x00000000 }, 528 .mem3 = { .start = 0x00000000, .size = 0x00000000 }, 529 }, 530 [PART_BOOT] = { 531 .mem = { .start = 0x00700000, .size = 0x0000030c }, 532 .reg = { .start = 0x00802000, .size = 0x00014578 }, 533 .mem2 = { .start = 0x00B00404, .size = 0x00001000 }, 534 .mem3 = { .start = 0x00C00000, .size = 0x00000400 }, 535 }, 536 [PART_WORK] = { 537 .mem = { .start = 0x00800000, .size = 0x000050FC }, 538 .reg = { .start = 0x00B00404, .size = 0x00001000 }, 539 .mem2 = { .start = 0x00C00000, .size = 0x00000400 }, 540 .mem3 = { .start = 0x00000000, .size = 0x00000000 }, 541 }, 542 [PART_PHY_INIT] = { 543 .mem = { .start = 0x80926000, 544 .size = sizeof(struct wl18xx_mac_and_phy_params) }, 545 .reg = { .start = 0x00000000, .size = 0x00000000 }, 546 .mem2 = { .start = 0x00000000, .size = 0x00000000 }, 547 .mem3 = { .start = 0x00000000, .size = 0x00000000 }, 548 }, 549 }; 550 551 static const int wl18xx_rtable[REG_TABLE_LEN] = { 552 [REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL, 553 [REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR, 554 [REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK, 555 [REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR, 556 [REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR, 557 [REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H, 558 [REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK, 559 [REG_PC_ON_RECOVERY] = WL18XX_SCR_PAD4, 560 [REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B, 561 [REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS, 562 563 /* data access memory addresses, used with partition translation */ 564 [REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA, 565 [REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA, 566 567 /* raw data access memory addresses */ 568 [REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR, 569 }; 570 571 static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = { 572 [CLOCK_CONFIG_16_2_M] = { 7, 104, 801, 4, true }, 573 [CLOCK_CONFIG_16_368_M] = { 9, 132, 3751, 4, true }, 574 [CLOCK_CONFIG_16_8_M] = { 7, 100, 0, 0, false }, 575 [CLOCK_CONFIG_19_2_M] = { 8, 100, 0, 0, false }, 576 [CLOCK_CONFIG_26_M] = { 13, 120, 0, 0, false }, 577 [CLOCK_CONFIG_32_736_M] = { 9, 132, 3751, 4, true }, 578 [CLOCK_CONFIG_33_6_M] = { 7, 100, 0, 0, false }, 579 [CLOCK_CONFIG_38_468_M] = { 8, 100, 0, 0, false }, 580 [CLOCK_CONFIG_52_M] = { 13, 120, 0, 0, false }, 581 }; 582 583 /* TODO: maybe move to a new header file? */ 584 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw.bin" 585 586 static int wl18xx_identify_chip(struct wl1271 *wl) 587 { 588 int ret = 0; 589 590 switch (wl->chip.id) { 591 case CHIP_ID_185x_PG20: 592 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG20)", 593 wl->chip.id); 594 wl->sr_fw_name = WL18XX_FW_NAME; 595 /* wl18xx uses the same firmware for PLT */ 596 wl->plt_fw_name = WL18XX_FW_NAME; 597 wl->quirks |= WLCORE_QUIRK_NO_ELP | 598 WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED | 599 WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN; 600 601 break; 602 case CHIP_ID_185x_PG10: 603 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG10)", 604 wl->chip.id); 605 wl->sr_fw_name = WL18XX_FW_NAME; 606 /* wl18xx uses the same firmware for PLT */ 607 wl->plt_fw_name = WL18XX_FW_NAME; 608 wl->quirks |= WLCORE_QUIRK_NO_ELP | 609 WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED | 610 WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN | 611 WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN; 612 613 /* PG 1.0 has some problems with MCS_13, so disable it */ 614 wl->ht_cap[IEEE80211_BAND_2GHZ].mcs.rx_mask[1] &= ~BIT(5); 615 616 break; 617 default: 618 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id); 619 ret = -ENODEV; 620 goto out; 621 } 622 623 out: 624 return ret; 625 } 626 627 static void wl18xx_set_clk(struct wl1271 *wl) 628 { 629 u32 clk_freq; 630 631 wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); 632 633 /* TODO: PG2: apparently we need to read the clk type */ 634 635 clk_freq = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT); 636 wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq, 637 wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m, 638 wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q, 639 wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit"); 640 641 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N, wl18xx_clk_table[clk_freq].n); 642 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M, wl18xx_clk_table[clk_freq].m); 643 644 if (wl18xx_clk_table[clk_freq].swallow) { 645 /* first the 16 lower bits */ 646 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1, 647 wl18xx_clk_table[clk_freq].q & 648 PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK); 649 /* then the 16 higher bits, masked out */ 650 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2, 651 (wl18xx_clk_table[clk_freq].q >> 16) & 652 PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK); 653 654 /* first the 16 lower bits */ 655 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1, 656 wl18xx_clk_table[clk_freq].p & 657 PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK); 658 /* then the 16 higher bits, masked out */ 659 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2, 660 (wl18xx_clk_table[clk_freq].p >> 16) & 661 PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK); 662 } else { 663 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN, 664 PLLSH_WCS_PLL_SWALLOW_EN_VAL2); 665 } 666 } 667 668 static void wl18xx_boot_soft_reset(struct wl1271 *wl) 669 { 670 /* disable Rx/Tx */ 671 wl1271_write32(wl, WL18XX_ENABLE, 0x0); 672 673 /* disable auto calibration on start*/ 674 wl1271_write32(wl, WL18XX_SPARE_A2, 0xffff); 675 } 676 677 static int wl18xx_pre_boot(struct wl1271 *wl) 678 { 679 wl18xx_set_clk(wl); 680 681 /* Continue the ELP wake up sequence */ 682 wl1271_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL); 683 udelay(500); 684 685 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); 686 687 /* Disable interrupts */ 688 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); 689 690 wl18xx_boot_soft_reset(wl); 691 692 return 0; 693 } 694 695 static void wl18xx_pre_upload(struct wl1271 *wl) 696 { 697 u32 tmp; 698 699 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); 700 701 /* TODO: check if this is all needed */ 702 wl1271_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND); 703 704 tmp = wlcore_read_reg(wl, REG_CHIP_ID_B); 705 706 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp); 707 708 tmp = wl1271_read32(wl, WL18XX_SCR_PAD2); 709 } 710 711 static void wl18xx_set_mac_and_phy(struct wl1271 *wl) 712 { 713 struct wl18xx_priv *priv = wl->priv; 714 struct wl18xx_conf_phy *phy = &priv->conf.phy; 715 struct wl18xx_mac_and_phy_params params; 716 717 memset(¶ms, 0, sizeof(params)); 718 719 params.phy_standalone = phy->phy_standalone; 720 params.rdl = phy->rdl; 721 params.enable_clpc = phy->enable_clpc; 722 params.enable_tx_low_pwr_on_siso_rdl = 723 phy->enable_tx_low_pwr_on_siso_rdl; 724 params.auto_detect = phy->auto_detect; 725 params.dedicated_fem = phy->dedicated_fem; 726 params.low_band_component = phy->low_band_component; 727 params.low_band_component_type = 728 phy->low_band_component_type; 729 params.high_band_component = phy->high_band_component; 730 params.high_band_component_type = 731 phy->high_band_component_type; 732 params.number_of_assembled_ant2_4 = 733 n_antennas_2_param; 734 params.number_of_assembled_ant5 = 735 n_antennas_5_param; 736 params.external_pa_dc2dc = dc2dc_param; 737 params.tcxo_ldo_voltage = phy->tcxo_ldo_voltage; 738 params.xtal_itrim_val = phy->xtal_itrim_val; 739 params.srf_state = phy->srf_state; 740 params.io_configuration = phy->io_configuration; 741 params.sdio_configuration = phy->sdio_configuration; 742 params.settings = phy->settings; 743 params.rx_profile = phy->rx_profile; 744 params.primary_clock_setting_time = 745 phy->primary_clock_setting_time; 746 params.clock_valid_on_wake_up = 747 phy->clock_valid_on_wake_up; 748 params.secondary_clock_setting_time = 749 phy->secondary_clock_setting_time; 750 params.pwr_limit_reference_11_abg = 751 phy->pwr_limit_reference_11_abg; 752 753 params.board_type = priv->board_type; 754 755 wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]); 756 wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)¶ms, 757 sizeof(params), false); 758 } 759 760 static void wl18xx_enable_interrupts(struct wl1271 *wl) 761 { 762 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_ALL_EVENTS_VECTOR); 763 764 wlcore_enable_interrupts(wl); 765 wlcore_write_reg(wl, REG_INTERRUPT_MASK, 766 WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK)); 767 } 768 769 static int wl18xx_boot(struct wl1271 *wl) 770 { 771 int ret; 772 773 ret = wl18xx_pre_boot(wl); 774 if (ret < 0) 775 goto out; 776 777 wl18xx_pre_upload(wl); 778 779 ret = wlcore_boot_upload_firmware(wl); 780 if (ret < 0) 781 goto out; 782 783 wl18xx_set_mac_and_phy(wl); 784 785 ret = wlcore_boot_run_firmware(wl); 786 if (ret < 0) 787 goto out; 788 789 wl18xx_enable_interrupts(wl); 790 791 out: 792 return ret; 793 } 794 795 static void wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr, 796 void *buf, size_t len) 797 { 798 struct wl18xx_priv *priv = wl->priv; 799 800 memcpy(priv->cmd_buf, buf, len); 801 memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len); 802 803 wl1271_write(wl, cmd_box_addr, priv->cmd_buf, WL18XX_CMD_MAX_SIZE, 804 false); 805 } 806 807 static void wl18xx_ack_event(struct wl1271 *wl) 808 { 809 wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL18XX_INTR_TRIG_EVENT_ACK); 810 } 811 812 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks) 813 { 814 u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE; 815 return (len + blk_size - 1) / blk_size + spare_blks; 816 } 817 818 static void 819 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc, 820 u32 blks, u32 spare_blks) 821 { 822 desc->wl18xx_mem.total_mem_blocks = blks; 823 desc->wl18xx_mem.reserved = 0; 824 } 825 826 static void 827 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc, 828 struct sk_buff *skb) 829 { 830 desc->length = cpu_to_le16(skb->len); 831 832 wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d " 833 "len: %d life: %d mem: %d", desc->hlid, 834 le16_to_cpu(desc->length), 835 le16_to_cpu(desc->life_time), 836 desc->wl18xx_mem.total_mem_blocks); 837 } 838 839 static enum wl_rx_buf_align 840 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc) 841 { 842 if (rx_desc & RX_BUF_PADDED_PAYLOAD) 843 return WLCORE_RX_BUF_PADDED; 844 845 return WLCORE_RX_BUF_ALIGNED; 846 } 847 848 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data, 849 u32 data_len) 850 { 851 struct wl1271_rx_descriptor *desc = rx_data; 852 853 /* invalid packet */ 854 if (data_len < sizeof(*desc)) 855 return 0; 856 857 return data_len - sizeof(*desc); 858 } 859 860 static void wl18xx_tx_immediate_completion(struct wl1271 *wl) 861 { 862 wl18xx_tx_immediate_complete(wl); 863 } 864 865 static int wl18xx_set_host_cfg_bitmap(struct wl1271 *wl, u32 extra_mem_blk) 866 { 867 int ret; 868 u32 sdio_align_size = 0; 869 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE | 870 HOST_IF_CFG_ADD_RX_ALIGNMENT; 871 872 /* Enable Tx SDIO padding */ 873 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) { 874 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK; 875 sdio_align_size = WL12XX_BUS_BLOCK_SIZE; 876 } 877 878 /* Enable Rx SDIO padding */ 879 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) { 880 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK; 881 sdio_align_size = WL12XX_BUS_BLOCK_SIZE; 882 } 883 884 ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap, 885 sdio_align_size, extra_mem_blk, 886 WL18XX_HOST_IF_LEN_SIZE_FIELD); 887 if (ret < 0) 888 return ret; 889 890 return 0; 891 } 892 893 static int wl18xx_hw_init(struct wl1271 *wl) 894 { 895 int ret; 896 struct wl18xx_priv *priv = wl->priv; 897 898 /* (re)init private structures. Relevant on recovery as well. */ 899 priv->last_fw_rls_idx = 0; 900 priv->extra_spare_vif_count = 0; 901 902 /* set the default amount of spare blocks in the bitmap */ 903 ret = wl18xx_set_host_cfg_bitmap(wl, WL18XX_TX_HW_BLOCK_SPARE); 904 if (ret < 0) 905 return ret; 906 907 if (checksum_param) { 908 ret = wl18xx_acx_set_checksum_state(wl); 909 if (ret != 0) 910 return ret; 911 } 912 913 return ret; 914 } 915 916 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl, 917 struct wl1271_tx_hw_descr *desc, 918 struct sk_buff *skb) 919 { 920 u32 ip_hdr_offset; 921 struct iphdr *ip_hdr; 922 923 if (!checksum_param) { 924 desc->wl18xx_checksum_data = 0; 925 return; 926 } 927 928 if (skb->ip_summed != CHECKSUM_PARTIAL) { 929 desc->wl18xx_checksum_data = 0; 930 return; 931 } 932 933 ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb); 934 if (WARN_ON(ip_hdr_offset >= (1<<7))) { 935 desc->wl18xx_checksum_data = 0; 936 return; 937 } 938 939 desc->wl18xx_checksum_data = ip_hdr_offset << 1; 940 941 /* FW is interested only in the LSB of the protocol TCP=0 UDP=1 */ 942 ip_hdr = (void *)skb_network_header(skb); 943 desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01); 944 } 945 946 static void wl18xx_set_rx_csum(struct wl1271 *wl, 947 struct wl1271_rx_descriptor *desc, 948 struct sk_buff *skb) 949 { 950 if (desc->status & WL18XX_RX_CHECKSUM_MASK) 951 skb->ip_summed = CHECKSUM_UNNECESSARY; 952 } 953 954 /* 955 * TODO: instead of having these two functions to get the rate mask, 956 * we should modify the wlvif->rate_set instead 957 */ 958 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl, 959 struct wl12xx_vif *wlvif) 960 { 961 u32 hw_rate_set = wlvif->rate_set; 962 963 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS || 964 wlvif->channel_type == NL80211_CHAN_HT40PLUS) { 965 wl1271_debug(DEBUG_ACX, "using wide channel rate mask"); 966 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN; 967 968 /* we don't support MIMO in wide-channel mode */ 969 hw_rate_set &= ~CONF_TX_MIMO_RATES; 970 } 971 972 return hw_rate_set; 973 } 974 975 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl, 976 struct wl12xx_vif *wlvif) 977 { 978 if ((wlvif->channel_type == NL80211_CHAN_HT40MINUS || 979 wlvif->channel_type == NL80211_CHAN_HT40PLUS) && 980 !strcmp(ht_mode_param, "wide")) { 981 wl1271_debug(DEBUG_ACX, "using wide channel rate mask"); 982 return CONF_TX_RATE_USE_WIDE_CHAN; 983 } else if (!strcmp(ht_mode_param, "mimo")) { 984 wl1271_debug(DEBUG_ACX, "using MIMO rate mask"); 985 986 /* 987 * PG 1.0 has some problems with MCS_13, so disable it 988 * 989 * TODO: instead of hacking this in here, we should 990 * make it more general and change a bit in the 991 * wlvif->rate_set instead. 992 */ 993 if (wl->chip.id == CHIP_ID_185x_PG10) 994 return CONF_TX_MIMO_RATES & ~CONF_HW_BIT_RATE_MCS_13; 995 996 return CONF_TX_MIMO_RATES; 997 } else { 998 return 0; 999 } 1000 } 1001 1002 static s8 wl18xx_get_pg_ver(struct wl1271 *wl) 1003 { 1004 u32 fuse; 1005 1006 wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); 1007 1008 fuse = wl1271_read32(wl, WL18XX_REG_FUSE_DATA_1_3); 1009 fuse = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET; 1010 1011 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); 1012 1013 return (s8)fuse; 1014 } 1015 1016 static void wl18xx_conf_init(struct wl1271 *wl) 1017 { 1018 struct wl18xx_priv *priv = wl->priv; 1019 1020 /* apply driver default configuration */ 1021 memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf)); 1022 1023 /* apply default private configuration */ 1024 memcpy(&priv->conf, &wl18xx_default_priv_conf, sizeof(priv->conf)); 1025 } 1026 1027 static int wl18xx_plt_init(struct wl1271 *wl) 1028 { 1029 wl1271_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT); 1030 1031 return wl->ops->boot(wl); 1032 } 1033 1034 static void wl18xx_get_mac(struct wl1271 *wl) 1035 { 1036 u32 mac1, mac2; 1037 1038 wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); 1039 1040 mac1 = wl1271_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1); 1041 mac2 = wl1271_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2); 1042 1043 /* these are the two parts of the BD_ADDR */ 1044 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) + 1045 ((mac1 & 0xff000000) >> 24); 1046 wl->fuse_nic_addr = (mac1 & 0xffffff); 1047 1048 wlcore_set_partition(wl, &wl->ptable[PART_DOWN]); 1049 } 1050 1051 static int wl18xx_handle_static_data(struct wl1271 *wl, 1052 struct wl1271_static_data *static_data) 1053 { 1054 struct wl18xx_static_data_priv *static_data_priv = 1055 (struct wl18xx_static_data_priv *) static_data->priv; 1056 1057 wl1271_info("PHY firmware version: %s", static_data_priv->phy_version); 1058 1059 return 0; 1060 } 1061 1062 static int wl18xx_get_spare_blocks(struct wl1271 *wl, bool is_gem) 1063 { 1064 struct wl18xx_priv *priv = wl->priv; 1065 1066 /* If we have VIFs requiring extra spare, indulge them */ 1067 if (priv->extra_spare_vif_count) 1068 return WL18XX_TX_HW_EXTRA_BLOCK_SPARE; 1069 1070 return WL18XX_TX_HW_BLOCK_SPARE; 1071 } 1072 1073 static int wl18xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd, 1074 struct ieee80211_vif *vif, 1075 struct ieee80211_sta *sta, 1076 struct ieee80211_key_conf *key_conf) 1077 { 1078 struct wl18xx_priv *priv = wl->priv; 1079 bool change_spare = false; 1080 int ret; 1081 1082 /* 1083 * when adding the first or removing the last GEM/TKIP interface, 1084 * we have to adjust the number of spare blocks. 1085 */ 1086 change_spare = (key_conf->cipher == WL1271_CIPHER_SUITE_GEM || 1087 key_conf->cipher == WLAN_CIPHER_SUITE_TKIP) && 1088 ((priv->extra_spare_vif_count == 0 && cmd == SET_KEY) || 1089 (priv->extra_spare_vif_count == 1 && cmd == DISABLE_KEY)); 1090 1091 /* no need to change spare - just regular set_key */ 1092 if (!change_spare) 1093 return wlcore_set_key(wl, cmd, vif, sta, key_conf); 1094 1095 /* 1096 * stop the queues and flush to ensure the next packets are 1097 * in sync with FW spare block accounting 1098 */ 1099 wlcore_stop_queues(wl, WLCORE_QUEUE_STOP_REASON_SPARE_BLK); 1100 wl1271_tx_flush(wl); 1101 1102 ret = wlcore_set_key(wl, cmd, vif, sta, key_conf); 1103 if (ret < 0) 1104 goto out; 1105 1106 /* key is now set, change the spare blocks */ 1107 if (cmd == SET_KEY) { 1108 ret = wl18xx_set_host_cfg_bitmap(wl, 1109 WL18XX_TX_HW_EXTRA_BLOCK_SPARE); 1110 if (ret < 0) 1111 goto out; 1112 1113 priv->extra_spare_vif_count++; 1114 } else { 1115 ret = wl18xx_set_host_cfg_bitmap(wl, 1116 WL18XX_TX_HW_BLOCK_SPARE); 1117 if (ret < 0) 1118 goto out; 1119 1120 priv->extra_spare_vif_count--; 1121 } 1122 1123 out: 1124 wlcore_wake_queues(wl, WLCORE_QUEUE_STOP_REASON_SPARE_BLK); 1125 return ret; 1126 } 1127 1128 static struct wlcore_ops wl18xx_ops = { 1129 .identify_chip = wl18xx_identify_chip, 1130 .boot = wl18xx_boot, 1131 .plt_init = wl18xx_plt_init, 1132 .trigger_cmd = wl18xx_trigger_cmd, 1133 .ack_event = wl18xx_ack_event, 1134 .calc_tx_blocks = wl18xx_calc_tx_blocks, 1135 .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks, 1136 .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len, 1137 .get_rx_buf_align = wl18xx_get_rx_buf_align, 1138 .get_rx_packet_len = wl18xx_get_rx_packet_len, 1139 .tx_immediate_compl = wl18xx_tx_immediate_completion, 1140 .tx_delayed_compl = NULL, 1141 .hw_init = wl18xx_hw_init, 1142 .set_tx_desc_csum = wl18xx_set_tx_desc_csum, 1143 .get_pg_ver = wl18xx_get_pg_ver, 1144 .set_rx_csum = wl18xx_set_rx_csum, 1145 .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask, 1146 .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask, 1147 .get_mac = wl18xx_get_mac, 1148 .debugfs_init = wl18xx_debugfs_add_files, 1149 .handle_static_data = wl18xx_handle_static_data, 1150 .get_spare_blocks = wl18xx_get_spare_blocks, 1151 .set_key = wl18xx_set_key, 1152 }; 1153 1154 /* HT cap appropriate for wide channels */ 1155 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap = { 1156 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 | 1157 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40, 1158 .ht_supported = true, 1159 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K, 1160 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 1161 .mcs = { 1162 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 1163 .rx_highest = cpu_to_le16(150), 1164 .tx_params = IEEE80211_HT_MCS_TX_DEFINED, 1165 }, 1166 }; 1167 1168 /* HT cap appropriate for SISO 20 */ 1169 static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = { 1170 .cap = IEEE80211_HT_CAP_SGI_20, 1171 .ht_supported = true, 1172 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K, 1173 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 1174 .mcs = { 1175 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 1176 .rx_highest = cpu_to_le16(72), 1177 .tx_params = IEEE80211_HT_MCS_TX_DEFINED, 1178 }, 1179 }; 1180 1181 /* HT cap appropriate for MIMO rates in 20mhz channel */ 1182 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_2ghz = { 1183 .cap = IEEE80211_HT_CAP_SGI_20, 1184 .ht_supported = true, 1185 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K, 1186 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 1187 .mcs = { 1188 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, }, 1189 .rx_highest = cpu_to_le16(144), 1190 .tx_params = IEEE80211_HT_MCS_TX_DEFINED, 1191 }, 1192 }; 1193 1194 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_5ghz = { 1195 .cap = IEEE80211_HT_CAP_SGI_20, 1196 .ht_supported = true, 1197 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K, 1198 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 1199 .mcs = { 1200 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 1201 .rx_highest = cpu_to_le16(72), 1202 .tx_params = IEEE80211_HT_MCS_TX_DEFINED, 1203 }, 1204 }; 1205 1206 static int __devinit wl18xx_probe(struct platform_device *pdev) 1207 { 1208 struct wl1271 *wl; 1209 struct ieee80211_hw *hw; 1210 struct wl18xx_priv *priv; 1211 1212 hw = wlcore_alloc_hw(sizeof(*priv)); 1213 if (IS_ERR(hw)) { 1214 wl1271_error("can't allocate hw"); 1215 return PTR_ERR(hw); 1216 } 1217 1218 wl = hw->priv; 1219 priv = wl->priv; 1220 wl->ops = &wl18xx_ops; 1221 wl->ptable = wl18xx_ptable; 1222 wl->rtable = wl18xx_rtable; 1223 wl->num_tx_desc = 32; 1224 wl->num_rx_desc = 16; 1225 wl->band_rate_to_idx = wl18xx_band_rate_to_idx; 1226 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX; 1227 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0; 1228 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv); 1229 wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics); 1230 wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv); 1231 1232 if (!strcmp(ht_mode_param, "wide")) { 1233 memcpy(&wl->ht_cap[IEEE80211_BAND_2GHZ], 1234 &wl18xx_siso40_ht_cap, 1235 sizeof(wl18xx_siso40_ht_cap)); 1236 memcpy(&wl->ht_cap[IEEE80211_BAND_5GHZ], 1237 &wl18xx_siso40_ht_cap, 1238 sizeof(wl18xx_siso40_ht_cap)); 1239 } else if (!strcmp(ht_mode_param, "mimo")) { 1240 memcpy(&wl->ht_cap[IEEE80211_BAND_2GHZ], 1241 &wl18xx_mimo_ht_cap_2ghz, 1242 sizeof(wl18xx_mimo_ht_cap_2ghz)); 1243 memcpy(&wl->ht_cap[IEEE80211_BAND_5GHZ], 1244 &wl18xx_mimo_ht_cap_5ghz, 1245 sizeof(wl18xx_mimo_ht_cap_5ghz)); 1246 } else if (!strcmp(ht_mode_param, "siso20")) { 1247 memcpy(&wl->ht_cap[IEEE80211_BAND_2GHZ], 1248 &wl18xx_siso20_ht_cap, 1249 sizeof(wl18xx_siso20_ht_cap)); 1250 memcpy(&wl->ht_cap[IEEE80211_BAND_5GHZ], 1251 &wl18xx_siso20_ht_cap, 1252 sizeof(wl18xx_siso20_ht_cap)); 1253 } else { 1254 wl1271_error("invalid ht_mode '%s'", ht_mode_param); 1255 goto out_free; 1256 } 1257 1258 wl18xx_conf_init(wl); 1259 1260 if (!strcmp(board_type_param, "fpga")) { 1261 priv->board_type = BOARD_TYPE_FPGA_18XX; 1262 } else if (!strcmp(board_type_param, "hdk")) { 1263 priv->board_type = BOARD_TYPE_HDK_18XX; 1264 /* HACK! Just for now we hardcode HDK to 0x06 */ 1265 priv->conf.phy.low_band_component_type = 0x06; 1266 } else if (!strcmp(board_type_param, "dvp")) { 1267 priv->board_type = BOARD_TYPE_DVP_18XX; 1268 } else if (!strcmp(board_type_param, "evb")) { 1269 priv->board_type = BOARD_TYPE_EVB_18XX; 1270 } else if (!strcmp(board_type_param, "com8")) { 1271 priv->board_type = BOARD_TYPE_COM8_18XX; 1272 /* HACK! Just for now we hardcode COM8 to 0x06 */ 1273 priv->conf.phy.low_band_component_type = 0x06; 1274 } else { 1275 wl1271_error("invalid board type '%s'", board_type_param); 1276 goto out_free; 1277 } 1278 1279 /* 1280 * If the module param is not set, update it with the one from 1281 * conf. If it is set, overwrite conf with it. 1282 */ 1283 if (low_band_component == -1) 1284 low_band_component = priv->conf.phy.low_band_component; 1285 else 1286 priv->conf.phy.low_band_component = low_band_component; 1287 if (low_band_component_type == -1) 1288 low_band_component_type = 1289 priv->conf.phy.low_band_component_type; 1290 else 1291 priv->conf.phy.low_band_component_type = 1292 low_band_component_type; 1293 1294 if (high_band_component == -1) 1295 high_band_component = priv->conf.phy.high_band_component; 1296 else 1297 priv->conf.phy.high_band_component = high_band_component; 1298 if (high_band_component_type == -1) 1299 high_band_component_type = 1300 priv->conf.phy.high_band_component_type; 1301 else 1302 priv->conf.phy.high_band_component_type = 1303 high_band_component_type; 1304 1305 if (pwr_limit_reference_11_abg == -1) 1306 pwr_limit_reference_11_abg = 1307 priv->conf.phy.pwr_limit_reference_11_abg; 1308 else 1309 priv->conf.phy.pwr_limit_reference_11_abg = 1310 pwr_limit_reference_11_abg; 1311 1312 if (!checksum_param) { 1313 wl18xx_ops.set_rx_csum = NULL; 1314 wl18xx_ops.init_vif = NULL; 1315 } 1316 1317 wl->enable_11a = enable_11a_param; 1318 1319 return wlcore_probe(wl, pdev); 1320 1321 out_free: 1322 wlcore_free_hw(wl); 1323 return -EINVAL; 1324 } 1325 1326 static const struct platform_device_id wl18xx_id_table[] __devinitconst = { 1327 { "wl18xx", 0 }, 1328 { } /* Terminating Entry */ 1329 }; 1330 MODULE_DEVICE_TABLE(platform, wl18xx_id_table); 1331 1332 static struct platform_driver wl18xx_driver = { 1333 .probe = wl18xx_probe, 1334 .remove = __devexit_p(wlcore_remove), 1335 .id_table = wl18xx_id_table, 1336 .driver = { 1337 .name = "wl18xx_driver", 1338 .owner = THIS_MODULE, 1339 } 1340 }; 1341 1342 static int __init wl18xx_init(void) 1343 { 1344 return platform_driver_register(&wl18xx_driver); 1345 } 1346 module_init(wl18xx_init); 1347 1348 static void __exit wl18xx_exit(void) 1349 { 1350 platform_driver_unregister(&wl18xx_driver); 1351 } 1352 module_exit(wl18xx_exit); 1353 1354 module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR); 1355 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide (default), mimo or siso20"); 1356 1357 module_param_named(board_type, board_type_param, charp, S_IRUSR); 1358 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or " 1359 "dvp"); 1360 1361 module_param_named(dc2dc, dc2dc_param, bool, S_IRUSR); 1362 MODULE_PARM_DESC(dc2dc, "External DC2DC: boolean (defaults to false)"); 1363 1364 module_param_named(n_antennas_2, n_antennas_2_param, uint, S_IRUSR); 1365 MODULE_PARM_DESC(n_antennas_2, "Number of installed 2.4GHz antennas: 1 (default) or 2"); 1366 1367 module_param_named(n_antennas_5, n_antennas_5_param, uint, S_IRUSR); 1368 MODULE_PARM_DESC(n_antennas_5, "Number of installed 5GHz antennas: 1 (default) or 2"); 1369 1370 module_param_named(checksum, checksum_param, bool, S_IRUSR); 1371 MODULE_PARM_DESC(checksum, "Enable TCP checksum: boolean (defaults to false)"); 1372 1373 module_param_named(enable_11a, enable_11a_param, bool, S_IRUSR); 1374 MODULE_PARM_DESC(enable_11a, "Enable 11a (5GHz): boolean (defaults to true)"); 1375 1376 module_param(low_band_component, uint, S_IRUSR); 1377 MODULE_PARM_DESC(low_band_component, "Low band component: u8 " 1378 "(default is 0x01)"); 1379 1380 module_param(low_band_component_type, uint, S_IRUSR); 1381 MODULE_PARM_DESC(low_band_component_type, "Low band component type: u8 " 1382 "(default is 0x05 or 0x06 depending on the board_type)"); 1383 1384 module_param(high_band_component, uint, S_IRUSR); 1385 MODULE_PARM_DESC(high_band_component, "High band component: u8, " 1386 "(default is 0x01)"); 1387 1388 module_param(high_band_component_type, uint, S_IRUSR); 1389 MODULE_PARM_DESC(high_band_component_type, "High band component type: u8 " 1390 "(default is 0x09)"); 1391 1392 module_param(pwr_limit_reference_11_abg, uint, S_IRUSR); 1393 MODULE_PARM_DESC(pwr_limit_reference_11_abg, "Power limit reference: u8 " 1394 "(default is 0xc8)"); 1395 1396 MODULE_LICENSE("GPL v2"); 1397 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>"); 1398 MODULE_FIRMWARE(WL18XX_FW_NAME); 1399