main.c (7fc00a3054b70b1794c2d64db703eb467ad0365c) main.c (4b883f021b9ccf2df3d14425e6e610281fb6a35e)
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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177 AR_SREV_9550(sc->sc_ah))
178 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
179 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
180
181 ath_start_rx_poll(sc, 3);
182 ath_start_ani(sc);
183}
184
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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177 AR_SREV_9550(sc->sc_ah))
178 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
179 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
180
181 ath_start_rx_poll(sc, 3);
182 ath_start_ani(sc);
183}
184
185static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
185static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx)
186{
187 struct ath_hw *ah = sc->sc_ah;
188 bool ret = true;
189
190 ieee80211_stop_queues(sc->hw);
191
192 sc->hw_busy_count = 0;
193 ath_stop_ani(sc);

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199 tasklet_disable(&sc->intr_tq);
200
201 if (!ath_stoprecv(sc))
202 ret = false;
203
204 if (!ath_drain_all_txq(sc, retry_tx))
205 ret = false;
206
186{
187 struct ath_hw *ah = sc->sc_ah;
188 bool ret = true;
189
190 ieee80211_stop_queues(sc->hw);
191
192 sc->hw_busy_count = 0;
193 ath_stop_ani(sc);

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199 tasklet_disable(&sc->intr_tq);
200
201 if (!ath_stoprecv(sc))
202 ret = false;
203
204 if (!ath_drain_all_txq(sc, retry_tx))
205 ret = false;
206
207 if (!flush) {
208 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
209 ath_rx_tasklet(sc, 1, true);
210 ath_rx_tasklet(sc, 1, false);
211 } else {
212 ath_flushrecv(sc);
213 }
214
215 tasklet_enable(&sc->intr_tq);
216
217 return ret;
218}
219
220static bool ath_complete_reset(struct ath_softc *sc, bool start)
221{
222 struct ath_hw *ah = sc->sc_ah;

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261
262static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
263 bool retry_tx)
264{
265 struct ath_hw *ah = sc->sc_ah;
266 struct ath_common *common = ath9k_hw_common(ah);
267 struct ath9k_hw_cal_data *caldata = NULL;
268 bool fastcc = true;
207 tasklet_enable(&sc->intr_tq);
208
209 return ret;
210}
211
212static bool ath_complete_reset(struct ath_softc *sc, bool start)
213{
214 struct ath_hw *ah = sc->sc_ah;

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253
254static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
255 bool retry_tx)
256{
257 struct ath_hw *ah = sc->sc_ah;
258 struct ath_common *common = ath9k_hw_common(ah);
259 struct ath9k_hw_cal_data *caldata = NULL;
260 bool fastcc = true;
269 bool flush = false;
270 int r;
271
272 __ath_cancel_work(sc);
273
274 spin_lock_bh(&sc->sc_pcu_lock);
275
276 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
277 fastcc = false;
278 caldata = &sc->caldata;
279 }
280
281 if (!hchan) {
282 fastcc = false;
261 int r;
262
263 __ath_cancel_work(sc);
264
265 spin_lock_bh(&sc->sc_pcu_lock);
266
267 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
268 fastcc = false;
269 caldata = &sc->caldata;
270 }
271
272 if (!hchan) {
273 fastcc = false;
283 flush = true;
284 hchan = ah->curchan;
285 }
286
274 hchan = ah->curchan;
275 }
276
287 if (!ath_prepare_reset(sc, retry_tx, flush))
277 if (!ath_prepare_reset(sc, retry_tx))
288 fastcc = false;
289
290 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
291 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
292
293 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
294 if (r) {
295 ath_err(common,

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803
804 spin_lock_bh(&sc->sc_pcu_lock);
805
806 if (ah->led_pin >= 0) {
807 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
808 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
809 }
810
278 fastcc = false;
279
280 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
281 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
282
283 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
284 if (r) {
285 ath_err(common,

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793
794 spin_lock_bh(&sc->sc_pcu_lock);
795
796 if (ah->led_pin >= 0) {
797 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
798 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
799 }
800
811 ath_prepare_reset(sc, false, true);
801 ath_prepare_reset(sc, false);
812
813 if (sc->rx.frag) {
814 dev_kfree_skb_any(sc->rx.frag);
815 sc->rx.frag = NULL;
816 }
817
818 if (!ah->curchan)
819 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);

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803 if (sc->rx.frag) {
804 dev_kfree_skb_any(sc->rx.frag);
805 sc->rx.frag = NULL;
806 }
807
808 if (!ah->curchan)
809 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);

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