1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 static void ath9k_set_assoc_state(struct ath_softc *sc, 23 struct ieee80211_vif *vif); 24 25 u8 ath9k_parse_mpdudensity(u8 mpdudensity) 26 { 27 /* 28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 29 * 0 for no restriction 30 * 1 for 1/4 us 31 * 2 for 1/2 us 32 * 3 for 1 us 33 * 4 for 2 us 34 * 5 for 4 us 35 * 6 for 8 us 36 * 7 for 16 us 37 */ 38 switch (mpdudensity) { 39 case 0: 40 return 0; 41 case 1: 42 case 2: 43 case 3: 44 /* Our lower layer calculations limit our precision to 45 1 microsecond */ 46 return 1; 47 case 4: 48 return 2; 49 case 5: 50 return 4; 51 case 6: 52 return 8; 53 case 7: 54 return 16; 55 default: 56 return 0; 57 } 58 } 59 60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) 61 { 62 bool pending = false; 63 64 spin_lock_bh(&txq->axq_lock); 65 66 if (txq->axq_depth || !list_empty(&txq->axq_acq)) 67 pending = true; 68 69 spin_unlock_bh(&txq->axq_lock); 70 return pending; 71 } 72 73 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 74 { 75 unsigned long flags; 76 bool ret; 77 78 spin_lock_irqsave(&sc->sc_pm_lock, flags); 79 ret = ath9k_hw_setpower(sc->sc_ah, mode); 80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 81 82 return ret; 83 } 84 85 void ath9k_ps_wakeup(struct ath_softc *sc) 86 { 87 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 88 unsigned long flags; 89 enum ath9k_power_mode power_mode; 90 91 spin_lock_irqsave(&sc->sc_pm_lock, flags); 92 if (++sc->ps_usecount != 1) 93 goto unlock; 94 95 power_mode = sc->sc_ah->power_mode; 96 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 97 98 /* 99 * While the hardware is asleep, the cycle counters contain no 100 * useful data. Better clear them now so that they don't mess up 101 * survey data results. 102 */ 103 if (power_mode != ATH9K_PM_AWAKE) { 104 spin_lock(&common->cc_lock); 105 ath_hw_cycle_counters_update(common); 106 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 107 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 108 spin_unlock(&common->cc_lock); 109 } 110 111 unlock: 112 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 113 } 114 115 void ath9k_ps_restore(struct ath_softc *sc) 116 { 117 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 118 enum ath9k_power_mode mode; 119 unsigned long flags; 120 bool reset; 121 122 spin_lock_irqsave(&sc->sc_pm_lock, flags); 123 if (--sc->ps_usecount != 0) 124 goto unlock; 125 126 if (sc->ps_idle) { 127 ath9k_hw_setrxabort(sc->sc_ah, 1); 128 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 129 mode = ATH9K_PM_FULL_SLEEP; 130 } else if (sc->ps_enabled && 131 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 132 PS_WAIT_FOR_CAB | 133 PS_WAIT_FOR_PSPOLL_DATA | 134 PS_WAIT_FOR_TX_ACK | 135 PS_WAIT_FOR_ANI))) { 136 mode = ATH9K_PM_NETWORK_SLEEP; 137 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) 138 ath9k_btcoex_stop_gen_timer(sc); 139 } else { 140 goto unlock; 141 } 142 143 spin_lock(&common->cc_lock); 144 ath_hw_cycle_counters_update(common); 145 spin_unlock(&common->cc_lock); 146 147 ath9k_hw_setpower(sc->sc_ah, mode); 148 149 unlock: 150 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 151 } 152 153 static void __ath_cancel_work(struct ath_softc *sc) 154 { 155 cancel_work_sync(&sc->paprd_work); 156 cancel_work_sync(&sc->hw_check_work); 157 cancel_delayed_work_sync(&sc->tx_complete_work); 158 cancel_delayed_work_sync(&sc->hw_pll_work); 159 160 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 161 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 162 cancel_work_sync(&sc->mci_work); 163 #endif 164 } 165 166 static void ath_cancel_work(struct ath_softc *sc) 167 { 168 __ath_cancel_work(sc); 169 cancel_work_sync(&sc->hw_reset_work); 170 } 171 172 static void ath_restart_work(struct ath_softc *sc) 173 { 174 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 175 176 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) || 177 AR_SREV_9550(sc->sc_ah)) 178 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, 179 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 180 181 ath_start_rx_poll(sc, 3); 182 ath_start_ani(sc); 183 } 184 185 static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush) 186 { 187 struct ath_hw *ah = sc->sc_ah; 188 bool ret = true; 189 190 ieee80211_stop_queues(sc->hw); 191 192 sc->hw_busy_count = 0; 193 ath_stop_ani(sc); 194 del_timer_sync(&sc->rx_poll_timer); 195 196 ath9k_debug_samp_bb_mac(sc); 197 ath9k_hw_disable_interrupts(ah); 198 199 tasklet_disable(&sc->intr_tq); 200 201 if (!ath_stoprecv(sc)) 202 ret = false; 203 204 if (!ath_drain_all_txq(sc, retry_tx)) 205 ret = false; 206 207 if (!flush) { 208 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 209 ath_rx_tasklet(sc, 1, true); 210 ath_rx_tasklet(sc, 1, false); 211 } else { 212 ath_flushrecv(sc); 213 } 214 215 tasklet_enable(&sc->intr_tq); 216 217 return ret; 218 } 219 220 static bool ath_complete_reset(struct ath_softc *sc, bool start) 221 { 222 struct ath_hw *ah = sc->sc_ah; 223 struct ath_common *common = ath9k_hw_common(ah); 224 unsigned long flags; 225 226 if (ath_startrecv(sc) != 0) { 227 ath_err(common, "Unable to restart recv logic\n"); 228 return false; 229 } 230 231 ath9k_cmn_update_txpow(ah, sc->curtxpow, 232 sc->config.txpowlimit, &sc->curtxpow); 233 234 clear_bit(SC_OP_HW_RESET, &sc->sc_flags); 235 ath9k_hw_set_interrupts(ah); 236 ath9k_hw_enable_interrupts(ah); 237 238 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) { 239 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags)) 240 goto work; 241 242 ath9k_set_beacon(sc); 243 244 if (ah->opmode == NL80211_IFTYPE_STATION && 245 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 246 spin_lock_irqsave(&sc->sc_pm_lock, flags); 247 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 248 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 249 } 250 work: 251 ath_restart_work(sc); 252 } 253 254 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) 255 ath_ant_comb_update(sc); 256 257 ieee80211_wake_queues(sc->hw); 258 259 return true; 260 } 261 262 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan, 263 bool retry_tx) 264 { 265 struct ath_hw *ah = sc->sc_ah; 266 struct ath_common *common = ath9k_hw_common(ah); 267 struct ath9k_hw_cal_data *caldata = NULL; 268 bool fastcc = true; 269 bool flush = false; 270 int r; 271 272 __ath_cancel_work(sc); 273 274 spin_lock_bh(&sc->sc_pcu_lock); 275 276 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { 277 fastcc = false; 278 caldata = &sc->caldata; 279 } 280 281 if (!hchan) { 282 fastcc = false; 283 flush = true; 284 hchan = ah->curchan; 285 } 286 287 if (!ath_prepare_reset(sc, retry_tx, flush)) 288 fastcc = false; 289 290 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 291 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 292 293 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 294 if (r) { 295 ath_err(common, 296 "Unable to reset channel, reset status %d\n", r); 297 goto out; 298 } 299 300 if (ath9k_hw_mci_is_enabled(sc->sc_ah) && 301 (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 302 ath9k_mci_set_txpower(sc, true, false); 303 304 if (!ath_complete_reset(sc, true)) 305 r = -EIO; 306 307 out: 308 spin_unlock_bh(&sc->sc_pcu_lock); 309 return r; 310 } 311 312 313 /* 314 * Set/change channels. If the channel is really being changed, it's done 315 * by reseting the chip. To accomplish this we must first cleanup any pending 316 * DMA, then restart stuff. 317 */ 318 static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 319 struct ath9k_channel *hchan) 320 { 321 int r; 322 323 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) 324 return -EIO; 325 326 r = ath_reset_internal(sc, hchan, false); 327 328 return r; 329 } 330 331 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 332 struct ieee80211_vif *vif) 333 { 334 struct ath_node *an; 335 u8 density; 336 an = (struct ath_node *)sta->drv_priv; 337 338 an->sc = sc; 339 an->sta = sta; 340 an->vif = vif; 341 342 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 343 ath_tx_node_init(sc, an); 344 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 345 sta->ht_cap.ampdu_factor); 346 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); 347 an->mpdudensity = density; 348 } 349 } 350 351 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 352 { 353 struct ath_node *an = (struct ath_node *)sta->drv_priv; 354 355 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) 356 ath_tx_node_cleanup(sc, an); 357 } 358 359 void ath9k_tasklet(unsigned long data) 360 { 361 struct ath_softc *sc = (struct ath_softc *)data; 362 struct ath_hw *ah = sc->sc_ah; 363 struct ath_common *common = ath9k_hw_common(ah); 364 enum ath_reset_type type; 365 unsigned long flags; 366 u32 status = sc->intrstatus; 367 u32 rxmask; 368 369 ath9k_ps_wakeup(sc); 370 spin_lock(&sc->sc_pcu_lock); 371 372 if ((status & ATH9K_INT_FATAL) || 373 (status & ATH9K_INT_BB_WATCHDOG)) { 374 375 if (status & ATH9K_INT_FATAL) 376 type = RESET_TYPE_FATAL_INT; 377 else 378 type = RESET_TYPE_BB_WATCHDOG; 379 380 ath9k_queue_reset(sc, type); 381 goto out; 382 } 383 384 spin_lock_irqsave(&sc->sc_pm_lock, flags); 385 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 386 /* 387 * TSF sync does not look correct; remain awake to sync with 388 * the next Beacon. 389 */ 390 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 391 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 392 } 393 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 394 395 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 396 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 397 ATH9K_INT_RXORN); 398 else 399 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 400 401 if (status & rxmask) { 402 /* Check for high priority Rx first */ 403 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 404 (status & ATH9K_INT_RXHP)) 405 ath_rx_tasklet(sc, 0, true); 406 407 ath_rx_tasklet(sc, 0, false); 408 } 409 410 if (status & ATH9K_INT_TX) { 411 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 412 ath_tx_edma_tasklet(sc); 413 else 414 ath_tx_tasklet(sc); 415 } 416 417 ath9k_btcoex_handle_interrupt(sc, status); 418 419 out: 420 /* re-enable hardware interrupt */ 421 ath9k_hw_enable_interrupts(ah); 422 423 spin_unlock(&sc->sc_pcu_lock); 424 ath9k_ps_restore(sc); 425 } 426 427 irqreturn_t ath_isr(int irq, void *dev) 428 { 429 #define SCHED_INTR ( \ 430 ATH9K_INT_FATAL | \ 431 ATH9K_INT_BB_WATCHDOG | \ 432 ATH9K_INT_RXORN | \ 433 ATH9K_INT_RXEOL | \ 434 ATH9K_INT_RX | \ 435 ATH9K_INT_RXLP | \ 436 ATH9K_INT_RXHP | \ 437 ATH9K_INT_TX | \ 438 ATH9K_INT_BMISS | \ 439 ATH9K_INT_CST | \ 440 ATH9K_INT_TSFOOR | \ 441 ATH9K_INT_GENTIMER | \ 442 ATH9K_INT_MCI) 443 444 struct ath_softc *sc = dev; 445 struct ath_hw *ah = sc->sc_ah; 446 struct ath_common *common = ath9k_hw_common(ah); 447 enum ath9k_int status; 448 bool sched = false; 449 450 /* 451 * The hardware is not ready/present, don't 452 * touch anything. Note this can happen early 453 * on if the IRQ is shared. 454 */ 455 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) 456 return IRQ_NONE; 457 458 /* shared irq, not for us */ 459 460 if (!ath9k_hw_intrpend(ah)) 461 return IRQ_NONE; 462 463 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) { 464 ath9k_hw_kill_interrupts(ah); 465 return IRQ_HANDLED; 466 } 467 468 /* 469 * Figure out the reason(s) for the interrupt. Note 470 * that the hal returns a pseudo-ISR that may include 471 * bits we haven't explicitly enabled so we mask the 472 * value to insure we only process bits we requested. 473 */ 474 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ 475 status &= ah->imask; /* discard unasked-for bits */ 476 477 /* 478 * If there are no status bits set, then this interrupt was not 479 * for me (should have been caught above). 480 */ 481 if (!status) 482 return IRQ_NONE; 483 484 /* Cache the status */ 485 sc->intrstatus = status; 486 487 if (status & SCHED_INTR) 488 sched = true; 489 490 /* 491 * If a FATAL or RXORN interrupt is received, we have to reset the 492 * chip immediately. 493 */ 494 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && 495 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) 496 goto chip_reset; 497 498 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 499 (status & ATH9K_INT_BB_WATCHDOG)) { 500 501 spin_lock(&common->cc_lock); 502 ath_hw_cycle_counters_update(common); 503 ar9003_hw_bb_watchdog_dbg_info(ah); 504 spin_unlock(&common->cc_lock); 505 506 goto chip_reset; 507 } 508 #ifdef CONFIG_PM_SLEEP 509 if (status & ATH9K_INT_BMISS) { 510 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { 511 ath_dbg(common, ANY, "during WoW we got a BMISS\n"); 512 atomic_inc(&sc->wow_got_bmiss_intr); 513 atomic_dec(&sc->wow_sleep_proc_intr); 514 } 515 } 516 #endif 517 if (status & ATH9K_INT_SWBA) 518 tasklet_schedule(&sc->bcon_tasklet); 519 520 if (status & ATH9K_INT_TXURN) 521 ath9k_hw_updatetxtriglevel(ah, true); 522 523 if (status & ATH9K_INT_RXEOL) { 524 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 525 ath9k_hw_set_interrupts(ah); 526 } 527 528 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 529 if (status & ATH9K_INT_TIM_TIMER) { 530 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 531 goto chip_reset; 532 /* Clear RxAbort bit so that we can 533 * receive frames */ 534 ath9k_setpower(sc, ATH9K_PM_AWAKE); 535 spin_lock(&sc->sc_pm_lock); 536 ath9k_hw_setrxabort(sc->sc_ah, 0); 537 sc->ps_flags |= PS_WAIT_FOR_BEACON; 538 spin_unlock(&sc->sc_pm_lock); 539 } 540 541 chip_reset: 542 543 ath_debug_stat_interrupt(sc, status); 544 545 if (sched) { 546 /* turn off every interrupt */ 547 ath9k_hw_disable_interrupts(ah); 548 tasklet_schedule(&sc->intr_tq); 549 } 550 551 return IRQ_HANDLED; 552 553 #undef SCHED_INTR 554 } 555 556 static int ath_reset(struct ath_softc *sc, bool retry_tx) 557 { 558 int r; 559 560 ath9k_ps_wakeup(sc); 561 562 r = ath_reset_internal(sc, NULL, retry_tx); 563 564 if (retry_tx) { 565 int i; 566 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 567 if (ATH_TXQ_SETUP(sc, i)) { 568 spin_lock_bh(&sc->tx.txq[i].axq_lock); 569 ath_txq_schedule(sc, &sc->tx.txq[i]); 570 spin_unlock_bh(&sc->tx.txq[i].axq_lock); 571 } 572 } 573 } 574 575 ath9k_ps_restore(sc); 576 577 return r; 578 } 579 580 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) 581 { 582 #ifdef CONFIG_ATH9K_DEBUGFS 583 RESET_STAT_INC(sc, type); 584 #endif 585 set_bit(SC_OP_HW_RESET, &sc->sc_flags); 586 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 587 } 588 589 void ath_reset_work(struct work_struct *work) 590 { 591 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 592 593 ath_reset(sc, true); 594 } 595 596 /**********************/ 597 /* mac80211 callbacks */ 598 /**********************/ 599 600 static int ath9k_start(struct ieee80211_hw *hw) 601 { 602 struct ath_softc *sc = hw->priv; 603 struct ath_hw *ah = sc->sc_ah; 604 struct ath_common *common = ath9k_hw_common(ah); 605 struct ieee80211_channel *curchan = hw->conf.channel; 606 struct ath9k_channel *init_channel; 607 int r; 608 609 ath_dbg(common, CONFIG, 610 "Starting driver with initial channel: %d MHz\n", 611 curchan->center_freq); 612 613 ath9k_ps_wakeup(sc); 614 mutex_lock(&sc->mutex); 615 616 init_channel = ath9k_cmn_get_curchannel(hw, ah); 617 618 /* Reset SERDES registers */ 619 ath9k_hw_configpcipowersave(ah, false); 620 621 /* 622 * The basic interface to setting the hardware in a good 623 * state is ``reset''. On return the hardware is known to 624 * be powered up and with interrupts disabled. This must 625 * be followed by initialization of the appropriate bits 626 * and then setup of the interrupt mask. 627 */ 628 spin_lock_bh(&sc->sc_pcu_lock); 629 630 atomic_set(&ah->intr_ref_cnt, -1); 631 632 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 633 if (r) { 634 ath_err(common, 635 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 636 r, curchan->center_freq); 637 ah->reset_power_on = false; 638 } 639 640 /* Setup our intr mask. */ 641 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 642 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 643 ATH9K_INT_GLOBAL; 644 645 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 646 ah->imask |= ATH9K_INT_RXHP | 647 ATH9K_INT_RXLP | 648 ATH9K_INT_BB_WATCHDOG; 649 else 650 ah->imask |= ATH9K_INT_RX; 651 652 ah->imask |= ATH9K_INT_GTT; 653 654 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 655 ah->imask |= ATH9K_INT_CST; 656 657 ath_mci_enable(sc); 658 659 clear_bit(SC_OP_INVALID, &sc->sc_flags); 660 sc->sc_ah->is_monitoring = false; 661 662 if (!ath_complete_reset(sc, false)) 663 ah->reset_power_on = false; 664 665 if (ah->led_pin >= 0) { 666 ath9k_hw_cfg_output(ah, ah->led_pin, 667 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 668 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 669 } 670 671 /* 672 * Reset key cache to sane defaults (all entries cleared) instead of 673 * semi-random values after suspend/resume. 674 */ 675 ath9k_cmn_init_crypto(sc->sc_ah); 676 677 spin_unlock_bh(&sc->sc_pcu_lock); 678 679 mutex_unlock(&sc->mutex); 680 681 ath9k_ps_restore(sc); 682 683 return 0; 684 } 685 686 static void ath9k_tx(struct ieee80211_hw *hw, 687 struct ieee80211_tx_control *control, 688 struct sk_buff *skb) 689 { 690 struct ath_softc *sc = hw->priv; 691 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 692 struct ath_tx_control txctl; 693 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 694 unsigned long flags; 695 696 if (sc->ps_enabled) { 697 /* 698 * mac80211 does not set PM field for normal data frames, so we 699 * need to update that based on the current PS mode. 700 */ 701 if (ieee80211_is_data(hdr->frame_control) && 702 !ieee80211_is_nullfunc(hdr->frame_control) && 703 !ieee80211_has_pm(hdr->frame_control)) { 704 ath_dbg(common, PS, 705 "Add PM=1 for a TX frame while in PS mode\n"); 706 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 707 } 708 } 709 710 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 711 /* 712 * We are using PS-Poll and mac80211 can request TX while in 713 * power save mode. Need to wake up hardware for the TX to be 714 * completed and if needed, also for RX of buffered frames. 715 */ 716 ath9k_ps_wakeup(sc); 717 spin_lock_irqsave(&sc->sc_pm_lock, flags); 718 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 719 ath9k_hw_setrxabort(sc->sc_ah, 0); 720 if (ieee80211_is_pspoll(hdr->frame_control)) { 721 ath_dbg(common, PS, 722 "Sending PS-Poll to pick a buffered frame\n"); 723 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 724 } else { 725 ath_dbg(common, PS, "Wake up to complete TX\n"); 726 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 727 } 728 /* 729 * The actual restore operation will happen only after 730 * the ps_flags bit is cleared. We are just dropping 731 * the ps_usecount here. 732 */ 733 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 734 ath9k_ps_restore(sc); 735 } 736 737 /* 738 * Cannot tx while the hardware is in full sleep, it first needs a full 739 * chip reset to recover from that 740 */ 741 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 742 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 743 goto exit; 744 } 745 746 memset(&txctl, 0, sizeof(struct ath_tx_control)); 747 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 748 txctl.sta = control->sta; 749 750 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 751 752 if (ath_tx_start(hw, skb, &txctl) != 0) { 753 ath_dbg(common, XMIT, "TX failed\n"); 754 TX_STAT_INC(txctl.txq->axq_qnum, txfailed); 755 goto exit; 756 } 757 758 return; 759 exit: 760 ieee80211_free_txskb(hw, skb); 761 } 762 763 static void ath9k_stop(struct ieee80211_hw *hw) 764 { 765 struct ath_softc *sc = hw->priv; 766 struct ath_hw *ah = sc->sc_ah; 767 struct ath_common *common = ath9k_hw_common(ah); 768 bool prev_idle; 769 770 mutex_lock(&sc->mutex); 771 772 ath_cancel_work(sc); 773 del_timer_sync(&sc->rx_poll_timer); 774 775 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 776 ath_dbg(common, ANY, "Device not present\n"); 777 mutex_unlock(&sc->mutex); 778 return; 779 } 780 781 /* Ensure HW is awake when we try to shut it down. */ 782 ath9k_ps_wakeup(sc); 783 784 spin_lock_bh(&sc->sc_pcu_lock); 785 786 /* prevent tasklets to enable interrupts once we disable them */ 787 ah->imask &= ~ATH9K_INT_GLOBAL; 788 789 /* make sure h/w will not generate any interrupt 790 * before setting the invalid flag. */ 791 ath9k_hw_disable_interrupts(ah); 792 793 spin_unlock_bh(&sc->sc_pcu_lock); 794 795 /* we can now sync irq and kill any running tasklets, since we already 796 * disabled interrupts and not holding a spin lock */ 797 synchronize_irq(sc->irq); 798 tasklet_kill(&sc->intr_tq); 799 tasklet_kill(&sc->bcon_tasklet); 800 801 prev_idle = sc->ps_idle; 802 sc->ps_idle = true; 803 804 spin_lock_bh(&sc->sc_pcu_lock); 805 806 if (ah->led_pin >= 0) { 807 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 808 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 809 } 810 811 ath_prepare_reset(sc, false, true); 812 813 if (sc->rx.frag) { 814 dev_kfree_skb_any(sc->rx.frag); 815 sc->rx.frag = NULL; 816 } 817 818 if (!ah->curchan) 819 ah->curchan = ath9k_cmn_get_curchannel(hw, ah); 820 821 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 822 ath9k_hw_phy_disable(ah); 823 824 ath9k_hw_configpcipowersave(ah, true); 825 826 spin_unlock_bh(&sc->sc_pcu_lock); 827 828 ath9k_ps_restore(sc); 829 830 set_bit(SC_OP_INVALID, &sc->sc_flags); 831 sc->ps_idle = prev_idle; 832 833 mutex_unlock(&sc->mutex); 834 835 ath_dbg(common, CONFIG, "Driver halt\n"); 836 } 837 838 bool ath9k_uses_beacons(int type) 839 { 840 switch (type) { 841 case NL80211_IFTYPE_AP: 842 case NL80211_IFTYPE_ADHOC: 843 case NL80211_IFTYPE_MESH_POINT: 844 return true; 845 default: 846 return false; 847 } 848 } 849 850 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 851 { 852 struct ath9k_vif_iter_data *iter_data = data; 853 int i; 854 855 if (iter_data->hw_macaddr) 856 for (i = 0; i < ETH_ALEN; i++) 857 iter_data->mask[i] &= 858 ~(iter_data->hw_macaddr[i] ^ mac[i]); 859 860 switch (vif->type) { 861 case NL80211_IFTYPE_AP: 862 iter_data->naps++; 863 break; 864 case NL80211_IFTYPE_STATION: 865 iter_data->nstations++; 866 break; 867 case NL80211_IFTYPE_ADHOC: 868 iter_data->nadhocs++; 869 break; 870 case NL80211_IFTYPE_MESH_POINT: 871 iter_data->nmeshes++; 872 break; 873 case NL80211_IFTYPE_WDS: 874 iter_data->nwds++; 875 break; 876 default: 877 break; 878 } 879 } 880 881 static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 882 { 883 struct ath_softc *sc = data; 884 struct ath_vif *avp = (void *)vif->drv_priv; 885 886 if (vif->type != NL80211_IFTYPE_STATION) 887 return; 888 889 if (avp->primary_sta_vif) 890 ath9k_set_assoc_state(sc, vif); 891 } 892 893 /* Called with sc->mutex held. */ 894 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 895 struct ieee80211_vif *vif, 896 struct ath9k_vif_iter_data *iter_data) 897 { 898 struct ath_softc *sc = hw->priv; 899 struct ath_hw *ah = sc->sc_ah; 900 struct ath_common *common = ath9k_hw_common(ah); 901 902 /* 903 * Use the hardware MAC address as reference, the hardware uses it 904 * together with the BSSID mask when matching addresses. 905 */ 906 memset(iter_data, 0, sizeof(*iter_data)); 907 iter_data->hw_macaddr = common->macaddr; 908 memset(&iter_data->mask, 0xff, ETH_ALEN); 909 910 if (vif) 911 ath9k_vif_iter(iter_data, vif->addr, vif); 912 913 /* Get list of all active MAC addresses */ 914 ieee80211_iterate_active_interfaces_atomic( 915 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 916 ath9k_vif_iter, iter_data); 917 } 918 919 /* Called with sc->mutex held. */ 920 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, 921 struct ieee80211_vif *vif) 922 { 923 struct ath_softc *sc = hw->priv; 924 struct ath_hw *ah = sc->sc_ah; 925 struct ath_common *common = ath9k_hw_common(ah); 926 struct ath9k_vif_iter_data iter_data; 927 enum nl80211_iftype old_opmode = ah->opmode; 928 929 ath9k_calculate_iter_data(hw, vif, &iter_data); 930 931 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 932 ath_hw_setbssidmask(common); 933 934 if (iter_data.naps > 0) { 935 ath9k_hw_set_tsfadjust(ah, true); 936 ah->opmode = NL80211_IFTYPE_AP; 937 } else { 938 ath9k_hw_set_tsfadjust(ah, false); 939 940 if (iter_data.nmeshes) 941 ah->opmode = NL80211_IFTYPE_MESH_POINT; 942 else if (iter_data.nwds) 943 ah->opmode = NL80211_IFTYPE_AP; 944 else if (iter_data.nadhocs) 945 ah->opmode = NL80211_IFTYPE_ADHOC; 946 else 947 ah->opmode = NL80211_IFTYPE_STATION; 948 } 949 950 ath9k_hw_setopmode(ah); 951 952 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 953 ah->imask |= ATH9K_INT_TSFOOR; 954 else 955 ah->imask &= ~ATH9K_INT_TSFOOR; 956 957 ath9k_hw_set_interrupts(ah); 958 959 /* 960 * If we are changing the opmode to STATION, 961 * a beacon sync needs to be done. 962 */ 963 if (ah->opmode == NL80211_IFTYPE_STATION && 964 old_opmode == NL80211_IFTYPE_AP && 965 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 966 ieee80211_iterate_active_interfaces_atomic( 967 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 968 ath9k_sta_vif_iter, sc); 969 } 970 } 971 972 static int ath9k_add_interface(struct ieee80211_hw *hw, 973 struct ieee80211_vif *vif) 974 { 975 struct ath_softc *sc = hw->priv; 976 struct ath_hw *ah = sc->sc_ah; 977 struct ath_common *common = ath9k_hw_common(ah); 978 979 mutex_lock(&sc->mutex); 980 981 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 982 sc->nvifs++; 983 984 ath9k_ps_wakeup(sc); 985 ath9k_calculate_summary_state(hw, vif); 986 ath9k_ps_restore(sc); 987 988 if (ath9k_uses_beacons(vif->type)) 989 ath9k_beacon_assign_slot(sc, vif); 990 991 mutex_unlock(&sc->mutex); 992 return 0; 993 } 994 995 static int ath9k_change_interface(struct ieee80211_hw *hw, 996 struct ieee80211_vif *vif, 997 enum nl80211_iftype new_type, 998 bool p2p) 999 { 1000 struct ath_softc *sc = hw->priv; 1001 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1002 1003 ath_dbg(common, CONFIG, "Change Interface\n"); 1004 mutex_lock(&sc->mutex); 1005 1006 if (ath9k_uses_beacons(vif->type)) 1007 ath9k_beacon_remove_slot(sc, vif); 1008 1009 vif->type = new_type; 1010 vif->p2p = p2p; 1011 1012 ath9k_ps_wakeup(sc); 1013 ath9k_calculate_summary_state(hw, vif); 1014 ath9k_ps_restore(sc); 1015 1016 if (ath9k_uses_beacons(vif->type)) 1017 ath9k_beacon_assign_slot(sc, vif); 1018 1019 mutex_unlock(&sc->mutex); 1020 return 0; 1021 } 1022 1023 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1024 struct ieee80211_vif *vif) 1025 { 1026 struct ath_softc *sc = hw->priv; 1027 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1028 1029 ath_dbg(common, CONFIG, "Detach Interface\n"); 1030 1031 mutex_lock(&sc->mutex); 1032 1033 sc->nvifs--; 1034 1035 if (ath9k_uses_beacons(vif->type)) 1036 ath9k_beacon_remove_slot(sc, vif); 1037 1038 ath9k_ps_wakeup(sc); 1039 ath9k_calculate_summary_state(hw, NULL); 1040 ath9k_ps_restore(sc); 1041 1042 mutex_unlock(&sc->mutex); 1043 } 1044 1045 static void ath9k_enable_ps(struct ath_softc *sc) 1046 { 1047 struct ath_hw *ah = sc->sc_ah; 1048 struct ath_common *common = ath9k_hw_common(ah); 1049 1050 sc->ps_enabled = true; 1051 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1052 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1053 ah->imask |= ATH9K_INT_TIM_TIMER; 1054 ath9k_hw_set_interrupts(ah); 1055 } 1056 ath9k_hw_setrxabort(ah, 1); 1057 } 1058 ath_dbg(common, PS, "PowerSave enabled\n"); 1059 } 1060 1061 static void ath9k_disable_ps(struct ath_softc *sc) 1062 { 1063 struct ath_hw *ah = sc->sc_ah; 1064 struct ath_common *common = ath9k_hw_common(ah); 1065 1066 sc->ps_enabled = false; 1067 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1068 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1069 ath9k_hw_setrxabort(ah, 0); 1070 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1071 PS_WAIT_FOR_CAB | 1072 PS_WAIT_FOR_PSPOLL_DATA | 1073 PS_WAIT_FOR_TX_ACK); 1074 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1075 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1076 ath9k_hw_set_interrupts(ah); 1077 } 1078 } 1079 ath_dbg(common, PS, "PowerSave disabled\n"); 1080 } 1081 1082 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1083 { 1084 struct ath_softc *sc = hw->priv; 1085 struct ath_hw *ah = sc->sc_ah; 1086 struct ath_common *common = ath9k_hw_common(ah); 1087 struct ieee80211_conf *conf = &hw->conf; 1088 bool reset_channel = false; 1089 1090 ath9k_ps_wakeup(sc); 1091 mutex_lock(&sc->mutex); 1092 1093 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1094 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1095 if (sc->ps_idle) { 1096 ath_cancel_work(sc); 1097 ath9k_stop_btcoex(sc); 1098 } else { 1099 ath9k_start_btcoex(sc); 1100 /* 1101 * The chip needs a reset to properly wake up from 1102 * full sleep 1103 */ 1104 reset_channel = ah->chip_fullsleep; 1105 } 1106 } 1107 1108 /* 1109 * We just prepare to enable PS. We have to wait until our AP has 1110 * ACK'd our null data frame to disable RX otherwise we'll ignore 1111 * those ACKs and end up retransmitting the same null data frames. 1112 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1113 */ 1114 if (changed & IEEE80211_CONF_CHANGE_PS) { 1115 unsigned long flags; 1116 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1117 if (conf->flags & IEEE80211_CONF_PS) 1118 ath9k_enable_ps(sc); 1119 else 1120 ath9k_disable_ps(sc); 1121 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1122 } 1123 1124 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1125 if (conf->flags & IEEE80211_CONF_MONITOR) { 1126 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1127 sc->sc_ah->is_monitoring = true; 1128 } else { 1129 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1130 sc->sc_ah->is_monitoring = false; 1131 } 1132 } 1133 1134 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) { 1135 struct ieee80211_channel *curchan = hw->conf.channel; 1136 int pos = curchan->hw_value; 1137 int old_pos = -1; 1138 unsigned long flags; 1139 1140 if (ah->curchan) 1141 old_pos = ah->curchan - &ah->channels[0]; 1142 1143 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n", 1144 curchan->center_freq, conf->channel_type); 1145 1146 /* update survey stats for the old channel before switching */ 1147 spin_lock_irqsave(&common->cc_lock, flags); 1148 ath_update_survey_stats(sc); 1149 spin_unlock_irqrestore(&common->cc_lock, flags); 1150 1151 /* 1152 * Preserve the current channel values, before updating 1153 * the same channel 1154 */ 1155 if (ah->curchan && (old_pos == pos)) 1156 ath9k_hw_getnf(ah, ah->curchan); 1157 1158 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], 1159 curchan, conf->channel_type); 1160 1161 /* 1162 * If the operating channel changes, change the survey in-use flags 1163 * along with it. 1164 * Reset the survey data for the new channel, unless we're switching 1165 * back to the operating channel from an off-channel operation. 1166 */ 1167 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && 1168 sc->cur_survey != &sc->survey[pos]) { 1169 1170 if (sc->cur_survey) 1171 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; 1172 1173 sc->cur_survey = &sc->survey[pos]; 1174 1175 memset(sc->cur_survey, 0, sizeof(struct survey_info)); 1176 sc->cur_survey->filled |= SURVEY_INFO_IN_USE; 1177 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { 1178 memset(&sc->survey[pos], 0, sizeof(struct survey_info)); 1179 } 1180 1181 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { 1182 ath_err(common, "Unable to set channel\n"); 1183 mutex_unlock(&sc->mutex); 1184 ath9k_ps_restore(sc); 1185 return -EINVAL; 1186 } 1187 1188 /* 1189 * The most recent snapshot of channel->noisefloor for the old 1190 * channel is only available after the hardware reset. Copy it to 1191 * the survey stats now. 1192 */ 1193 if (old_pos >= 0) 1194 ath_update_survey_nf(sc, old_pos); 1195 } 1196 1197 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1198 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); 1199 sc->config.txpowlimit = 2 * conf->power_level; 1200 ath9k_cmn_update_txpow(ah, sc->curtxpow, 1201 sc->config.txpowlimit, &sc->curtxpow); 1202 } 1203 1204 mutex_unlock(&sc->mutex); 1205 ath9k_ps_restore(sc); 1206 1207 return 0; 1208 } 1209 1210 #define SUPPORTED_FILTERS \ 1211 (FIF_PROMISC_IN_BSS | \ 1212 FIF_ALLMULTI | \ 1213 FIF_CONTROL | \ 1214 FIF_PSPOLL | \ 1215 FIF_OTHER_BSS | \ 1216 FIF_BCN_PRBRESP_PROMISC | \ 1217 FIF_PROBE_REQ | \ 1218 FIF_FCSFAIL) 1219 1220 /* FIXME: sc->sc_full_reset ? */ 1221 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1222 unsigned int changed_flags, 1223 unsigned int *total_flags, 1224 u64 multicast) 1225 { 1226 struct ath_softc *sc = hw->priv; 1227 u32 rfilt; 1228 1229 changed_flags &= SUPPORTED_FILTERS; 1230 *total_flags &= SUPPORTED_FILTERS; 1231 1232 sc->rx.rxfilter = *total_flags; 1233 ath9k_ps_wakeup(sc); 1234 rfilt = ath_calcrxfilter(sc); 1235 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1236 ath9k_ps_restore(sc); 1237 1238 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1239 rfilt); 1240 } 1241 1242 static int ath9k_sta_add(struct ieee80211_hw *hw, 1243 struct ieee80211_vif *vif, 1244 struct ieee80211_sta *sta) 1245 { 1246 struct ath_softc *sc = hw->priv; 1247 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1248 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1249 struct ieee80211_key_conf ps_key = { }; 1250 1251 ath_node_attach(sc, sta, vif); 1252 1253 if (vif->type != NL80211_IFTYPE_AP && 1254 vif->type != NL80211_IFTYPE_AP_VLAN) 1255 return 0; 1256 1257 an->ps_key = ath_key_config(common, vif, sta, &ps_key); 1258 1259 return 0; 1260 } 1261 1262 static void ath9k_del_ps_key(struct ath_softc *sc, 1263 struct ieee80211_vif *vif, 1264 struct ieee80211_sta *sta) 1265 { 1266 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1267 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1268 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; 1269 1270 if (!an->ps_key) 1271 return; 1272 1273 ath_key_delete(common, &ps_key); 1274 } 1275 1276 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1277 struct ieee80211_vif *vif, 1278 struct ieee80211_sta *sta) 1279 { 1280 struct ath_softc *sc = hw->priv; 1281 1282 ath9k_del_ps_key(sc, vif, sta); 1283 ath_node_detach(sc, sta); 1284 1285 return 0; 1286 } 1287 1288 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1289 struct ieee80211_vif *vif, 1290 enum sta_notify_cmd cmd, 1291 struct ieee80211_sta *sta) 1292 { 1293 struct ath_softc *sc = hw->priv; 1294 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1295 1296 if (!sta->ht_cap.ht_supported) 1297 return; 1298 1299 switch (cmd) { 1300 case STA_NOTIFY_SLEEP: 1301 an->sleeping = true; 1302 ath_tx_aggr_sleep(sta, sc, an); 1303 break; 1304 case STA_NOTIFY_AWAKE: 1305 an->sleeping = false; 1306 ath_tx_aggr_wakeup(sc, an); 1307 break; 1308 } 1309 } 1310 1311 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1312 struct ieee80211_vif *vif, u16 queue, 1313 const struct ieee80211_tx_queue_params *params) 1314 { 1315 struct ath_softc *sc = hw->priv; 1316 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1317 struct ath_txq *txq; 1318 struct ath9k_tx_queue_info qi; 1319 int ret = 0; 1320 1321 if (queue >= IEEE80211_NUM_ACS) 1322 return 0; 1323 1324 txq = sc->tx.txq_map[queue]; 1325 1326 ath9k_ps_wakeup(sc); 1327 mutex_lock(&sc->mutex); 1328 1329 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1330 1331 qi.tqi_aifs = params->aifs; 1332 qi.tqi_cwmin = params->cw_min; 1333 qi.tqi_cwmax = params->cw_max; 1334 qi.tqi_burstTime = params->txop * 32; 1335 1336 ath_dbg(common, CONFIG, 1337 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1338 queue, txq->axq_qnum, params->aifs, params->cw_min, 1339 params->cw_max, params->txop); 1340 1341 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); 1342 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1343 if (ret) 1344 ath_err(common, "TXQ Update failed\n"); 1345 1346 mutex_unlock(&sc->mutex); 1347 ath9k_ps_restore(sc); 1348 1349 return ret; 1350 } 1351 1352 static int ath9k_set_key(struct ieee80211_hw *hw, 1353 enum set_key_cmd cmd, 1354 struct ieee80211_vif *vif, 1355 struct ieee80211_sta *sta, 1356 struct ieee80211_key_conf *key) 1357 { 1358 struct ath_softc *sc = hw->priv; 1359 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1360 int ret = 0; 1361 1362 if (ath9k_modparam_nohwcrypt) 1363 return -ENOSPC; 1364 1365 if ((vif->type == NL80211_IFTYPE_ADHOC || 1366 vif->type == NL80211_IFTYPE_MESH_POINT) && 1367 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1368 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1369 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1370 /* 1371 * For now, disable hw crypto for the RSN IBSS group keys. This 1372 * could be optimized in the future to use a modified key cache 1373 * design to support per-STA RX GTK, but until that gets 1374 * implemented, use of software crypto for group addressed 1375 * frames is a acceptable to allow RSN IBSS to be used. 1376 */ 1377 return -EOPNOTSUPP; 1378 } 1379 1380 mutex_lock(&sc->mutex); 1381 ath9k_ps_wakeup(sc); 1382 ath_dbg(common, CONFIG, "Set HW Key\n"); 1383 1384 switch (cmd) { 1385 case SET_KEY: 1386 if (sta) 1387 ath9k_del_ps_key(sc, vif, sta); 1388 1389 ret = ath_key_config(common, vif, sta, key); 1390 if (ret >= 0) { 1391 key->hw_key_idx = ret; 1392 /* push IV and Michael MIC generation to stack */ 1393 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1394 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1395 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1396 if (sc->sc_ah->sw_mgmt_crypto && 1397 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1398 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 1399 ret = 0; 1400 } 1401 break; 1402 case DISABLE_KEY: 1403 ath_key_delete(common, key); 1404 break; 1405 default: 1406 ret = -EINVAL; 1407 } 1408 1409 ath9k_ps_restore(sc); 1410 mutex_unlock(&sc->mutex); 1411 1412 return ret; 1413 } 1414 1415 static void ath9k_set_assoc_state(struct ath_softc *sc, 1416 struct ieee80211_vif *vif) 1417 { 1418 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1419 struct ath_vif *avp = (void *)vif->drv_priv; 1420 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1421 unsigned long flags; 1422 1423 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); 1424 avp->primary_sta_vif = true; 1425 1426 /* 1427 * Set the AID, BSSID and do beacon-sync only when 1428 * the HW opmode is STATION. 1429 * 1430 * But the primary bit is set above in any case. 1431 */ 1432 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) 1433 return; 1434 1435 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1436 common->curaid = bss_conf->aid; 1437 ath9k_hw_write_associd(sc->sc_ah); 1438 1439 sc->last_rssi = ATH_RSSI_DUMMY_MARKER; 1440 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1441 1442 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1443 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1444 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1445 1446 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1447 ath9k_mci_update_wlan_channels(sc, false); 1448 1449 ath_dbg(common, CONFIG, 1450 "Primary Station interface: %pM, BSSID: %pM\n", 1451 vif->addr, common->curbssid); 1452 } 1453 1454 static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1455 { 1456 struct ath_softc *sc = data; 1457 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1458 1459 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) 1460 return; 1461 1462 if (bss_conf->assoc) 1463 ath9k_set_assoc_state(sc, vif); 1464 } 1465 1466 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1467 struct ieee80211_vif *vif, 1468 struct ieee80211_bss_conf *bss_conf, 1469 u32 changed) 1470 { 1471 #define CHECK_ANI \ 1472 (BSS_CHANGED_ASSOC | \ 1473 BSS_CHANGED_IBSS | \ 1474 BSS_CHANGED_BEACON_ENABLED) 1475 1476 struct ath_softc *sc = hw->priv; 1477 struct ath_hw *ah = sc->sc_ah; 1478 struct ath_common *common = ath9k_hw_common(ah); 1479 struct ath_vif *avp = (void *)vif->drv_priv; 1480 int slottime; 1481 1482 ath9k_ps_wakeup(sc); 1483 mutex_lock(&sc->mutex); 1484 1485 if (changed & BSS_CHANGED_ASSOC) { 1486 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", 1487 bss_conf->bssid, bss_conf->assoc); 1488 1489 if (avp->primary_sta_vif && !bss_conf->assoc) { 1490 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); 1491 avp->primary_sta_vif = false; 1492 1493 if (ah->opmode == NL80211_IFTYPE_STATION) 1494 clear_bit(SC_OP_BEACONS, &sc->sc_flags); 1495 } 1496 1497 ieee80211_iterate_active_interfaces_atomic( 1498 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 1499 ath9k_bss_assoc_iter, sc); 1500 1501 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) && 1502 ah->opmode == NL80211_IFTYPE_STATION) { 1503 memset(common->curbssid, 0, ETH_ALEN); 1504 common->curaid = 0; 1505 ath9k_hw_write_associd(sc->sc_ah); 1506 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1507 ath9k_mci_update_wlan_channels(sc, true); 1508 } 1509 } 1510 1511 if (changed & BSS_CHANGED_IBSS) { 1512 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1513 common->curaid = bss_conf->aid; 1514 ath9k_hw_write_associd(sc->sc_ah); 1515 } 1516 1517 if ((changed & BSS_CHANGED_BEACON_ENABLED) || 1518 (changed & BSS_CHANGED_BEACON_INT)) { 1519 if (ah->opmode == NL80211_IFTYPE_AP && 1520 bss_conf->enable_beacon) 1521 ath9k_set_tsfadjust(sc, vif); 1522 if (ath9k_allow_beacon_config(sc, vif)) 1523 ath9k_beacon_config(sc, vif, changed); 1524 } 1525 1526 if (changed & BSS_CHANGED_ERP_SLOT) { 1527 if (bss_conf->use_short_slot) 1528 slottime = 9; 1529 else 1530 slottime = 20; 1531 if (vif->type == NL80211_IFTYPE_AP) { 1532 /* 1533 * Defer update, so that connected stations can adjust 1534 * their settings at the same time. 1535 * See beacon.c for more details 1536 */ 1537 sc->beacon.slottime = slottime; 1538 sc->beacon.updateslot = UPDATE; 1539 } else { 1540 ah->slottime = slottime; 1541 ath9k_hw_init_global_settings(ah); 1542 } 1543 } 1544 1545 if (changed & CHECK_ANI) 1546 ath_check_ani(sc); 1547 1548 mutex_unlock(&sc->mutex); 1549 ath9k_ps_restore(sc); 1550 1551 #undef CHECK_ANI 1552 } 1553 1554 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1555 { 1556 struct ath_softc *sc = hw->priv; 1557 u64 tsf; 1558 1559 mutex_lock(&sc->mutex); 1560 ath9k_ps_wakeup(sc); 1561 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1562 ath9k_ps_restore(sc); 1563 mutex_unlock(&sc->mutex); 1564 1565 return tsf; 1566 } 1567 1568 static void ath9k_set_tsf(struct ieee80211_hw *hw, 1569 struct ieee80211_vif *vif, 1570 u64 tsf) 1571 { 1572 struct ath_softc *sc = hw->priv; 1573 1574 mutex_lock(&sc->mutex); 1575 ath9k_ps_wakeup(sc); 1576 ath9k_hw_settsf64(sc->sc_ah, tsf); 1577 ath9k_ps_restore(sc); 1578 mutex_unlock(&sc->mutex); 1579 } 1580 1581 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1582 { 1583 struct ath_softc *sc = hw->priv; 1584 1585 mutex_lock(&sc->mutex); 1586 1587 ath9k_ps_wakeup(sc); 1588 ath9k_hw_reset_tsf(sc->sc_ah); 1589 ath9k_ps_restore(sc); 1590 1591 mutex_unlock(&sc->mutex); 1592 } 1593 1594 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1595 struct ieee80211_vif *vif, 1596 enum ieee80211_ampdu_mlme_action action, 1597 struct ieee80211_sta *sta, 1598 u16 tid, u16 *ssn, u8 buf_size) 1599 { 1600 struct ath_softc *sc = hw->priv; 1601 int ret = 0; 1602 1603 local_bh_disable(); 1604 1605 switch (action) { 1606 case IEEE80211_AMPDU_RX_START: 1607 break; 1608 case IEEE80211_AMPDU_RX_STOP: 1609 break; 1610 case IEEE80211_AMPDU_TX_START: 1611 ath9k_ps_wakeup(sc); 1612 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1613 if (!ret) 1614 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1615 ath9k_ps_restore(sc); 1616 break; 1617 case IEEE80211_AMPDU_TX_STOP: 1618 ath9k_ps_wakeup(sc); 1619 ath_tx_aggr_stop(sc, sta, tid); 1620 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1621 ath9k_ps_restore(sc); 1622 break; 1623 case IEEE80211_AMPDU_TX_OPERATIONAL: 1624 ath9k_ps_wakeup(sc); 1625 ath_tx_aggr_resume(sc, sta, tid); 1626 ath9k_ps_restore(sc); 1627 break; 1628 default: 1629 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 1630 } 1631 1632 local_bh_enable(); 1633 1634 return ret; 1635 } 1636 1637 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 1638 struct survey_info *survey) 1639 { 1640 struct ath_softc *sc = hw->priv; 1641 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1642 struct ieee80211_supported_band *sband; 1643 struct ieee80211_channel *chan; 1644 unsigned long flags; 1645 int pos; 1646 1647 spin_lock_irqsave(&common->cc_lock, flags); 1648 if (idx == 0) 1649 ath_update_survey_stats(sc); 1650 1651 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; 1652 if (sband && idx >= sband->n_channels) { 1653 idx -= sband->n_channels; 1654 sband = NULL; 1655 } 1656 1657 if (!sband) 1658 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; 1659 1660 if (!sband || idx >= sband->n_channels) { 1661 spin_unlock_irqrestore(&common->cc_lock, flags); 1662 return -ENOENT; 1663 } 1664 1665 chan = &sband->channels[idx]; 1666 pos = chan->hw_value; 1667 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 1668 survey->channel = chan; 1669 spin_unlock_irqrestore(&common->cc_lock, flags); 1670 1671 return 0; 1672 } 1673 1674 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) 1675 { 1676 struct ath_softc *sc = hw->priv; 1677 struct ath_hw *ah = sc->sc_ah; 1678 1679 mutex_lock(&sc->mutex); 1680 ah->coverage_class = coverage_class; 1681 1682 ath9k_ps_wakeup(sc); 1683 ath9k_hw_init_global_settings(ah); 1684 ath9k_ps_restore(sc); 1685 1686 mutex_unlock(&sc->mutex); 1687 } 1688 1689 static void ath9k_flush(struct ieee80211_hw *hw, bool drop) 1690 { 1691 struct ath_softc *sc = hw->priv; 1692 struct ath_hw *ah = sc->sc_ah; 1693 struct ath_common *common = ath9k_hw_common(ah); 1694 int timeout = 200; /* ms */ 1695 int i, j; 1696 bool drain_txq; 1697 1698 mutex_lock(&sc->mutex); 1699 cancel_delayed_work_sync(&sc->tx_complete_work); 1700 1701 if (ah->ah_flags & AH_UNPLUGGED) { 1702 ath_dbg(common, ANY, "Device has been unplugged!\n"); 1703 mutex_unlock(&sc->mutex); 1704 return; 1705 } 1706 1707 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 1708 ath_dbg(common, ANY, "Device not present\n"); 1709 mutex_unlock(&sc->mutex); 1710 return; 1711 } 1712 1713 for (j = 0; j < timeout; j++) { 1714 bool npend = false; 1715 1716 if (j) 1717 usleep_range(1000, 2000); 1718 1719 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1720 if (!ATH_TXQ_SETUP(sc, i)) 1721 continue; 1722 1723 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); 1724 1725 if (npend) 1726 break; 1727 } 1728 1729 if (!npend) 1730 break; 1731 } 1732 1733 if (drop) { 1734 ath9k_ps_wakeup(sc); 1735 spin_lock_bh(&sc->sc_pcu_lock); 1736 drain_txq = ath_drain_all_txq(sc, false); 1737 spin_unlock_bh(&sc->sc_pcu_lock); 1738 1739 if (!drain_txq) 1740 ath_reset(sc, false); 1741 1742 ath9k_ps_restore(sc); 1743 ieee80211_wake_queues(hw); 1744 } 1745 1746 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); 1747 mutex_unlock(&sc->mutex); 1748 } 1749 1750 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 1751 { 1752 struct ath_softc *sc = hw->priv; 1753 int i; 1754 1755 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1756 if (!ATH_TXQ_SETUP(sc, i)) 1757 continue; 1758 1759 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) 1760 return true; 1761 } 1762 return false; 1763 } 1764 1765 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 1766 { 1767 struct ath_softc *sc = hw->priv; 1768 struct ath_hw *ah = sc->sc_ah; 1769 struct ieee80211_vif *vif; 1770 struct ath_vif *avp; 1771 struct ath_buf *bf; 1772 struct ath_tx_status ts; 1773 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1774 int status; 1775 1776 vif = sc->beacon.bslot[0]; 1777 if (!vif) 1778 return 0; 1779 1780 if (!vif->bss_conf.enable_beacon) 1781 return 0; 1782 1783 avp = (void *)vif->drv_priv; 1784 1785 if (!sc->beacon.tx_processed && !edma) { 1786 tasklet_disable(&sc->bcon_tasklet); 1787 1788 bf = avp->av_bcbuf; 1789 if (!bf || !bf->bf_mpdu) 1790 goto skip; 1791 1792 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 1793 if (status == -EINPROGRESS) 1794 goto skip; 1795 1796 sc->beacon.tx_processed = true; 1797 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 1798 1799 skip: 1800 tasklet_enable(&sc->bcon_tasklet); 1801 } 1802 1803 return sc->beacon.tx_last; 1804 } 1805 1806 static int ath9k_get_stats(struct ieee80211_hw *hw, 1807 struct ieee80211_low_level_stats *stats) 1808 { 1809 struct ath_softc *sc = hw->priv; 1810 struct ath_hw *ah = sc->sc_ah; 1811 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 1812 1813 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 1814 stats->dot11RTSFailureCount = mib_stats->rts_bad; 1815 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 1816 stats->dot11RTSSuccessCount = mib_stats->rts_good; 1817 return 0; 1818 } 1819 1820 static u32 fill_chainmask(u32 cap, u32 new) 1821 { 1822 u32 filled = 0; 1823 int i; 1824 1825 for (i = 0; cap && new; i++, cap >>= 1) { 1826 if (!(cap & BIT(0))) 1827 continue; 1828 1829 if (new & BIT(0)) 1830 filled |= BIT(i); 1831 1832 new >>= 1; 1833 } 1834 1835 return filled; 1836 } 1837 1838 static bool validate_antenna_mask(struct ath_hw *ah, u32 val) 1839 { 1840 switch (val & 0x7) { 1841 case 0x1: 1842 case 0x3: 1843 case 0x7: 1844 return true; 1845 case 0x2: 1846 return (ah->caps.rx_chainmask == 1); 1847 default: 1848 return false; 1849 } 1850 } 1851 1852 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 1853 { 1854 struct ath_softc *sc = hw->priv; 1855 struct ath_hw *ah = sc->sc_ah; 1856 1857 if (ah->caps.rx_chainmask != 1) 1858 rx_ant |= tx_ant; 1859 1860 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) 1861 return -EINVAL; 1862 1863 sc->ant_rx = rx_ant; 1864 sc->ant_tx = tx_ant; 1865 1866 if (ah->caps.rx_chainmask == 1) 1867 return 0; 1868 1869 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 1870 if (AR_SREV_9100(ah)) 1871 ah->rxchainmask = 0x7; 1872 else 1873 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 1874 1875 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 1876 ath9k_reload_chainmask_settings(sc); 1877 1878 return 0; 1879 } 1880 1881 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 1882 { 1883 struct ath_softc *sc = hw->priv; 1884 1885 *tx_ant = sc->ant_tx; 1886 *rx_ant = sc->ant_rx; 1887 return 0; 1888 } 1889 1890 #ifdef CONFIG_PM_SLEEP 1891 1892 static void ath9k_wow_map_triggers(struct ath_softc *sc, 1893 struct cfg80211_wowlan *wowlan, 1894 u32 *wow_triggers) 1895 { 1896 if (wowlan->disconnect) 1897 *wow_triggers |= AH_WOW_LINK_CHANGE | 1898 AH_WOW_BEACON_MISS; 1899 if (wowlan->magic_pkt) 1900 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN; 1901 1902 if (wowlan->n_patterns) 1903 *wow_triggers |= AH_WOW_USER_PATTERN_EN; 1904 1905 sc->wow_enabled = *wow_triggers; 1906 1907 } 1908 1909 static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc) 1910 { 1911 struct ath_hw *ah = sc->sc_ah; 1912 struct ath_common *common = ath9k_hw_common(ah); 1913 struct ath9k_hw_capabilities *pcaps = &ah->caps; 1914 int pattern_count = 0; 1915 int i, byte_cnt; 1916 u8 dis_deauth_pattern[MAX_PATTERN_SIZE]; 1917 u8 dis_deauth_mask[MAX_PATTERN_SIZE]; 1918 1919 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE); 1920 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE); 1921 1922 /* 1923 * Create Dissassociate / Deauthenticate packet filter 1924 * 1925 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes 1926 * +--------------+----------+---------+--------+--------+---- 1927 * + Frame Control+ Duration + DA + SA + BSSID + 1928 * +--------------+----------+---------+--------+--------+---- 1929 * 1930 * The above is the management frame format for disassociate/ 1931 * deauthenticate pattern, from this we need to match the first byte 1932 * of 'Frame Control' and DA, SA, and BSSID fields 1933 * (skipping 2nd byte of FC and Duration feild. 1934 * 1935 * Disassociate pattern 1936 * -------------------- 1937 * Frame control = 00 00 1010 1938 * DA, SA, BSSID = x:x:x:x:x:x 1939 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x 1940 * | x:x:x:x:x:x -- 22 bytes 1941 * 1942 * Deauthenticate pattern 1943 * ---------------------- 1944 * Frame control = 00 00 1100 1945 * DA, SA, BSSID = x:x:x:x:x:x 1946 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x 1947 * | x:x:x:x:x:x -- 22 bytes 1948 */ 1949 1950 /* Create Disassociate Pattern first */ 1951 1952 byte_cnt = 0; 1953 1954 /* Fill out the mask with all FF's */ 1955 1956 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++) 1957 dis_deauth_mask[i] = 0xff; 1958 1959 /* copy the first byte of frame control field */ 1960 dis_deauth_pattern[byte_cnt] = 0xa0; 1961 byte_cnt++; 1962 1963 /* skip 2nd byte of frame control and Duration field */ 1964 byte_cnt += 3; 1965 1966 /* 1967 * need not match the destination mac address, it can be a broadcast 1968 * mac address or an unicast to this station 1969 */ 1970 byte_cnt += 6; 1971 1972 /* copy the source mac address */ 1973 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); 1974 1975 byte_cnt += 6; 1976 1977 /* copy the bssid, its same as the source mac address */ 1978 1979 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); 1980 1981 /* Create Disassociate pattern mask */ 1982 1983 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) { 1984 1985 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) { 1986 /* 1987 * for AR9280, because of hardware limitation, the 1988 * first 4 bytes have to be matched for all patterns. 1989 * the mask for disassociation and de-auth pattern 1990 * matching need to enable the first 4 bytes. 1991 * also the duration field needs to be filled. 1992 */ 1993 dis_deauth_mask[0] = 0xf0; 1994 1995 /* 1996 * fill in duration field 1997 FIXME: what is the exact value ? 1998 */ 1999 dis_deauth_pattern[2] = 0xff; 2000 dis_deauth_pattern[3] = 0xff; 2001 } else { 2002 dis_deauth_mask[0] = 0xfe; 2003 } 2004 2005 dis_deauth_mask[1] = 0x03; 2006 dis_deauth_mask[2] = 0xc0; 2007 } else { 2008 dis_deauth_mask[0] = 0xef; 2009 dis_deauth_mask[1] = 0x3f; 2010 dis_deauth_mask[2] = 0x00; 2011 dis_deauth_mask[3] = 0xfc; 2012 } 2013 2014 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n"); 2015 2016 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, 2017 pattern_count, byte_cnt); 2018 2019 pattern_count++; 2020 /* 2021 * for de-authenticate pattern, only the first byte of the frame 2022 * control field gets changed from 0xA0 to 0xC0 2023 */ 2024 dis_deauth_pattern[0] = 0xC0; 2025 2026 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, 2027 pattern_count, byte_cnt); 2028 2029 } 2030 2031 static void ath9k_wow_add_pattern(struct ath_softc *sc, 2032 struct cfg80211_wowlan *wowlan) 2033 { 2034 struct ath_hw *ah = sc->sc_ah; 2035 struct ath9k_wow_pattern *wow_pattern = NULL; 2036 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns; 2037 int mask_len; 2038 s8 i = 0; 2039 2040 if (!wowlan->n_patterns) 2041 return; 2042 2043 /* 2044 * Add the new user configured patterns 2045 */ 2046 for (i = 0; i < wowlan->n_patterns; i++) { 2047 2048 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL); 2049 2050 if (!wow_pattern) 2051 return; 2052 2053 /* 2054 * TODO: convert the generic user space pattern to 2055 * appropriate chip specific/802.11 pattern. 2056 */ 2057 2058 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8); 2059 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE); 2060 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE); 2061 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern, 2062 patterns[i].pattern_len); 2063 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len); 2064 wow_pattern->pattern_len = patterns[i].pattern_len; 2065 2066 /* 2067 * just need to take care of deauth and disssoc pattern, 2068 * make sure we don't overwrite them. 2069 */ 2070 2071 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes, 2072 wow_pattern->mask_bytes, 2073 i + 2, 2074 wow_pattern->pattern_len); 2075 kfree(wow_pattern); 2076 2077 } 2078 2079 } 2080 2081 static int ath9k_suspend(struct ieee80211_hw *hw, 2082 struct cfg80211_wowlan *wowlan) 2083 { 2084 struct ath_softc *sc = hw->priv; 2085 struct ath_hw *ah = sc->sc_ah; 2086 struct ath_common *common = ath9k_hw_common(ah); 2087 u32 wow_triggers_enabled = 0; 2088 int ret = 0; 2089 2090 mutex_lock(&sc->mutex); 2091 2092 ath_cancel_work(sc); 2093 ath_stop_ani(sc); 2094 del_timer_sync(&sc->rx_poll_timer); 2095 2096 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 2097 ath_dbg(common, ANY, "Device not present\n"); 2098 ret = -EINVAL; 2099 goto fail_wow; 2100 } 2101 2102 if (WARN_ON(!wowlan)) { 2103 ath_dbg(common, WOW, "None of the WoW triggers enabled\n"); 2104 ret = -EINVAL; 2105 goto fail_wow; 2106 } 2107 2108 if (!device_can_wakeup(sc->dev)) { 2109 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n"); 2110 ret = 1; 2111 goto fail_wow; 2112 } 2113 2114 /* 2115 * none of the sta vifs are associated 2116 * and we are not currently handling multivif 2117 * cases, for instance we have to seperately 2118 * configure 'keep alive frame' for each 2119 * STA. 2120 */ 2121 2122 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 2123 ath_dbg(common, WOW, "None of the STA vifs are associated\n"); 2124 ret = 1; 2125 goto fail_wow; 2126 } 2127 2128 if (sc->nvifs > 1) { 2129 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n"); 2130 ret = 1; 2131 goto fail_wow; 2132 } 2133 2134 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled); 2135 2136 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n", 2137 wow_triggers_enabled); 2138 2139 ath9k_ps_wakeup(sc); 2140 2141 ath9k_stop_btcoex(sc); 2142 2143 /* 2144 * Enable wake up on recieving disassoc/deauth 2145 * frame by default. 2146 */ 2147 ath9k_wow_add_disassoc_deauth_pattern(sc); 2148 2149 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN) 2150 ath9k_wow_add_pattern(sc, wowlan); 2151 2152 spin_lock_bh(&sc->sc_pcu_lock); 2153 /* 2154 * To avoid false wake, we enable beacon miss interrupt only 2155 * when we go to sleep. We save the current interrupt mask 2156 * so we can restore it after the system wakes up 2157 */ 2158 sc->wow_intr_before_sleep = ah->imask; 2159 ah->imask &= ~ATH9K_INT_GLOBAL; 2160 ath9k_hw_disable_interrupts(ah); 2161 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL; 2162 ath9k_hw_set_interrupts(ah); 2163 ath9k_hw_enable_interrupts(ah); 2164 2165 spin_unlock_bh(&sc->sc_pcu_lock); 2166 2167 /* 2168 * we can now sync irq and kill any running tasklets, since we already 2169 * disabled interrupts and not holding a spin lock 2170 */ 2171 synchronize_irq(sc->irq); 2172 tasklet_kill(&sc->intr_tq); 2173 2174 ath9k_hw_wow_enable(ah, wow_triggers_enabled); 2175 2176 ath9k_ps_restore(sc); 2177 ath_dbg(common, ANY, "WoW enabled in ath9k\n"); 2178 atomic_inc(&sc->wow_sleep_proc_intr); 2179 2180 fail_wow: 2181 mutex_unlock(&sc->mutex); 2182 return ret; 2183 } 2184 2185 static int ath9k_resume(struct ieee80211_hw *hw) 2186 { 2187 struct ath_softc *sc = hw->priv; 2188 struct ath_hw *ah = sc->sc_ah; 2189 struct ath_common *common = ath9k_hw_common(ah); 2190 u32 wow_status; 2191 2192 mutex_lock(&sc->mutex); 2193 2194 ath9k_ps_wakeup(sc); 2195 2196 spin_lock_bh(&sc->sc_pcu_lock); 2197 2198 ath9k_hw_disable_interrupts(ah); 2199 ah->imask = sc->wow_intr_before_sleep; 2200 ath9k_hw_set_interrupts(ah); 2201 ath9k_hw_enable_interrupts(ah); 2202 2203 spin_unlock_bh(&sc->sc_pcu_lock); 2204 2205 wow_status = ath9k_hw_wow_wakeup(ah); 2206 2207 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) { 2208 /* 2209 * some devices may not pick beacon miss 2210 * as the reason they woke up so we add 2211 * that here for that shortcoming. 2212 */ 2213 wow_status |= AH_WOW_BEACON_MISS; 2214 atomic_dec(&sc->wow_got_bmiss_intr); 2215 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n"); 2216 } 2217 2218 atomic_dec(&sc->wow_sleep_proc_intr); 2219 2220 if (wow_status) { 2221 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n", 2222 ath9k_hw_wow_event_to_string(wow_status), wow_status); 2223 } 2224 2225 ath_restart_work(sc); 2226 ath9k_start_btcoex(sc); 2227 2228 ath9k_ps_restore(sc); 2229 mutex_unlock(&sc->mutex); 2230 2231 return 0; 2232 } 2233 2234 static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) 2235 { 2236 struct ath_softc *sc = hw->priv; 2237 2238 mutex_lock(&sc->mutex); 2239 device_init_wakeup(sc->dev, 1); 2240 device_set_wakeup_enable(sc->dev, enabled); 2241 mutex_unlock(&sc->mutex); 2242 } 2243 2244 #endif 2245 2246 struct ieee80211_ops ath9k_ops = { 2247 .tx = ath9k_tx, 2248 .start = ath9k_start, 2249 .stop = ath9k_stop, 2250 .add_interface = ath9k_add_interface, 2251 .change_interface = ath9k_change_interface, 2252 .remove_interface = ath9k_remove_interface, 2253 .config = ath9k_config, 2254 .configure_filter = ath9k_configure_filter, 2255 .sta_add = ath9k_sta_add, 2256 .sta_remove = ath9k_sta_remove, 2257 .sta_notify = ath9k_sta_notify, 2258 .conf_tx = ath9k_conf_tx, 2259 .bss_info_changed = ath9k_bss_info_changed, 2260 .set_key = ath9k_set_key, 2261 .get_tsf = ath9k_get_tsf, 2262 .set_tsf = ath9k_set_tsf, 2263 .reset_tsf = ath9k_reset_tsf, 2264 .ampdu_action = ath9k_ampdu_action, 2265 .get_survey = ath9k_get_survey, 2266 .rfkill_poll = ath9k_rfkill_poll_state, 2267 .set_coverage_class = ath9k_set_coverage_class, 2268 .flush = ath9k_flush, 2269 .tx_frames_pending = ath9k_tx_frames_pending, 2270 .tx_last_beacon = ath9k_tx_last_beacon, 2271 .get_stats = ath9k_get_stats, 2272 .set_antenna = ath9k_set_antenna, 2273 .get_antenna = ath9k_get_antenna, 2274 2275 #ifdef CONFIG_PM_SLEEP 2276 .suspend = ath9k_suspend, 2277 .resume = ath9k_resume, 2278 .set_wakeup = ath9k_set_wakeup, 2279 #endif 2280 2281 #ifdef CONFIG_ATH9K_DEBUGFS 2282 .get_et_sset_count = ath9k_get_et_sset_count, 2283 .get_et_stats = ath9k_get_et_stats, 2284 .get_et_strings = ath9k_get_et_strings, 2285 #endif 2286 2287 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS) 2288 .sta_add_debugfs = ath9k_sta_add_debugfs, 2289 .sta_remove_debugfs = ath9k_sta_remove_debugfs, 2290 #endif 2291 }; 2292