hw.h (aa7eb8e78d8ecd6cd0475d86ea8385ff9cb47ece) hw.h (d4930086bdd0c08a8b3a4d66a9c702297cb74a99)
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

--- 31 unchanged lines hidden (view full) ---

40#define AR9280_DEVID_PCIE 0x002a
41#define AR9285_DEVID_PCIE 0x002b
42#define AR2427_DEVID_PCIE 0x002c
43#define AR9287_DEVID_PCI 0x002d
44#define AR9287_DEVID_PCIE 0x002e
45#define AR9300_DEVID_PCIE 0x0030
46#define AR9300_DEVID_AR9340 0x0031
47#define AR9300_DEVID_AR9485_PCIE 0x0032
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

--- 31 unchanged lines hidden (view full) ---

40#define AR9280_DEVID_PCIE 0x002a
41#define AR9285_DEVID_PCIE 0x002b
42#define AR2427_DEVID_PCIE 0x002c
43#define AR9287_DEVID_PCI 0x002d
44#define AR9287_DEVID_PCIE 0x002e
45#define AR9300_DEVID_PCIE 0x0030
46#define AR9300_DEVID_AR9340 0x0031
47#define AR9300_DEVID_AR9485_PCIE 0x0032
48#define AR9300_DEVID_AR9330 0x0035
48
49#define AR5416_AR9100_DEVID 0x000b
50
51#define AR_SUBVENDOR_ID_NOG 0x0e11
52#define AR_SUBVENDOR_ID_NEW_A 0x7065
53#define AR5416_MAGIC 0x19641014
54
55#define AR9280_COEX2WIRE_SUBSYSID 0x309b

--- 81 unchanged lines hidden (view full) ---

137
138#define MAX_RATE_POWER 63
139#define AH_WAIT_TIMEOUT 100000 /* (us) */
140#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
141#define AH_TIME_QUANTUM 10
142#define AR_KEYTABLE_SIZE 128
143#define POWER_UP_TIME 10000
144#define SPUR_RSSI_THRESH 40
49
50#define AR5416_AR9100_DEVID 0x000b
51
52#define AR_SUBVENDOR_ID_NOG 0x0e11
53#define AR_SUBVENDOR_ID_NEW_A 0x7065
54#define AR5416_MAGIC 0x19641014
55
56#define AR9280_COEX2WIRE_SUBSYSID 0x309b

--- 81 unchanged lines hidden (view full) ---

138
139#define MAX_RATE_POWER 63
140#define AH_WAIT_TIMEOUT 100000 /* (us) */
141#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
142#define AH_TIME_QUANTUM 10
143#define AR_KEYTABLE_SIZE 128
144#define POWER_UP_TIME 10000
145#define SPUR_RSSI_THRESH 40
146#define UPPER_5G_SUB_BAND_START 5700
147#define MID_5G_SUB_BAND_START 5400
145
146#define CAB_TIMEOUT_VAL 10
147#define BEACON_TIMEOUT_VAL 10
148#define MIN_BEACON_TIMEOUT_VAL 1
149#define SLEEP_SLOP 3
150
151#define INIT_CONFIG_STATUS 0x00000000
152#define INIT_RSSI_THR 0x00000700
153#define INIT_BCON_CNTRL_REG 0x00000000
154
155#define TU_TO_USEC(_tu) ((_tu) << 10)
156
157#define ATH9K_HW_RX_HP_QDEPTH 16
158#define ATH9K_HW_RX_LP_QDEPTH 128
159
148
149#define CAB_TIMEOUT_VAL 10
150#define BEACON_TIMEOUT_VAL 10
151#define MIN_BEACON_TIMEOUT_VAL 1
152#define SLEEP_SLOP 3
153
154#define INIT_CONFIG_STATUS 0x00000000
155#define INIT_RSSI_THR 0x00000700
156#define INIT_BCON_CNTRL_REG 0x00000000
157
158#define TU_TO_USEC(_tu) ((_tu) << 10)
159
160#define ATH9K_HW_RX_HP_QDEPTH 16
161#define ATH9K_HW_RX_LP_QDEPTH 128
162
160#define PAPRD_GAIN_TABLE_ENTRIES 32
161#define PAPRD_TABLE_SZ 24
163#define PAPRD_GAIN_TABLE_ENTRIES 32
164#define PAPRD_TABLE_SZ 24
165#define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
162
163enum ath_hw_txq_subtype {
164 ATH_TXQ_AC_BE = 0,
165 ATH_TXQ_AC_BK = 1,
166 ATH_TXQ_AC_VI = 2,
167 ATH_TXQ_AC_VO = 3,
168};
169

--- 40 unchanged lines hidden (view full) ---

210};
211
212struct ath9k_ops_config {
213 int dma_beacon_response_time;
214 int sw_beacon_response_time;
215 int additional_swba_backoff;
216 int ack_6mb;
217 u32 cwm_ignore_extcca;
166
167enum ath_hw_txq_subtype {
168 ATH_TXQ_AC_BE = 0,
169 ATH_TXQ_AC_BK = 1,
170 ATH_TXQ_AC_VI = 2,
171 ATH_TXQ_AC_VO = 3,
172};
173

--- 40 unchanged lines hidden (view full) ---

214};
215
216struct ath9k_ops_config {
217 int dma_beacon_response_time;
218 int sw_beacon_response_time;
219 int additional_swba_backoff;
220 int ack_6mb;
221 u32 cwm_ignore_extcca;
218 u8 pcie_powersave_enable;
219 bool pcieSerDesWrite;
220 u8 pcie_clock_req;
221 u32 pcie_waen;
222 u8 analog_shiftreg;
223 u8 paprd_disable;
224 u32 ofdm_trig_low;
225 u32 ofdm_trig_high;
226 u32 cck_trig_high;

--- 171 unchanged lines hidden (view full) ---

398 ATH9K_RX_QUEUE_LP,
399 ATH9K_RX_QUEUE_MAX,
400};
401
402struct ath9k_beacon_state {
403 u32 bs_nexttbtt;
404 u32 bs_nextdtim;
405 u32 bs_intval;
222 bool pcieSerDesWrite;
223 u8 pcie_clock_req;
224 u32 pcie_waen;
225 u8 analog_shiftreg;
226 u8 paprd_disable;
227 u32 ofdm_trig_low;
228 u32 ofdm_trig_high;
229 u32 cck_trig_high;

--- 171 unchanged lines hidden (view full) ---

401 ATH9K_RX_QUEUE_LP,
402 ATH9K_RX_QUEUE_MAX,
403};
404
405struct ath9k_beacon_state {
406 u32 bs_nexttbtt;
407 u32 bs_nextdtim;
408 u32 bs_intval;
406#define ATH9K_BEACON_PERIOD 0x0000ffff
407#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
408 u32 bs_dtimperiod;
409 u16 bs_cfpperiod;
410 u16 bs_cfpmaxduration;
411 u32 bs_cfpnext;
412 u16 bs_timoffset;
413 u16 bs_bmissthreshold;
414 u32 bs_sleepduration;

--- 183 unchanged lines hidden (view full) ---

598 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
599 */
600struct ath_hw_ops {
601 void (*config_pci_powersave)(struct ath_hw *ah,
602 int restore,
603 int power_off);
604 void (*rx_enable)(struct ath_hw *ah);
605 void (*set_desc_link)(void *ds, u32 link);
409#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
410 u32 bs_dtimperiod;
411 u16 bs_cfpperiod;
412 u16 bs_cfpmaxduration;
413 u32 bs_cfpnext;
414 u16 bs_timoffset;
415 u16 bs_bmissthreshold;
416 u32 bs_sleepduration;

--- 183 unchanged lines hidden (view full) ---

600 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
601 */
602struct ath_hw_ops {
603 void (*config_pci_powersave)(struct ath_hw *ah,
604 int restore,
605 int power_off);
606 void (*rx_enable)(struct ath_hw *ah);
607 void (*set_desc_link)(void *ds, u32 link);
606 void (*get_desc_link)(void *ds, u32 **link);
607 bool (*calibrate)(struct ath_hw *ah,
608 struct ath9k_channel *chan,
609 u8 rxchainmask,
610 bool longcal);
611 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
612 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
613 bool is_firstseg, bool is_is_lastseg,
614 const void *ds0, dma_addr_t buf_addr,

--- 51 unchanged lines hidden (view full) ---

666 struct ar5416_eeprom_4k map4k;
667 struct ar9287_eeprom map9287;
668 struct ar9300_eeprom ar9300_eep;
669 } eeprom;
670 const struct eeprom_ops *eep_ops;
671
672 bool sw_mgmt_crypto;
673 bool is_pciexpress;
608 bool (*calibrate)(struct ath_hw *ah,
609 struct ath9k_channel *chan,
610 u8 rxchainmask,
611 bool longcal);
612 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
613 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
614 bool is_firstseg, bool is_is_lastseg,
615 const void *ds0, dma_addr_t buf_addr,

--- 51 unchanged lines hidden (view full) ---

667 struct ar5416_eeprom_4k map4k;
668 struct ar9287_eeprom map9287;
669 struct ar9300_eeprom ar9300_eep;
670 } eeprom;
671 const struct eeprom_ops *eep_ops;
672
673 bool sw_mgmt_crypto;
674 bool is_pciexpress;
675 bool aspm_enabled;
674 bool is_monitoring;
675 bool need_an_top2_fixup;
676 u16 tx_trig_level;
677
678 u32 nf_regs[6];
679 struct ath_nf_limits nf_2g;
680 struct ath_nf_limits nf_5g;
681 u16 rfsilent;

--- 175 unchanged lines hidden (view full) ---

857 * this register when in sleep states.
858 */
859 u32 WARegVal;
860
861 /* Enterprise mode cap */
862 u32 ent_mode;
863
864 bool is_clk_25mhz;
676 bool is_monitoring;
677 bool need_an_top2_fixup;
678 u16 tx_trig_level;
679
680 u32 nf_regs[6];
681 struct ath_nf_limits nf_2g;
682 struct ath_nf_limits nf_5g;
683 u16 rfsilent;

--- 175 unchanged lines hidden (view full) ---

859 * this register when in sleep states.
860 */
861 u32 WARegVal;
862
863 /* Enterprise mode cap */
864 u32 ent_mode;
865
866 bool is_clk_25mhz;
867 int (*get_mac_revision)(void);
868 int (*external_reset)(void);
865};
866
867struct ath_bus_ops {
868 enum ath_bus_type ath_bus_type;
869 void (*read_cachesize)(struct ath_common *common, int *csz);
870 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
871 void (*bt_coex_prep)(struct ath_common *common);
872 void (*extn_synch_en)(struct ath_common *common);
869};
870
871struct ath_bus_ops {
872 enum ath_bus_type ath_bus_type;
873 void (*read_cachesize)(struct ath_common *common, int *csz);
874 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
875 void (*bt_coex_prep)(struct ath_common *common);
876 void (*extn_synch_en)(struct ath_common *common);
877 void (*aspm_init)(struct ath_common *common);
873};
874
875static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
876{
877 return &ah->common;
878}
879
880static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)

--- 95 unchanged lines hidden (view full) ---

976
977/*
978 * Code Specific to AR5008, AR9001 or AR9002,
979 * we stuff these here to avoid callbacks for AR9003.
980 */
981void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
982int ar9002_hw_rf_claim(struct ath_hw *ah);
983void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
878};
879
880static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
881{
882 return &ah->common;
883}
884
885static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)

--- 95 unchanged lines hidden (view full) ---

981
982/*
983 * Code Specific to AR5008, AR9001 or AR9002,
984 * we stuff these here to avoid callbacks for AR9003.
985 */
986void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
987int ar9002_hw_rf_claim(struct ath_hw *ah);
988void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
984void ar9002_hw_update_async_fifo(struct ath_hw *ah);
985void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
986
987/*
988 * Code specific to AR9003, we stuff these here to avoid callbacks
989 * for older families
990 */
991void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
992void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
993void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);

--- 46 unchanged lines hidden --- 		989
990/*
991 * Code specific to AR9003, we stuff these here to avoid callbacks
992 * for older families
993 */
994void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
995void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
996void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);

--- 46 unchanged lines hidden ---