1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef HW_H 18 #define HW_H 19 20 #include <linux/if_ether.h> 21 #include <linux/delay.h> 22 #include <linux/io.h> 23 24 #include "mac.h" 25 #include "ani.h" 26 #include "eeprom.h" 27 #include "calib.h" 28 #include "reg.h" 29 #include "phy.h" 30 #include "btcoex.h" 31 32 #include "../regd.h" 33 34 #define ATHEROS_VENDOR_ID 0x168c 35 36 #define AR5416_DEVID_PCI 0x0023 37 #define AR5416_DEVID_PCIE 0x0024 38 #define AR9160_DEVID_PCI 0x0027 39 #define AR9280_DEVID_PCI 0x0029 40 #define AR9280_DEVID_PCIE 0x002a 41 #define AR9285_DEVID_PCIE 0x002b 42 #define AR2427_DEVID_PCIE 0x002c 43 #define AR9287_DEVID_PCI 0x002d 44 #define AR9287_DEVID_PCIE 0x002e 45 #define AR9300_DEVID_PCIE 0x0030 46 #define AR9300_DEVID_AR9340 0x0031 47 #define AR9300_DEVID_AR9485_PCIE 0x0032 48 49 #define AR5416_AR9100_DEVID 0x000b 50 51 #define AR_SUBVENDOR_ID_NOG 0x0e11 52 #define AR_SUBVENDOR_ID_NEW_A 0x7065 53 #define AR5416_MAGIC 0x19641014 54 55 #define AR9280_COEX2WIRE_SUBSYSID 0x309b 56 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa 57 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab 58 59 #define AR9300_NUM_BT_WEIGHTS 4 60 #define AR9300_NUM_WLAN_WEIGHTS 4 61 62 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) 63 64 #define ATH_DEFAULT_NOISE_FLOOR -95 65 66 #define ATH9K_RSSI_BAD -128 67 68 #define ATH9K_NUM_CHANNELS 38 69 70 /* Register read/write primitives */ 71 #define REG_WRITE(_ah, _reg, _val) \ 72 (_ah)->reg_ops.write((_ah), (_val), (_reg)) 73 74 #define REG_READ(_ah, _reg) \ 75 (_ah)->reg_ops.read((_ah), (_reg)) 76 77 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ 78 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) 79 80 #define REG_RMW(_ah, _reg, _set, _clr) \ 81 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) 82 83 #define ENABLE_REGWRITE_BUFFER(_ah) \ 84 do { \ 85 if ((_ah)->reg_ops.enable_write_buffer) \ 86 (_ah)->reg_ops.enable_write_buffer((_ah)); \ 87 } while (0) 88 89 #define REGWRITE_BUFFER_FLUSH(_ah) \ 90 do { \ 91 if ((_ah)->reg_ops.write_flush) \ 92 (_ah)->reg_ops.write_flush((_ah)); \ 93 } while (0) 94 95 #define SM(_v, _f) (((_v) << _f##_S) & _f) 96 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 97 #define REG_RMW_FIELD(_a, _r, _f, _v) \ 98 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) 99 #define REG_READ_FIELD(_a, _r, _f) \ 100 (((REG_READ(_a, _r) & _f) >> _f##_S)) 101 #define REG_SET_BIT(_a, _r, _f) \ 102 REG_RMW(_a, _r, (_f), 0) 103 #define REG_CLR_BIT(_a, _r, _f) \ 104 REG_RMW(_a, _r, 0, (_f)) 105 106 #define DO_DELAY(x) do { \ 107 if (((++(x) % 64) == 0) && \ 108 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ 109 != ATH_USB)) \ 110 udelay(1); \ 111 } while (0) 112 113 #define REG_WRITE_ARRAY(iniarray, column, regWr) \ 114 ath9k_hw_write_array(ah, iniarray, column, &(regWr)) 115 116 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 117 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 118 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 119 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 120 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 121 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 122 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 123 124 #define AR_GPIOD_MASK 0x00001FFF 125 #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 126 127 #define BASE_ACTIVATE_DELAY 100 128 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) 129 #define COEF_SCALE_S 24 130 #define HT40_CHANNEL_CENTER_SHIFT 10 131 132 #define ATH9K_ANTENNA0_CHAINMASK 0x1 133 #define ATH9K_ANTENNA1_CHAINMASK 0x2 134 135 #define ATH9K_NUM_DMA_DEBUG_REGS 8 136 #define ATH9K_NUM_QUEUES 10 137 138 #define MAX_RATE_POWER 63 139 #define AH_WAIT_TIMEOUT 100000 /* (us) */ 140 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ 141 #define AH_TIME_QUANTUM 10 142 #define AR_KEYTABLE_SIZE 128 143 #define POWER_UP_TIME 10000 144 #define SPUR_RSSI_THRESH 40 145 146 #define CAB_TIMEOUT_VAL 10 147 #define BEACON_TIMEOUT_VAL 10 148 #define MIN_BEACON_TIMEOUT_VAL 1 149 #define SLEEP_SLOP 3 150 151 #define INIT_CONFIG_STATUS 0x00000000 152 #define INIT_RSSI_THR 0x00000700 153 #define INIT_BCON_CNTRL_REG 0x00000000 154 155 #define TU_TO_USEC(_tu) ((_tu) << 10) 156 157 #define ATH9K_HW_RX_HP_QDEPTH 16 158 #define ATH9K_HW_RX_LP_QDEPTH 128 159 160 #define PAPRD_GAIN_TABLE_ENTRIES 32 161 #define PAPRD_TABLE_SZ 24 162 163 enum ath_hw_txq_subtype { 164 ATH_TXQ_AC_BE = 0, 165 ATH_TXQ_AC_BK = 1, 166 ATH_TXQ_AC_VI = 2, 167 ATH_TXQ_AC_VO = 3, 168 }; 169 170 enum ath_ini_subsys { 171 ATH_INI_PRE = 0, 172 ATH_INI_CORE, 173 ATH_INI_POST, 174 ATH_INI_NUM_SPLIT, 175 }; 176 177 enum ath9k_hw_caps { 178 ATH9K_HW_CAP_HT = BIT(0), 179 ATH9K_HW_CAP_RFSILENT = BIT(1), 180 ATH9K_HW_CAP_CST = BIT(2), 181 ATH9K_HW_CAP_AUTOSLEEP = BIT(4), 182 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5), 183 ATH9K_HW_CAP_EDMA = BIT(6), 184 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7), 185 ATH9K_HW_CAP_LDPC = BIT(8), 186 ATH9K_HW_CAP_FASTCLOCK = BIT(9), 187 ATH9K_HW_CAP_SGI_20 = BIT(10), 188 ATH9K_HW_CAP_PAPRD = BIT(11), 189 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12), 190 ATH9K_HW_CAP_2GHZ = BIT(13), 191 ATH9K_HW_CAP_5GHZ = BIT(14), 192 ATH9K_HW_CAP_APM = BIT(15), 193 }; 194 195 struct ath9k_hw_capabilities { 196 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ 197 u16 rts_aggr_limit; 198 u8 tx_chainmask; 199 u8 rx_chainmask; 200 u8 max_txchains; 201 u8 max_rxchains; 202 u8 num_gpio_pins; 203 u8 rx_hp_qdepth; 204 u8 rx_lp_qdepth; 205 u8 rx_status_len; 206 u8 tx_desc_len; 207 u8 txs_len; 208 u16 pcie_lcr_offset; 209 bool pcie_lcr_extsync_en; 210 }; 211 212 struct ath9k_ops_config { 213 int dma_beacon_response_time; 214 int sw_beacon_response_time; 215 int additional_swba_backoff; 216 int ack_6mb; 217 u32 cwm_ignore_extcca; 218 u8 pcie_powersave_enable; 219 bool pcieSerDesWrite; 220 u8 pcie_clock_req; 221 u32 pcie_waen; 222 u8 analog_shiftreg; 223 u8 paprd_disable; 224 u32 ofdm_trig_low; 225 u32 ofdm_trig_high; 226 u32 cck_trig_high; 227 u32 cck_trig_low; 228 u32 enable_ani; 229 int serialize_regmode; 230 bool rx_intr_mitigation; 231 bool tx_intr_mitigation; 232 #define SPUR_DISABLE 0 233 #define SPUR_ENABLE_IOCTL 1 234 #define SPUR_ENABLE_EEPROM 2 235 #define AR_SPUR_5413_1 1640 236 #define AR_SPUR_5413_2 1200 237 #define AR_NO_SPUR 0x8000 238 #define AR_BASE_FREQ_2GHZ 2300 239 #define AR_BASE_FREQ_5GHZ 4900 240 #define AR_SPUR_FEEQ_BOUND_HT40 19 241 #define AR_SPUR_FEEQ_BOUND_HT20 10 242 int spurmode; 243 u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; 244 u8 max_txtrig_level; 245 u16 ani_poll_interval; /* ANI poll interval in ms */ 246 }; 247 248 enum ath9k_int { 249 ATH9K_INT_RX = 0x00000001, 250 ATH9K_INT_RXDESC = 0x00000002, 251 ATH9K_INT_RXHP = 0x00000001, 252 ATH9K_INT_RXLP = 0x00000002, 253 ATH9K_INT_RXNOFRM = 0x00000008, 254 ATH9K_INT_RXEOL = 0x00000010, 255 ATH9K_INT_RXORN = 0x00000020, 256 ATH9K_INT_TX = 0x00000040, 257 ATH9K_INT_TXDESC = 0x00000080, 258 ATH9K_INT_TIM_TIMER = 0x00000100, 259 ATH9K_INT_BB_WATCHDOG = 0x00000400, 260 ATH9K_INT_TXURN = 0x00000800, 261 ATH9K_INT_MIB = 0x00001000, 262 ATH9K_INT_RXPHY = 0x00004000, 263 ATH9K_INT_RXKCM = 0x00008000, 264 ATH9K_INT_SWBA = 0x00010000, 265 ATH9K_INT_BMISS = 0x00040000, 266 ATH9K_INT_BNR = 0x00100000, 267 ATH9K_INT_TIM = 0x00200000, 268 ATH9K_INT_DTIM = 0x00400000, 269 ATH9K_INT_DTIMSYNC = 0x00800000, 270 ATH9K_INT_GPIO = 0x01000000, 271 ATH9K_INT_CABEND = 0x02000000, 272 ATH9K_INT_TSFOOR = 0x04000000, 273 ATH9K_INT_GENTIMER = 0x08000000, 274 ATH9K_INT_CST = 0x10000000, 275 ATH9K_INT_GTT = 0x20000000, 276 ATH9K_INT_FATAL = 0x40000000, 277 ATH9K_INT_GLOBAL = 0x80000000, 278 ATH9K_INT_BMISC = ATH9K_INT_TIM | 279 ATH9K_INT_DTIM | 280 ATH9K_INT_DTIMSYNC | 281 ATH9K_INT_TSFOOR | 282 ATH9K_INT_CABEND, 283 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | 284 ATH9K_INT_RXDESC | 285 ATH9K_INT_RXEOL | 286 ATH9K_INT_RXORN | 287 ATH9K_INT_TXURN | 288 ATH9K_INT_TXDESC | 289 ATH9K_INT_MIB | 290 ATH9K_INT_RXPHY | 291 ATH9K_INT_RXKCM | 292 ATH9K_INT_SWBA | 293 ATH9K_INT_BMISS | 294 ATH9K_INT_GPIO, 295 ATH9K_INT_NOCARD = 0xffffffff 296 }; 297 298 #define CHANNEL_CW_INT 0x00002 299 #define CHANNEL_CCK 0x00020 300 #define CHANNEL_OFDM 0x00040 301 #define CHANNEL_2GHZ 0x00080 302 #define CHANNEL_5GHZ 0x00100 303 #define CHANNEL_PASSIVE 0x00200 304 #define CHANNEL_DYN 0x00400 305 #define CHANNEL_HALF 0x04000 306 #define CHANNEL_QUARTER 0x08000 307 #define CHANNEL_HT20 0x10000 308 #define CHANNEL_HT40PLUS 0x20000 309 #define CHANNEL_HT40MINUS 0x40000 310 311 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 312 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 313 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 314 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) 315 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) 316 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) 317 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) 318 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) 319 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) 320 #define CHANNEL_ALL \ 321 (CHANNEL_OFDM| \ 322 CHANNEL_CCK| \ 323 CHANNEL_2GHZ | \ 324 CHANNEL_5GHZ | \ 325 CHANNEL_HT20 | \ 326 CHANNEL_HT40PLUS | \ 327 CHANNEL_HT40MINUS) 328 329 struct ath9k_hw_cal_data { 330 u16 channel; 331 u32 channelFlags; 332 int32_t CalValid; 333 int8_t iCoff; 334 int8_t qCoff; 335 bool paprd_done; 336 bool nfcal_pending; 337 bool nfcal_interference; 338 u16 small_signal_gain[AR9300_MAX_CHAINS]; 339 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; 340 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 341 }; 342 343 struct ath9k_channel { 344 struct ieee80211_channel *chan; 345 struct ar5416AniState ani; 346 u16 channel; 347 u32 channelFlags; 348 u32 chanmode; 349 s16 noisefloor; 350 }; 351 352 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ 353 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ 354 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ 355 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) 356 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) 357 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) 358 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) 359 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) 360 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) 361 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ 362 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ 363 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) 364 365 /* These macros check chanmode and not channelFlags */ 366 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) 367 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ 368 ((_c)->chanmode == CHANNEL_G_HT20)) 369 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ 370 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ 371 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ 372 ((_c)->chanmode == CHANNEL_G_HT40MINUS)) 373 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) 374 375 enum ath9k_power_mode { 376 ATH9K_PM_AWAKE = 0, 377 ATH9K_PM_FULL_SLEEP, 378 ATH9K_PM_NETWORK_SLEEP, 379 ATH9K_PM_UNDEFINED 380 }; 381 382 enum ath9k_tp_scale { 383 ATH9K_TP_SCALE_MAX = 0, 384 ATH9K_TP_SCALE_50, 385 ATH9K_TP_SCALE_25, 386 ATH9K_TP_SCALE_12, 387 ATH9K_TP_SCALE_MIN 388 }; 389 390 enum ser_reg_mode { 391 SER_REG_MODE_OFF = 0, 392 SER_REG_MODE_ON = 1, 393 SER_REG_MODE_AUTO = 2, 394 }; 395 396 enum ath9k_rx_qtype { 397 ATH9K_RX_QUEUE_HP, 398 ATH9K_RX_QUEUE_LP, 399 ATH9K_RX_QUEUE_MAX, 400 }; 401 402 struct ath9k_beacon_state { 403 u32 bs_nexttbtt; 404 u32 bs_nextdtim; 405 u32 bs_intval; 406 #define ATH9K_BEACON_PERIOD 0x0000ffff 407 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ 408 u32 bs_dtimperiod; 409 u16 bs_cfpperiod; 410 u16 bs_cfpmaxduration; 411 u32 bs_cfpnext; 412 u16 bs_timoffset; 413 u16 bs_bmissthreshold; 414 u32 bs_sleepduration; 415 u32 bs_tsfoor_threshold; 416 }; 417 418 struct chan_centers { 419 u16 synth_center; 420 u16 ctl_center; 421 u16 ext_center; 422 }; 423 424 enum { 425 ATH9K_RESET_POWER_ON, 426 ATH9K_RESET_WARM, 427 ATH9K_RESET_COLD, 428 }; 429 430 struct ath9k_hw_version { 431 u32 magic; 432 u16 devid; 433 u16 subvendorid; 434 u32 macVersion; 435 u16 macRev; 436 u16 phyRev; 437 u16 analog5GhzRev; 438 u16 analog2GhzRev; 439 u16 subsysid; 440 enum ath_usb_dev usbdev; 441 }; 442 443 /* Generic TSF timer definitions */ 444 445 #define ATH_MAX_GEN_TIMER 16 446 447 #define AR_GENTMR_BIT(_index) (1 << (_index)) 448 449 /* 450 * Using de Bruijin sequence to look up 1's index in a 32 bit number 451 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 452 */ 453 #define debruijn32 0x077CB531U 454 455 struct ath_gen_timer_configuration { 456 u32 next_addr; 457 u32 period_addr; 458 u32 mode_addr; 459 u32 mode_mask; 460 }; 461 462 struct ath_gen_timer { 463 void (*trigger)(void *arg); 464 void (*overflow)(void *arg); 465 void *arg; 466 u8 index; 467 }; 468 469 struct ath_gen_timer_table { 470 u32 gen_timer_index[32]; 471 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; 472 union { 473 unsigned long timer_bits; 474 u16 val; 475 } timer_mask; 476 }; 477 478 struct ath_hw_antcomb_conf { 479 u8 main_lna_conf; 480 u8 alt_lna_conf; 481 u8 fast_div_bias; 482 u8 main_gaintb; 483 u8 alt_gaintb; 484 int lna1_lna2_delta; 485 u8 div_group; 486 }; 487 488 /** 489 * struct ath_hw_radar_conf - radar detection initialization parameters 490 * 491 * @pulse_inband: threshold for checking the ratio of in-band power 492 * to total power for short radar pulses (half dB steps) 493 * @pulse_inband_step: threshold for checking an in-band power to total 494 * power ratio increase for short radar pulses (half dB steps) 495 * @pulse_height: threshold for detecting the beginning of a short 496 * radar pulse (dB step) 497 * @pulse_rssi: threshold for detecting if a short radar pulse is 498 * gone (dB step) 499 * @pulse_maxlen: maximum pulse length (0.8 us steps) 500 * 501 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) 502 * @radar_inband: threshold for checking the ratio of in-band power 503 * to total power for long radar pulses (half dB steps) 504 * @fir_power: threshold for detecting the end of a long radar pulse (dB) 505 * 506 * @ext_channel: enable extension channel radar detection 507 */ 508 struct ath_hw_radar_conf { 509 unsigned int pulse_inband; 510 unsigned int pulse_inband_step; 511 unsigned int pulse_height; 512 unsigned int pulse_rssi; 513 unsigned int pulse_maxlen; 514 515 unsigned int radar_rssi; 516 unsigned int radar_inband; 517 int fir_power; 518 519 bool ext_channel; 520 }; 521 522 /** 523 * struct ath_hw_private_ops - callbacks used internally by hardware code 524 * 525 * This structure contains private callbacks designed to only be used internally 526 * by the hardware core. 527 * 528 * @init_cal_settings: setup types of calibrations supported 529 * @init_cal: starts actual calibration 530 * 531 * @init_mode_regs: Initializes mode registers 532 * @init_mode_gain_regs: Initialize TX/RX gain registers 533 * 534 * @rf_set_freq: change frequency 535 * @spur_mitigate_freq: spur mitigation 536 * @rf_alloc_ext_banks: 537 * @rf_free_ext_banks: 538 * @set_rf_regs: 539 * @compute_pll_control: compute the PLL control value to use for 540 * AR_RTC_PLL_CONTROL for a given channel 541 * @setup_calibration: set up calibration 542 * @iscal_supported: used to query if a type of calibration is supported 543 * 544 * @ani_cache_ini_regs: cache the values for ANI from the initial 545 * register settings through the register initialization. 546 */ 547 struct ath_hw_private_ops { 548 /* Calibration ops */ 549 void (*init_cal_settings)(struct ath_hw *ah); 550 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); 551 552 void (*init_mode_regs)(struct ath_hw *ah); 553 void (*init_mode_gain_regs)(struct ath_hw *ah); 554 void (*setup_calibration)(struct ath_hw *ah, 555 struct ath9k_cal_list *currCal); 556 557 /* PHY ops */ 558 int (*rf_set_freq)(struct ath_hw *ah, 559 struct ath9k_channel *chan); 560 void (*spur_mitigate_freq)(struct ath_hw *ah, 561 struct ath9k_channel *chan); 562 int (*rf_alloc_ext_banks)(struct ath_hw *ah); 563 void (*rf_free_ext_banks)(struct ath_hw *ah); 564 bool (*set_rf_regs)(struct ath_hw *ah, 565 struct ath9k_channel *chan, 566 u16 modesIndex); 567 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); 568 void (*init_bb)(struct ath_hw *ah, 569 struct ath9k_channel *chan); 570 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); 571 void (*olc_init)(struct ath_hw *ah); 572 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); 573 void (*mark_phy_inactive)(struct ath_hw *ah); 574 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); 575 bool (*rfbus_req)(struct ath_hw *ah); 576 void (*rfbus_done)(struct ath_hw *ah); 577 void (*restore_chainmask)(struct ath_hw *ah); 578 void (*set_diversity)(struct ath_hw *ah, bool value); 579 u32 (*compute_pll_control)(struct ath_hw *ah, 580 struct ath9k_channel *chan); 581 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, 582 int param); 583 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); 584 void (*set_radar_params)(struct ath_hw *ah, 585 struct ath_hw_radar_conf *conf); 586 587 /* ANI */ 588 void (*ani_cache_ini_regs)(struct ath_hw *ah); 589 }; 590 591 /** 592 * struct ath_hw_ops - callbacks used by hardware code and driver code 593 * 594 * This structure contains callbacks designed to to be used internally by 595 * hardware code and also by the lower level driver. 596 * 597 * @config_pci_powersave: 598 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC 599 */ 600 struct ath_hw_ops { 601 void (*config_pci_powersave)(struct ath_hw *ah, 602 int restore, 603 int power_off); 604 void (*rx_enable)(struct ath_hw *ah); 605 void (*set_desc_link)(void *ds, u32 link); 606 void (*get_desc_link)(void *ds, u32 **link); 607 bool (*calibrate)(struct ath_hw *ah, 608 struct ath9k_channel *chan, 609 u8 rxchainmask, 610 bool longcal); 611 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); 612 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen, 613 bool is_firstseg, bool is_is_lastseg, 614 const void *ds0, dma_addr_t buf_addr, 615 unsigned int qcu); 616 int (*proc_txdesc)(struct ath_hw *ah, void *ds, 617 struct ath_tx_status *ts); 618 void (*set11n_txdesc)(struct ath_hw *ah, void *ds, 619 u32 pktLen, enum ath9k_pkt_type type, 620 u32 txPower, u32 keyIx, 621 enum ath9k_key_type keyType, 622 u32 flags); 623 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds, 624 void *lastds, 625 u32 durUpdateEn, u32 rtsctsRate, 626 u32 rtsctsDuration, 627 struct ath9k_11n_rate_series series[], 628 u32 nseries, u32 flags); 629 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds, 630 u32 aggrLen); 631 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds, 632 u32 numDelims); 633 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds); 634 void (*clr11n_aggr)(struct ath_hw *ah, void *ds); 635 void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val); 636 void (*antdiv_comb_conf_get)(struct ath_hw *ah, 637 struct ath_hw_antcomb_conf *antconf); 638 void (*antdiv_comb_conf_set)(struct ath_hw *ah, 639 struct ath_hw_antcomb_conf *antconf); 640 641 }; 642 643 struct ath_nf_limits { 644 s16 max; 645 s16 min; 646 s16 nominal; 647 }; 648 649 /* ah_flags */ 650 #define AH_USE_EEPROM 0x1 651 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ 652 653 struct ath_hw { 654 struct ath_ops reg_ops; 655 656 struct ieee80211_hw *hw; 657 struct ath_common common; 658 struct ath9k_hw_version hw_version; 659 struct ath9k_ops_config config; 660 struct ath9k_hw_capabilities caps; 661 struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; 662 struct ath9k_channel *curchan; 663 664 union { 665 struct ar5416_eeprom_def def; 666 struct ar5416_eeprom_4k map4k; 667 struct ar9287_eeprom map9287; 668 struct ar9300_eeprom ar9300_eep; 669 } eeprom; 670 const struct eeprom_ops *eep_ops; 671 672 bool sw_mgmt_crypto; 673 bool is_pciexpress; 674 bool is_monitoring; 675 bool need_an_top2_fixup; 676 u16 tx_trig_level; 677 678 u32 nf_regs[6]; 679 struct ath_nf_limits nf_2g; 680 struct ath_nf_limits nf_5g; 681 u16 rfsilent; 682 u32 rfkill_gpio; 683 u32 rfkill_polarity; 684 u32 ah_flags; 685 686 bool htc_reset_init; 687 688 enum nl80211_iftype opmode; 689 enum ath9k_power_mode power_mode; 690 691 struct ath9k_hw_cal_data *caldata; 692 struct ath9k_pacal_info pacal_info; 693 struct ar5416Stats stats; 694 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; 695 696 int16_t curchan_rad_index; 697 enum ath9k_int imask; 698 u32 imrs2_reg; 699 u32 txok_interrupt_mask; 700 u32 txerr_interrupt_mask; 701 u32 txdesc_interrupt_mask; 702 u32 txeol_interrupt_mask; 703 u32 txurn_interrupt_mask; 704 bool chip_fullsleep; 705 u32 atim_window; 706 707 /* Calibration */ 708 u32 supp_cals; 709 struct ath9k_cal_list iq_caldata; 710 struct ath9k_cal_list adcgain_caldata; 711 struct ath9k_cal_list adcdc_caldata; 712 struct ath9k_cal_list tempCompCalData; 713 struct ath9k_cal_list *cal_list; 714 struct ath9k_cal_list *cal_list_last; 715 struct ath9k_cal_list *cal_list_curr; 716 #define totalPowerMeasI meas0.unsign 717 #define totalPowerMeasQ meas1.unsign 718 #define totalIqCorrMeas meas2.sign 719 #define totalAdcIOddPhase meas0.unsign 720 #define totalAdcIEvenPhase meas1.unsign 721 #define totalAdcQOddPhase meas2.unsign 722 #define totalAdcQEvenPhase meas3.unsign 723 #define totalAdcDcOffsetIOddPhase meas0.sign 724 #define totalAdcDcOffsetIEvenPhase meas1.sign 725 #define totalAdcDcOffsetQOddPhase meas2.sign 726 #define totalAdcDcOffsetQEvenPhase meas3.sign 727 union { 728 u32 unsign[AR5416_MAX_CHAINS]; 729 int32_t sign[AR5416_MAX_CHAINS]; 730 } meas0; 731 union { 732 u32 unsign[AR5416_MAX_CHAINS]; 733 int32_t sign[AR5416_MAX_CHAINS]; 734 } meas1; 735 union { 736 u32 unsign[AR5416_MAX_CHAINS]; 737 int32_t sign[AR5416_MAX_CHAINS]; 738 } meas2; 739 union { 740 u32 unsign[AR5416_MAX_CHAINS]; 741 int32_t sign[AR5416_MAX_CHAINS]; 742 } meas3; 743 u16 cal_samples; 744 745 u32 sta_id1_defaults; 746 u32 misc_mode; 747 enum { 748 AUTO_32KHZ, 749 USE_32KHZ, 750 DONT_USE_32KHZ, 751 } enable_32kHz_clock; 752 753 /* Private to hardware code */ 754 struct ath_hw_private_ops private_ops; 755 /* Accessed by the lower level driver */ 756 struct ath_hw_ops ops; 757 758 /* Used to program the radio on non single-chip devices */ 759 u32 *analogBank0Data; 760 u32 *analogBank1Data; 761 u32 *analogBank2Data; 762 u32 *analogBank3Data; 763 u32 *analogBank6Data; 764 u32 *analogBank6TPCData; 765 u32 *analogBank7Data; 766 u32 *addac5416_21; 767 u32 *bank6Temp; 768 769 u8 txpower_limit; 770 int coverage_class; 771 u32 slottime; 772 u32 globaltxtimeout; 773 774 /* ANI */ 775 u32 proc_phyerr; 776 u32 aniperiod; 777 int totalSizeDesired[5]; 778 int coarse_high[5]; 779 int coarse_low[5]; 780 int firpwr[5]; 781 enum ath9k_ani_cmd ani_function; 782 783 /* Bluetooth coexistance */ 784 struct ath_btcoex_hw btcoex_hw; 785 u32 bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS]; 786 u32 bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS]; 787 788 u32 intr_txqs; 789 u8 txchainmask; 790 u8 rxchainmask; 791 792 struct ath_hw_radar_conf radar_conf; 793 794 u32 originalGain[22]; 795 int initPDADC; 796 int PDADCdelta; 797 int led_pin; 798 u32 gpio_mask; 799 u32 gpio_val; 800 801 struct ar5416IniArray iniModes; 802 struct ar5416IniArray iniCommon; 803 struct ar5416IniArray iniBank0; 804 struct ar5416IniArray iniBB_RfGain; 805 struct ar5416IniArray iniBank1; 806 struct ar5416IniArray iniBank2; 807 struct ar5416IniArray iniBank3; 808 struct ar5416IniArray iniBank6; 809 struct ar5416IniArray iniBank6TPC; 810 struct ar5416IniArray iniBank7; 811 struct ar5416IniArray iniAddac; 812 struct ar5416IniArray iniPcieSerdes; 813 struct ar5416IniArray iniPcieSerdesLowPower; 814 struct ar5416IniArray iniModesAdditional; 815 struct ar5416IniArray iniModesAdditional_40M; 816 struct ar5416IniArray iniModesRxGain; 817 struct ar5416IniArray iniModesTxGain; 818 struct ar5416IniArray iniModes_9271_1_0_only; 819 struct ar5416IniArray iniCckfirNormal; 820 struct ar5416IniArray iniCckfirJapan2484; 821 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271; 822 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271; 823 struct ar5416IniArray iniModes_9271_ANI_reg; 824 struct ar5416IniArray iniModes_high_power_tx_gain_9271; 825 struct ar5416IniArray iniModes_normal_power_tx_gain_9271; 826 827 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; 828 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; 829 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; 830 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; 831 832 u32 intr_gen_timer_trigger; 833 u32 intr_gen_timer_thresh; 834 struct ath_gen_timer_table hw_gen_timers; 835 836 struct ar9003_txs *ts_ring; 837 void *ts_start; 838 u32 ts_paddr_start; 839 u32 ts_paddr_end; 840 u16 ts_tail; 841 u8 ts_size; 842 843 u32 bb_watchdog_last_status; 844 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ 845 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */ 846 847 unsigned int paprd_target_power; 848 unsigned int paprd_training_power; 849 unsigned int paprd_ratemask; 850 unsigned int paprd_ratemask_ht40; 851 bool paprd_table_write_done; 852 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; 853 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; 854 /* 855 * Store the permanent value of Reg 0x4004in WARegVal 856 * so we dont have to R/M/W. We should not be reading 857 * this register when in sleep states. 858 */ 859 u32 WARegVal; 860 861 /* Enterprise mode cap */ 862 u32 ent_mode; 863 864 bool is_clk_25mhz; 865 }; 866 867 struct ath_bus_ops { 868 enum ath_bus_type ath_bus_type; 869 void (*read_cachesize)(struct ath_common *common, int *csz); 870 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); 871 void (*bt_coex_prep)(struct ath_common *common); 872 void (*extn_synch_en)(struct ath_common *common); 873 }; 874 875 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 876 { 877 return &ah->common; 878 } 879 880 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) 881 { 882 return &(ath9k_hw_common(ah)->regulatory); 883 } 884 885 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) 886 { 887 return &ah->private_ops; 888 } 889 890 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) 891 { 892 return &ah->ops; 893 } 894 895 static inline u8 get_streams(int mask) 896 { 897 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); 898 } 899 900 /* Initialization, Detach, Reset */ 901 const char *ath9k_hw_probe(u16 vendorid, u16 devid); 902 void ath9k_hw_deinit(struct ath_hw *ah); 903 int ath9k_hw_init(struct ath_hw *ah); 904 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 905 struct ath9k_hw_cal_data *caldata, bool bChannelChange); 906 int ath9k_hw_fill_cap_info(struct ath_hw *ah); 907 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); 908 909 /* GPIO / RFKILL / Antennae */ 910 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); 911 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); 912 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 913 u32 ah_signal_type); 914 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); 915 u32 ath9k_hw_getdefantenna(struct ath_hw *ah); 916 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); 917 918 /* General Operation */ 919 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); 920 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 921 int column, unsigned int *writecnt); 922 u32 ath9k_hw_reverse_bits(u32 val, u32 n); 923 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 924 u8 phy, int kbps, 925 u32 frameLen, u16 rateix, bool shortPreamble); 926 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 927 struct ath9k_channel *chan, 928 struct chan_centers *centers); 929 u32 ath9k_hw_getrxfilter(struct ath_hw *ah); 930 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); 931 bool ath9k_hw_phy_disable(struct ath_hw *ah); 932 bool ath9k_hw_disable(struct ath_hw *ah); 933 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); 934 void ath9k_hw_setopmode(struct ath_hw *ah); 935 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); 936 void ath9k_hw_setbssidmask(struct ath_hw *ah); 937 void ath9k_hw_write_associd(struct ath_hw *ah); 938 u32 ath9k_hw_gettsf32(struct ath_hw *ah); 939 u64 ath9k_hw_gettsf64(struct ath_hw *ah); 940 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); 941 void ath9k_hw_reset_tsf(struct ath_hw *ah); 942 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); 943 void ath9k_hw_init_global_settings(struct ath_hw *ah); 944 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); 945 void ath9k_hw_set11nmac2040(struct ath_hw *ah); 946 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); 947 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 948 const struct ath9k_beacon_state *bs); 949 bool ath9k_hw_check_alive(struct ath_hw *ah); 950 951 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); 952 953 /* Generic hw timer primitives */ 954 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 955 void (*trigger)(void *), 956 void (*overflow)(void *), 957 void *arg, 958 u8 timer_index); 959 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 960 struct ath_gen_timer *timer, 961 u32 timer_next, 962 u32 timer_period); 963 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); 964 965 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); 966 void ath_gen_timer_isr(struct ath_hw *hw); 967 968 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); 969 970 /* HTC */ 971 void ath9k_hw_htc_resetinit(struct ath_hw *ah); 972 973 /* PHY */ 974 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 975 u32 *coef_mantissa, u32 *coef_exponent); 976 977 /* 978 * Code Specific to AR5008, AR9001 or AR9002, 979 * we stuff these here to avoid callbacks for AR9003. 980 */ 981 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah); 982 int ar9002_hw_rf_claim(struct ath_hw *ah); 983 void ar9002_hw_enable_async_fifo(struct ath_hw *ah); 984 void ar9002_hw_update_async_fifo(struct ath_hw *ah); 985 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah); 986 987 /* 988 * Code specific to AR9003, we stuff these here to avoid callbacks 989 * for older families 990 */ 991 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); 992 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); 993 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); 994 void ar9003_hw_disable_phy_restart(struct ath_hw *ah); 995 void ar9003_paprd_enable(struct ath_hw *ah, bool val); 996 void ar9003_paprd_populate_single_table(struct ath_hw *ah, 997 struct ath9k_hw_cal_data *caldata, 998 int chain); 999 int ar9003_paprd_create_curve(struct ath_hw *ah, 1000 struct ath9k_hw_cal_data *caldata, int chain); 1001 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); 1002 int ar9003_paprd_init_table(struct ath_hw *ah); 1003 bool ar9003_paprd_is_done(struct ath_hw *ah); 1004 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains); 1005 1006 /* Hardware family op attach helpers */ 1007 void ar5008_hw_attach_phy_ops(struct ath_hw *ah); 1008 void ar9002_hw_attach_phy_ops(struct ath_hw *ah); 1009 void ar9003_hw_attach_phy_ops(struct ath_hw *ah); 1010 1011 void ar9002_hw_attach_calib_ops(struct ath_hw *ah); 1012 void ar9003_hw_attach_calib_ops(struct ath_hw *ah); 1013 1014 void ar9002_hw_attach_ops(struct ath_hw *ah); 1015 void ar9003_hw_attach_ops(struct ath_hw *ah); 1016 1017 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); 1018 /* 1019 * ANI work can be shared between all families but a next 1020 * generation implementation of ANI will be used only for AR9003 only 1021 * for now as the other families still need to be tested with the same 1022 * next generation ANI. Feel free to start testing it though for the 1023 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani. 1024 */ 1025 extern int modparam_force_new_ani; 1026 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); 1027 void ath9k_hw_proc_mib_event(struct ath_hw *ah); 1028 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); 1029 1030 #define ATH_PCIE_CAP_LINK_CTRL 0x70 1031 #define ATH_PCIE_CAP_LINK_L0S 1 1032 #define ATH_PCIE_CAP_LINK_L1 2 1033 1034 #define ATH9K_CLOCK_RATE_CCK 22 1035 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 1036 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 1037 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 1038 1039 #endif 1040