hw.c (4598702d1b3e0b6aa6694f4c786313a999afbdc9) hw.c (990de2b2e48ac377fb40842a9b04fd940ba78e1b)
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

--- 1515 unchanged lines hidden (view full) ---

1524 if (!(gpio_mask & 1))
1525 continue;
1526
1527 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1528 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1529 }
1530}
1531
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

--- 1515 unchanged lines hidden (view full) ---

1524 if (!(gpio_mask & 1))
1525 continue;
1526
1527 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1528 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1529 }
1530}
1531
1532static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1533 int *hang_state, int *hang_pos)
1534{
1535 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1536 u32 chain_state, dcs_pos, i;
1537
1538 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1539 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1540 for (i = 0; i < 3; i++) {
1541 if (chain_state == dcu_chain_state[i]) {
1542 *hang_state = chain_state;
1543 *hang_pos = dcs_pos;
1544 return true;
1545 }
1546 }
1547 }
1548 return false;
1549}
1550
1551#define DCU_COMPLETE_STATE 1
1552#define DCU_COMPLETE_STATE_MASK 0x3
1553#define NUM_STATUS_READS 50
1554static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1555{
1556 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1557 u32 i, hang_pos, hang_state, num_state = 6;
1558
1559 comp_state = REG_READ(ah, AR_DMADBG_6);
1560
1561 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1562 ath_dbg(ath9k_hw_common(ah), RESET,
1563 "MAC Hang signature not found at DCU complete\n");
1564 return false;
1565 }
1566
1567 chain_state = REG_READ(ah, dcs_reg);
1568 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1569 goto hang_check_iter;
1570
1571 dcs_reg = AR_DMADBG_5;
1572 num_state = 4;
1573 chain_state = REG_READ(ah, dcs_reg);
1574 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1575 goto hang_check_iter;
1576
1577 ath_dbg(ath9k_hw_common(ah), RESET,
1578 "MAC Hang signature 1 not found\n");
1579 return false;
1580
1581hang_check_iter:
1582 ath_dbg(ath9k_hw_common(ah), RESET,
1583 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1584 chain_state, comp_state, hang_state, hang_pos);
1585
1586 for (i = 0; i < NUM_STATUS_READS; i++) {
1587 chain_state = REG_READ(ah, dcs_reg);
1588 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1589 comp_state = REG_READ(ah, AR_DMADBG_6);
1590
1591 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1592 DCU_COMPLETE_STATE) ||
1593 (chain_state != hang_state))
1594 return false;
1595 }
1596
1597 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1598
1599 return true;
1600}
1601
1602void ath9k_hw_check_nav(struct ath_hw *ah)
1603{
1604 struct ath_common *common = ath9k_hw_common(ah);
1605 u32 val;
1606
1607 val = REG_READ(ah, AR_NAV);
1608 if (val != 0xdeadbeef && val > 0x7fff) {
1609 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);

--- 1592 unchanged lines hidden --- 		1532void ath9k_hw_check_nav(struct ath_hw *ah)
1533{
1534 struct ath_common *common = ath9k_hw_common(ah);
1535 u32 val;
1536
1537 val = REG_READ(ah, AR_NAV);
1538 if (val != 0xdeadbeef && val > 0x7fff) {
1539 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);

--- 1592 unchanged lines hidden ---