hw.c (19eddca67628e5fb722e4ebbbba8c307a884d0e8) hw.c (8fbff4b838c53945d6baeafe609c627000f85cd6)
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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1269
1270static int ath9k_hw_process_ini(struct ath_hw *ah,
1271 struct ath9k_channel *chan,
1272 enum ath9k_ht_macmode macmode)
1273{
1274 int i, regWrites = 0;
1275 struct ieee80211_channel *channel = chan->chan;
1276 u32 modesIndex, freqIndex;
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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1269
1270static int ath9k_hw_process_ini(struct ath_hw *ah,
1271 struct ath9k_channel *chan,
1272 enum ath9k_ht_macmode macmode)
1273{
1274 int i, regWrites = 0;
1275 struct ieee80211_channel *channel = chan->chan;
1276 u32 modesIndex, freqIndex;
1277 int status;
1278
1279 switch (chan->chanmode) {
1280 case CHANNEL_A:
1281 case CHANNEL_A_HT20:
1282 modesIndex = 1;
1283 freqIndex = 1;
1284 break;
1285 case CHANNEL_A_HT40PLUS:

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1371
1372 ath9k_hw_override_ini(ah, chan);
1373 ath9k_hw_set_regs(ah, chan, macmode);
1374 ath9k_hw_init_chain_masks(ah);
1375
1376 if (OLC_FOR_AR9280_20_LATER)
1377 ath9k_olc_init(ah);
1378
1277
1278 switch (chan->chanmode) {
1279 case CHANNEL_A:
1280 case CHANNEL_A_HT20:
1281 modesIndex = 1;
1282 freqIndex = 1;
1283 break;
1284 case CHANNEL_A_HT40PLUS:

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1370
1371 ath9k_hw_override_ini(ah, chan);
1372 ath9k_hw_set_regs(ah, chan, macmode);
1373 ath9k_hw_init_chain_masks(ah);
1374
1375 if (OLC_FOR_AR9280_20_LATER)
1376 ath9k_olc_init(ah);
1377
1379 status = ah->eep_ops->set_txpower(ah, chan,
1380 ath9k_regd_get_ctl(&ah->regulatory, chan),
1381 channel->max_antenna_gain * 2,
1382 channel->max_power * 2,
1383 min((u32) MAX_RATE_POWER,
1384 (u32) ah->regulatory.power_limit));
1385 if (status != 0) {
1386 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1387 "Error initializing transmit power\n");
1388 return -EIO;
1389 }
1378 ah->eep_ops->set_txpower(ah, chan,
1379 ath9k_regd_get_ctl(&ah->regulatory, chan),
1380 channel->max_antenna_gain * 2,
1381 channel->max_power * 2,
1382 min((u32) MAX_RATE_POWER,
1383 (u32) ah->regulatory.power_limit));
1390
1391 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1392 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1393 "ar5416SetRfRegs failed\n");
1394 return -EIO;
1395 }
1396
1397 return 0;

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1696 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1697 "Could not kill baseband RX\n");
1698 return false;
1699 }
1700
1701 ath9k_hw_set_regs(ah, chan, macmode);
1702
1703 if (AR_SREV_9280_10_OR_LATER(ah)) {
1384
1385 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1386 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1387 "ar5416SetRfRegs failed\n");
1388 return -EIO;
1389 }
1390
1391 return 0;

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1690 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1691 "Could not kill baseband RX\n");
1692 return false;
1693 }
1694
1695 ath9k_hw_set_regs(ah, chan, macmode);
1696
1697 if (AR_SREV_9280_10_OR_LATER(ah)) {
1704 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1705 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1706 "Failed to set channel\n");
1707 return false;
1708 }
1698 ath9k_hw_ar9280_set_channel(ah, chan);
1709 } else {
1710 if (!(ath9k_hw_set_channel(ah, chan))) {
1711 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1712 "Failed to set channel\n");
1713 return false;
1714 }
1715 }
1716
1699 } else {
1700 if (!(ath9k_hw_set_channel(ah, chan))) {
1701 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1702 "Failed to set channel\n");
1703 return false;
1704 }
1705 }
1706
1717 if (ah->eep_ops->set_txpower(ah, chan,
1707 ah->eep_ops->set_txpower(ah, chan,
1718 ath9k_regd_get_ctl(&ah->regulatory, chan),
1719 channel->max_antenna_gain * 2,
1720 channel->max_power * 2,
1721 min((u32) MAX_RATE_POWER,
1708 ath9k_regd_get_ctl(&ah->regulatory, chan),
1709 channel->max_antenna_gain * 2,
1710 channel->max_power * 2,
1711 min((u32) MAX_RATE_POWER,
1722 (u32) ah->regulatory.power_limit)) != 0) {
1723 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1724 "Error initializing transmit power\n");
1725 return false;
1726 }
1712 (u32) ah->regulatory.power_limit));
1727
1728 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1729 if (IS_CHAN_B(chan))
1730 synthDelay = (4 * synthDelay) / 22;
1731 else
1732 synthDelay /= 10;
1733
1734 udelay(synthDelay + BASE_ACTIVATE_DELAY);

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2306 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2307 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2308 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2309
2310 REG_WRITE(ah, AR_ISR, ~0);
2311
2312 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2313
1713
1714 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1715 if (IS_CHAN_B(chan))
1716 synthDelay = (4 * synthDelay) / 22;
1717 else
1718 synthDelay /= 10;
1719
1720 udelay(synthDelay + BASE_ACTIVATE_DELAY);

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2292 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2293 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2294 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2295
2296 REG_WRITE(ah, AR_ISR, ~0);
2297
2298 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2299
2314 if (AR_SREV_9280_10_OR_LATER(ah)) {
2315 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2316 return -EIO;
2317 } else {
2300 if (AR_SREV_9280_10_OR_LATER(ah))
2301 ath9k_hw_ar9280_set_channel(ah, chan);
2302 else
2318 if (!(ath9k_hw_set_channel(ah, chan)))
2319 return -EIO;
2303 if (!(ath9k_hw_set_channel(ah, chan)))
2304 return -EIO;
2320 }
2321
2322 for (i = 0; i < AR_NUM_DCU; i++)
2323 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2324
2325 ah->intr_txqs = 0;
2326 for (i = 0; i < ah->caps.total_queues; i++)
2327 ath9k_hw_resettxqueue(ah, i);
2328

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3743bool ath9k_hw_disable(struct ath_hw *ah)
3744{
3745 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3746 return false;
3747
3748 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3749}
3750
2305
2306 for (i = 0; i < AR_NUM_DCU; i++)
2307 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2308
2309 ah->intr_txqs = 0;
2310 for (i = 0; i < ah->caps.total_queues; i++)
2311 ath9k_hw_resettxqueue(ah, i);
2312

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3727bool ath9k_hw_disable(struct ath_hw *ah)
3728{
3729 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3730 return false;
3731
3732 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3733}
3734
3751bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3735void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3752{
3753 struct ath9k_channel *chan = ah->curchan;
3754 struct ieee80211_channel *channel = chan->chan;
3755
3756 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3757
3736{
3737 struct ath9k_channel *chan = ah->curchan;
3738 struct ieee80211_channel *channel = chan->chan;
3739
3740 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3741
3758 if (ah->eep_ops->set_txpower(ah, chan,
3759 ath9k_regd_get_ctl(&ah->regulatory, chan),
3760 channel->max_antenna_gain * 2,
3761 channel->max_power * 2,
3762 min((u32) MAX_RATE_POWER,
3763 (u32) ah->regulatory.power_limit)) != 0)
3764 return false;
3765
3766 return true;
3742 ah->eep_ops->set_txpower(ah, chan,
3743 ath9k_regd_get_ctl(&ah->regulatory, chan),
3744 channel->max_antenna_gain * 2,
3745 channel->max_power * 2,
3746 min((u32) MAX_RATE_POWER,
3747 (u32) ah->regulatory.power_limit));
3767}
3768
3769void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3770{
3771 memcpy(ah->macaddr, mac, ETH_ALEN);
3772}
3773
3774void ath9k_hw_setopmode(struct ath_hw *ah)

--- 118 unchanged lines hidden --- 		3748}
3749
3750void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3751{
3752 memcpy(ah->macaddr, mac, ETH_ALEN);
3753}
3754
3755void ath9k_hw_setopmode(struct ath_hw *ah)

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