reset.c (418de6d955fa1da0cb4332661a31d21f57e954ab) reset.c (a180a13081708b78d42232c6d922ce3de63f12e0)
1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any

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954 s_seq[i] = ath5k_hw_reg_read(ah,
955 AR5K_QUEUE_DCU_SEQNUM(i));
956
957 } else {
958 s_seq[0] = ath5k_hw_reg_read(ah,
959 AR5K_QUEUE_DCU_SEQNUM(0));
960 }
961
1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any

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954 s_seq[i] = ath5k_hw_reg_read(ah,
955 AR5K_QUEUE_DCU_SEQNUM(i));
956
957 } else {
958 s_seq[0] = ath5k_hw_reg_read(ah,
959 AR5K_QUEUE_DCU_SEQNUM(0));
960 }
961
962 /* TSF accelerates on AR5211 durring reset
962 /* TSF accelerates on AR5211 during reset
963 * As a workaround save it here and restore
964 * it later so that it's back in time after
965 * reset. This way it'll get re-synced on the
966 * next beacon without breaking ad-hoc.
967 *
968 * On AR5212 TSF is almost preserved across a
969 * reset so it stays back in time anyway and
970 * we don't have to save/restore it.

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1075 if (ah->ah_version == AR5K_AR5212 &&
1076 channel->hw_value & CHANNEL_OFDM) {
1077
1078 ret = ath5k_hw_write_ofdm_timings(ah, channel);
1079 if (ret)
1080 return ret;
1081
1082 /* Spur info is available only from EEPROM versions
963 * As a workaround save it here and restore
964 * it later so that it's back in time after
965 * reset. This way it'll get re-synced on the
966 * next beacon without breaking ad-hoc.
967 *
968 * On AR5212 TSF is almost preserved across a
969 * reset so it stays back in time anyway and
970 * we don't have to save/restore it.

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1075 if (ah->ah_version == AR5K_AR5212 &&
1076 channel->hw_value & CHANNEL_OFDM) {
1077
1078 ret = ath5k_hw_write_ofdm_timings(ah, channel);
1079 if (ret)
1080 return ret;
1081
1082 /* Spur info is available only from EEPROM versions
1083 * bigger than 5.3 but but the EEPOM routines will use
1083 * greater than 5.3, but the EEPROM routines will use
1084 * static values for older versions */
1085 if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
1086 ath5k_hw_set_spur_mitigation_filter(ah,
1087 channel);
1088 }
1089
1090 /*Enable/disable 802.11b mode on 5111
1091 (enable 2111 frequency converter + CCK)*/

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1168 /* Clear any pending interrupts
1169 * PISR/SISR Not available on 5210 */
1170 if (ah->ah_version != AR5K_AR5210)
1171 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
1172
1173 /* Set RSSI/BRSSI thresholds
1174 *
1175 * Note: If we decide to set this value
1084 * static values for older versions */
1085 if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
1086 ath5k_hw_set_spur_mitigation_filter(ah,
1087 channel);
1088 }
1089
1090 /*Enable/disable 802.11b mode on 5111
1091 (enable 2111 frequency converter + CCK)*/

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1168 /* Clear any pending interrupts
1169 * PISR/SISR Not available on 5210 */
1170 if (ah->ah_version != AR5K_AR5210)
1171 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
1172
1173 /* Set RSSI/BRSSI thresholds
1174 *
1175 * Note: If we decide to set this value
1176 * dynamicaly, have in mind that when AR5K_RSSI_THR
1177 * register is read it might return 0x40 if we haven't
1178 * wrote anything to it plus BMISS RSSI threshold is zeroed.
1176 * dynamically, keep in mind that when AR5K_RSSI_THR
1177 * register is read, it might return 0x40 if we haven't
1178 * written anything to it. Also, BMISS RSSI threshold is zeroed.
1179 * So doing a save/restore procedure here isn't the right
1179 * So doing a save/restore procedure here isn't the right
1180 * choice. Instead store it on ath5k_hw */
1180 * choice. Instead, store it in ath5k_hw */
1181 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
1182 AR5K_TUNE_BMISS_THRES <<
1183 AR5K_RSSI_THR_BMISS_S),
1184 AR5K_RSSI_THR);
1185
1186 /* MIC QoS support */
1187 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
1188 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);

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1230
1231 udelay(100 + (2 * delay));
1232 } else {
1233 mdelay(1);
1234 }
1235
1236 /*
1237 * Perform ADC test to see if baseband is ready
1181 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
1182 AR5K_TUNE_BMISS_THRES <<
1183 AR5K_RSSI_THR_BMISS_S),
1184 AR5K_RSSI_THR);
1185
1186 /* MIC QoS support */
1187 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
1188 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);

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1230
1231 udelay(100 + (2 * delay));
1232 } else {
1233 mdelay(1);
1234 }
1235
1236 /*
1237 * Perform ADC test to see if baseband is ready
1238 * Set tx hold and check adc test register
1238 * Set TX hold and check ADC test register
1239 */
1240 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
1241 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
1242 for (i = 0; i <= 20; i++) {
1243 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
1244 break;
1245 udelay(200);
1246 }
1247 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
1248
1249 /*
1250 * Start automatic gain control calibration
1251 *
1252 * During AGC calibration RX path is re-routed to
1253 * a power detector so we don't receive anything.
1254 *
1255 * This method is used to calibrate some static offsets
1256 * used together with on-the fly I/Q calibration (the
1239 */
1240 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
1241 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
1242 for (i = 0; i <= 20; i++) {
1243 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
1244 break;
1245 udelay(200);
1246 }
1247 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
1248
1249 /*
1250 * Start automatic gain control calibration
1251 *
1252 * During AGC calibration RX path is re-routed to
1253 * a power detector so we don't receive anything.
1254 *
1255 * This method is used to calibrate some static offsets
1256 * used together with on-the fly I/Q calibration (the
1257 * one performed via ath5k_hw_phy_calibrate), that doesn't
1257 * one performed via ath5k_hw_phy_calibrate), which doesn't
1258 * interrupt rx path.
1259 *
1260 * While rx path is re-routed to the power detector we also
1258 * interrupt rx path.
1259 *
1260 * While rx path is re-routed to the power detector we also
1261 * start a noise floor calibration, to measure the
1261 * start a noise floor calibration to measure the
1262 * card's noise floor (the noise we measure when we are not
1262 * card's noise floor (the noise we measure when we are not
1263 * transmiting or receiving anything).
1263 * transmitting or receiving anything).
1264 *
1264 *
1265 * If we are in a noisy environment AGC calibration may time
1265 * If we are in a noisy environment, AGC calibration may time
1266 * out and/or noise floor calibration might timeout.
1267 */
1268 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1269 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
1270
1271 /* At the same time start I/Q calibration for QAM constellation
1272 * -no need for CCK- */
1273 ah->ah_calibration = false;

--- 88 unchanged lines hidden --- 		1266 * out and/or noise floor calibration might timeout.
1267 */
1268 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1269 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
1270
1271 /* At the same time start I/Q calibration for QAM constellation
1272 * -no need for CCK- */
1273 ah->ah_calibration = false;

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