1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu> 5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 * 20 */ 21 22 /*****************************\ 23 Reset functions and helpers 24 \*****************************/ 25 26 #include <asm/unaligned.h> 27 28 #include <linux/pci.h> /* To determine if a card is pci-e */ 29 #include <linux/log2.h> 30 #include "ath5k.h" 31 #include "reg.h" 32 #include "base.h" 33 #include "debug.h" 34 35 /* 36 * Check if a register write has been completed 37 */ 38 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, 39 bool is_set) 40 { 41 int i; 42 u32 data; 43 44 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { 45 data = ath5k_hw_reg_read(ah, reg); 46 if (is_set && (data & flag)) 47 break; 48 else if ((data & flag) == val) 49 break; 50 udelay(15); 51 } 52 53 return (i <= 0) ? -EAGAIN : 0; 54 } 55 56 /** 57 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 58 * 59 * @ah: the &struct ath5k_hw 60 * @channel: the currently set channel upon reset 61 * 62 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM 63 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_reset(). 64 * 65 * Since delta slope is floating point we split it on its exponent and 66 * mantissa and provide these values on hw. 67 * 68 * For more infos i think this patent is related 69 * http://www.freepatentsonline.com/7184495.html 70 */ 71 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, 72 struct ieee80211_channel *channel) 73 { 74 /* Get exponent and mantissa and set it */ 75 u32 coef_scaled, coef_exp, coef_man, 76 ds_coef_exp, ds_coef_man, clock; 77 78 BUG_ON(!(ah->ah_version == AR5K_AR5212) || 79 !(channel->hw_value & CHANNEL_OFDM)); 80 81 /* Get coefficient 82 * ALGO: coef = (5 * clock / carrier_freq) / 2 83 * we scale coef by shifting clock value by 24 for 84 * better precision since we use integers */ 85 /* TODO: Half/quarter rate */ 86 clock = (channel->hw_value & CHANNEL_TURBO) ? 80 : 40; 87 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq; 88 89 /* Get exponent 90 * ALGO: coef_exp = 14 - highest set bit position */ 91 coef_exp = ilog2(coef_scaled); 92 93 /* Doesn't make sense if it's zero*/ 94 if (!coef_scaled || !coef_exp) 95 return -EINVAL; 96 97 /* Note: we've shifted coef_scaled by 24 */ 98 coef_exp = 14 - (coef_exp - 24); 99 100 101 /* Get mantissa (significant digits) 102 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */ 103 coef_man = coef_scaled + 104 (1 << (24 - coef_exp - 1)); 105 106 /* Calculate delta slope coefficient exponent 107 * and mantissa (remove scaling) and set them on hw */ 108 ds_coef_man = coef_man >> (24 - coef_exp); 109 ds_coef_exp = coef_exp - 16; 110 111 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 112 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); 113 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 114 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); 115 116 return 0; 117 } 118 119 120 /* 121 * index into rates for control rates, we can set it up like this because 122 * this is only used for AR5212 and we know it supports G mode 123 */ 124 static const unsigned int control_rates[] = 125 { 0, 1, 1, 1, 4, 4, 6, 6, 8, 8, 8, 8 }; 126 127 /** 128 * ath5k_hw_write_rate_duration - fill rate code to duration table 129 * 130 * @ah: the &struct ath5k_hw 131 * @mode: one of enum ath5k_driver_mode 132 * 133 * Write the rate code to duration table upon hw reset. This is a helper for 134 * ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout on 135 * the hardware, based on current mode, for each rate. The rates which are 136 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have 137 * different rate code so we write their value twice (one for long preample 138 * and one for short). 139 * 140 * Note: Band doesn't matter here, if we set the values for OFDM it works 141 * on both a and g modes. So all we have to do is set values for all g rates 142 * that include all OFDM and CCK rates. If we operate in turbo or xr/half/ 143 * quarter rate mode, we need to use another set of bitrates (that's why we 144 * need the mode parameter) but we don't handle these proprietary modes yet. 145 */ 146 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah, 147 unsigned int mode) 148 { 149 struct ath5k_softc *sc = ah->ah_sc; 150 struct ieee80211_rate *rate; 151 unsigned int i; 152 153 /* Write rate duration table */ 154 for (i = 0; i < sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates; i++) { 155 u32 reg; 156 u16 tx_time; 157 158 rate = &sc->sbands[IEEE80211_BAND_2GHZ].bitrates[control_rates[i]]; 159 160 /* Set ACK timeout */ 161 reg = AR5K_RATE_DUR(rate->hw_value); 162 163 /* An ACK frame consists of 10 bytes. If you add the FCS, 164 * which ieee80211_generic_frame_duration() adds, 165 * its 14 bytes. Note we use the control rate and not the 166 * actual rate for this rate. See mac80211 tx.c 167 * ieee80211_duration() for a brief description of 168 * what rate we should choose to TX ACKs. */ 169 tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw, 170 sc->vif, 10, rate)); 171 172 ath5k_hw_reg_write(ah, tx_time, reg); 173 174 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE)) 175 continue; 176 177 /* 178 * We're not distinguishing short preamble here, 179 * This is true, all we'll get is a longer value here 180 * which is not necessarilly bad. We could use 181 * export ieee80211_frame_duration() but that needs to be 182 * fixed first to be properly used by mac802111 drivers: 183 * 184 * - remove erp stuff and let the routine figure ofdm 185 * erp rates 186 * - remove passing argument ieee80211_local as 187 * drivers don't have access to it 188 * - move drivers using ieee80211_generic_frame_duration() 189 * to this 190 */ 191 ath5k_hw_reg_write(ah, tx_time, 192 reg + (AR5K_SET_SHORT_PREAMBLE << 2)); 193 } 194 } 195 196 /* 197 * Reset chipset 198 */ 199 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val) 200 { 201 int ret; 202 u32 mask = val ? val : ~0U; 203 204 /* Read-and-clear RX Descriptor Pointer*/ 205 ath5k_hw_reg_read(ah, AR5K_RXDP); 206 207 /* 208 * Reset the device and wait until success 209 */ 210 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL); 211 212 /* Wait at least 128 PCI clocks */ 213 udelay(15); 214 215 if (ah->ah_version == AR5K_AR5210) { 216 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA 217 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY; 218 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA 219 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY; 220 } else { 221 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; 222 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; 223 } 224 225 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false); 226 227 /* 228 * Reset configuration register (for hw byte-swap). Note that this 229 * is only set for big endian. We do the necessary magic in 230 * AR5K_INIT_CFG. 231 */ 232 if ((val & AR5K_RESET_CTL_PCU) == 0) 233 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG); 234 235 return ret; 236 } 237 238 /* 239 * Sleep control 240 */ 241 static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, 242 bool set_chip, u16 sleep_duration) 243 { 244 unsigned int i; 245 u32 staid, data; 246 247 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1); 248 249 switch (mode) { 250 case AR5K_PM_AUTO: 251 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA; 252 /* fallthrough */ 253 case AR5K_PM_NETWORK_SLEEP: 254 if (set_chip) 255 ath5k_hw_reg_write(ah, 256 AR5K_SLEEP_CTL_SLE_ALLOW | 257 sleep_duration, 258 AR5K_SLEEP_CTL); 259 260 staid |= AR5K_STA_ID1_PWR_SV; 261 break; 262 263 case AR5K_PM_FULL_SLEEP: 264 if (set_chip) 265 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP, 266 AR5K_SLEEP_CTL); 267 268 staid |= AR5K_STA_ID1_PWR_SV; 269 break; 270 271 case AR5K_PM_AWAKE: 272 273 staid &= ~AR5K_STA_ID1_PWR_SV; 274 275 if (!set_chip) 276 goto commit; 277 278 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL); 279 280 /* If card is down we 'll get 0xffff... so we 281 * need to clean this up before we write the register 282 */ 283 if (data & 0xffc00000) 284 data = 0; 285 else 286 /* Preserve sleep duration etc */ 287 data = data & ~AR5K_SLEEP_CTL_SLE; 288 289 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE, 290 AR5K_SLEEP_CTL); 291 udelay(15); 292 293 for (i = 200; i > 0; i--) { 294 /* Check if the chip did wake up */ 295 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) & 296 AR5K_PCICFG_SPWR_DN) == 0) 297 break; 298 299 /* Wait a bit and retry */ 300 udelay(50); 301 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE, 302 AR5K_SLEEP_CTL); 303 } 304 305 /* Fail if the chip didn't wake up */ 306 if (i == 0) 307 return -EIO; 308 309 break; 310 311 default: 312 return -EINVAL; 313 } 314 315 commit: 316 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1); 317 318 return 0; 319 } 320 321 /* 322 * Put device on hold 323 * 324 * Put MAC and Baseband on warm reset and 325 * keep that state (don't clean sleep control 326 * register). After this MAC and Baseband are 327 * disabled and a full reset is needed to come 328 * back. This way we save as much power as possible 329 * without puting the card on full sleep. 330 */ 331 int ath5k_hw_on_hold(struct ath5k_hw *ah) 332 { 333 struct pci_dev *pdev = ah->ah_sc->pdev; 334 u32 bus_flags; 335 int ret; 336 337 /* Make sure device is awake */ 338 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 339 if (ret) { 340 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n"); 341 return ret; 342 } 343 344 /* 345 * Put chipset on warm reset... 346 * 347 * Note: puting PCI core on warm reset on PCI-E cards 348 * results card to hang and always return 0xffff... so 349 * we ingore that flag for PCI-E cards. On PCI cards 350 * this flag gets cleared after 64 PCI clocks. 351 */ 352 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI; 353 354 if (ah->ah_version == AR5K_AR5210) { 355 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 356 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA | 357 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI); 358 mdelay(2); 359 } else { 360 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 361 AR5K_RESET_CTL_BASEBAND | bus_flags); 362 } 363 364 if (ret) { 365 ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n"); 366 return -EIO; 367 } 368 369 /* ...wakeup again!*/ 370 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 371 if (ret) { 372 ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n"); 373 return ret; 374 } 375 376 return ret; 377 } 378 379 /* 380 * Bring up MAC + PHY Chips and program PLL 381 * TODO: Half/Quarter rate support 382 */ 383 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial) 384 { 385 struct pci_dev *pdev = ah->ah_sc->pdev; 386 u32 turbo, mode, clock, bus_flags; 387 int ret; 388 389 turbo = 0; 390 mode = 0; 391 clock = 0; 392 393 /* Wakeup the device */ 394 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 395 if (ret) { 396 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n"); 397 return ret; 398 } 399 400 /* 401 * Put chipset on warm reset... 402 * 403 * Note: puting PCI core on warm reset on PCI-E cards 404 * results card to hang and always return 0xffff... so 405 * we ingore that flag for PCI-E cards. On PCI cards 406 * this flag gets cleared after 64 PCI clocks. 407 */ 408 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI; 409 410 if (ah->ah_version == AR5K_AR5210) { 411 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 412 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA | 413 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI); 414 mdelay(2); 415 } else { 416 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 417 AR5K_RESET_CTL_BASEBAND | bus_flags); 418 } 419 420 if (ret) { 421 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n"); 422 return -EIO; 423 } 424 425 /* ...wakeup again!...*/ 426 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 427 if (ret) { 428 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n"); 429 return ret; 430 } 431 432 /* ...clear reset control register and pull device out of 433 * warm reset */ 434 if (ath5k_hw_nic_reset(ah, 0)) { 435 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n"); 436 return -EIO; 437 } 438 439 /* On initialization skip PLL programming since we don't have 440 * a channel / mode set yet */ 441 if (initial) 442 return 0; 443 444 if (ah->ah_version != AR5K_AR5210) { 445 /* 446 * Get channel mode flags 447 */ 448 449 if (ah->ah_radio >= AR5K_RF5112) { 450 mode = AR5K_PHY_MODE_RAD_RF5112; 451 clock = AR5K_PHY_PLL_RF5112; 452 } else { 453 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/ 454 clock = AR5K_PHY_PLL_RF5111; /*Zero*/ 455 } 456 457 if (flags & CHANNEL_2GHZ) { 458 mode |= AR5K_PHY_MODE_FREQ_2GHZ; 459 clock |= AR5K_PHY_PLL_44MHZ; 460 461 if (flags & CHANNEL_CCK) { 462 mode |= AR5K_PHY_MODE_MOD_CCK; 463 } else if (flags & CHANNEL_OFDM) { 464 /* XXX Dynamic OFDM/CCK is not supported by the 465 * AR5211 so we set MOD_OFDM for plain g (no 466 * CCK headers) operation. We need to test 467 * this, 5211 might support ofdm-only g after 468 * all, there are also initial register values 469 * in the code for g mode (see initvals.c). */ 470 if (ah->ah_version == AR5K_AR5211) 471 mode |= AR5K_PHY_MODE_MOD_OFDM; 472 else 473 mode |= AR5K_PHY_MODE_MOD_DYN; 474 } else { 475 ATH5K_ERR(ah->ah_sc, 476 "invalid radio modulation mode\n"); 477 return -EINVAL; 478 } 479 } else if (flags & CHANNEL_5GHZ) { 480 mode |= AR5K_PHY_MODE_FREQ_5GHZ; 481 482 if (ah->ah_radio == AR5K_RF5413) 483 clock = AR5K_PHY_PLL_40MHZ_5413; 484 else 485 clock |= AR5K_PHY_PLL_40MHZ; 486 487 if (flags & CHANNEL_OFDM) 488 mode |= AR5K_PHY_MODE_MOD_OFDM; 489 else { 490 ATH5K_ERR(ah->ah_sc, 491 "invalid radio modulation mode\n"); 492 return -EINVAL; 493 } 494 } else { 495 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n"); 496 return -EINVAL; 497 } 498 499 if (flags & CHANNEL_TURBO) 500 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT; 501 } else { /* Reset the device */ 502 503 /* ...enable Atheros turbo mode if requested */ 504 if (flags & CHANNEL_TURBO) 505 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE, 506 AR5K_PHY_TURBO); 507 } 508 509 if (ah->ah_version != AR5K_AR5210) { 510 511 /* ...update PLL if needed */ 512 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) { 513 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL); 514 udelay(300); 515 } 516 517 /* ...set the PHY operating mode */ 518 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE); 519 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO); 520 } 521 522 return 0; 523 } 524 525 /* 526 * If there is an external 32KHz crystal available, use it 527 * as ref. clock instead of 32/40MHz clock and baseband clocks 528 * to save power during sleep or restore normal 32/40MHz 529 * operation. 530 * 531 * XXX: When operating on 32KHz certain PHY registers (27 - 31, 532 * 123 - 127) require delay on access. 533 */ 534 static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable) 535 { 536 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 537 u32 scal, spending, usec32; 538 539 /* Only set 32KHz settings if we have an external 540 * 32KHz crystal present */ 541 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) || 542 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) && 543 enable) { 544 545 /* 1 usec/cycle */ 546 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1); 547 /* Set up tsf increment on each cycle */ 548 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61); 549 550 /* Set baseband sleep control registers 551 * and sleep control rate */ 552 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR); 553 554 if ((ah->ah_radio == AR5K_RF5112) || 555 (ah->ah_radio == AR5K_RF5413) || 556 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 557 spending = 0x14; 558 else 559 spending = 0x18; 560 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING); 561 562 if ((ah->ah_radio == AR5K_RF5112) || 563 (ah->ah_radio == AR5K_RF5413) || 564 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) { 565 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT); 566 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL); 567 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK); 568 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY); 569 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG, 570 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02); 571 } else { 572 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT); 573 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL); 574 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK); 575 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY); 576 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG, 577 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03); 578 } 579 580 /* Enable sleep clock operation */ 581 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, 582 AR5K_PCICFG_SLEEP_CLOCK_EN); 583 584 } else { 585 586 /* Disable sleep clock operation and 587 * restore default parameters */ 588 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG, 589 AR5K_PCICFG_SLEEP_CLOCK_EN); 590 591 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG, 592 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0); 593 594 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR); 595 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT); 596 597 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)) 598 scal = AR5K_PHY_SCAL_32MHZ_2417; 599 else if (ee->ee_is_hb63) 600 scal = AR5K_PHY_SCAL_32MHZ_HB63; 601 else 602 scal = AR5K_PHY_SCAL_32MHZ; 603 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL); 604 605 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK); 606 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY); 607 608 if ((ah->ah_radio == AR5K_RF5112) || 609 (ah->ah_radio == AR5K_RF5413) || 610 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 611 spending = 0x14; 612 else 613 spending = 0x18; 614 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING); 615 616 if ((ah->ah_radio == AR5K_RF5112) || 617 (ah->ah_radio == AR5K_RF5413)) 618 usec32 = 39; 619 else 620 usec32 = 31; 621 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, usec32); 622 623 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1); 624 } 625 } 626 627 /* TODO: Half/Quarter rate */ 628 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah, 629 struct ieee80211_channel *channel) 630 { 631 if (ah->ah_version == AR5K_AR5212 && 632 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 633 634 /* Setup ADC control */ 635 ath5k_hw_reg_write(ah, 636 (AR5K_REG_SM(2, 637 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) | 638 AR5K_REG_SM(2, 639 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) | 640 AR5K_PHY_ADC_CTL_PWD_DAC_OFF | 641 AR5K_PHY_ADC_CTL_PWD_ADC_OFF), 642 AR5K_PHY_ADC_CTL); 643 644 645 646 /* Disable barker RSSI threshold */ 647 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL, 648 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR); 649 650 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL, 651 AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2); 652 653 /* Set the mute mask */ 654 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK); 655 } 656 657 /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */ 658 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B) 659 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH); 660 661 /* Enable DCU double buffering */ 662 if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B) 663 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 664 AR5K_TXCFG_DCU_DBL_BUF_DIS); 665 666 /* Set DAC/ADC delays */ 667 if (ah->ah_version == AR5K_AR5212) { 668 u32 scal; 669 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 670 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)) 671 scal = AR5K_PHY_SCAL_32MHZ_2417; 672 else if (ee->ee_is_hb63) 673 scal = AR5K_PHY_SCAL_32MHZ_HB63; 674 else 675 scal = AR5K_PHY_SCAL_32MHZ; 676 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL); 677 } 678 679 /* Set fast ADC */ 680 if ((ah->ah_radio == AR5K_RF5413) || 681 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) { 682 u32 fast_adc = true; 683 684 if (channel->center_freq == 2462 || 685 channel->center_freq == 2467) 686 fast_adc = 0; 687 688 /* Only update if needed */ 689 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc) 690 ath5k_hw_reg_write(ah, fast_adc, 691 AR5K_PHY_FAST_ADC); 692 } 693 694 /* Fix for first revision of the RF5112 RF chipset */ 695 if (ah->ah_radio == AR5K_RF5112 && 696 ah->ah_radio_5ghz_revision < 697 AR5K_SREV_RAD_5112A) { 698 u32 data; 699 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD, 700 AR5K_PHY_CCKTXCTL); 701 if (channel->hw_value & CHANNEL_5GHZ) 702 data = 0xffb81020; 703 else 704 data = 0xffb80d20; 705 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL); 706 } 707 708 if (ah->ah_mac_srev < AR5K_SREV_AR5211) { 709 u32 usec_reg; 710 /* 5311 has different tx/rx latency masks 711 * from 5211, since we deal 5311 the same 712 * as 5211 when setting initvals, shift 713 * values here to their proper locations */ 714 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211); 715 ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 | 716 AR5K_USEC_32 | 717 AR5K_USEC_TX_LATENCY_5211 | 718 AR5K_REG_SM(29, 719 AR5K_USEC_RX_LATENCY_5210)), 720 AR5K_USEC_5211); 721 /* Clear QCU/DCU clock gating register */ 722 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT); 723 /* Set DAC/ADC delays */ 724 ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL); 725 /* Enable PCU FIFO corruption ECO */ 726 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211, 727 AR5K_DIAG_SW_ECO_ENABLE); 728 } 729 } 730 731 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah, 732 struct ieee80211_channel *channel, u8 ee_mode) 733 { 734 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 735 s16 cck_ofdm_pwr_delta; 736 737 /* Adjust power delta for channel 14 */ 738 if (channel->center_freq == 2484) 739 cck_ofdm_pwr_delta = 740 ((ee->ee_cck_ofdm_power_delta - 741 ee->ee_scaled_cck_delta) * 2) / 10; 742 else 743 cck_ofdm_pwr_delta = 744 (ee->ee_cck_ofdm_power_delta * 2) / 10; 745 746 /* Set CCK to OFDM power delta on tx power 747 * adjustment register */ 748 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 749 if (channel->hw_value == CHANNEL_G) 750 ath5k_hw_reg_write(ah, 751 AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1), 752 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) | 753 AR5K_REG_SM((cck_ofdm_pwr_delta * -1), 754 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX), 755 AR5K_PHY_TX_PWR_ADJ); 756 else 757 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ); 758 } else { 759 /* For older revs we scale power on sw during tx power 760 * setup */ 761 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta; 762 ah->ah_txpower.txp_cck_ofdm_gainf_delta = 763 ee->ee_cck_ofdm_gain_delta; 764 } 765 766 /* XXX: necessary here? is called from ath5k_hw_set_antenna_mode() 767 * too */ 768 ath5k_hw_set_antenna_switch(ah, ee_mode); 769 770 /* Noise floor threshold */ 771 ath5k_hw_reg_write(ah, 772 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]), 773 AR5K_PHY_NFTHRES); 774 775 if ((channel->hw_value & CHANNEL_TURBO) && 776 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) { 777 /* Switch settling time (Turbo) */ 778 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING, 779 AR5K_PHY_SETTLING_SWITCH, 780 ee->ee_switch_settling_turbo[ee_mode]); 781 782 /* Tx/Rx attenuation (Turbo) */ 783 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN, 784 AR5K_PHY_GAIN_TXRX_ATTEN, 785 ee->ee_atn_tx_rx_turbo[ee_mode]); 786 787 /* ADC/PGA desired size (Turbo) */ 788 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 789 AR5K_PHY_DESIRED_SIZE_ADC, 790 ee->ee_adc_desired_size_turbo[ee_mode]); 791 792 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 793 AR5K_PHY_DESIRED_SIZE_PGA, 794 ee->ee_pga_desired_size_turbo[ee_mode]); 795 796 /* Tx/Rx margin (Turbo) */ 797 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ, 798 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, 799 ee->ee_margin_tx_rx_turbo[ee_mode]); 800 801 } else { 802 /* Switch settling time */ 803 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING, 804 AR5K_PHY_SETTLING_SWITCH, 805 ee->ee_switch_settling[ee_mode]); 806 807 /* Tx/Rx attenuation */ 808 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN, 809 AR5K_PHY_GAIN_TXRX_ATTEN, 810 ee->ee_atn_tx_rx[ee_mode]); 811 812 /* ADC/PGA desired size */ 813 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 814 AR5K_PHY_DESIRED_SIZE_ADC, 815 ee->ee_adc_desired_size[ee_mode]); 816 817 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 818 AR5K_PHY_DESIRED_SIZE_PGA, 819 ee->ee_pga_desired_size[ee_mode]); 820 821 /* Tx/Rx margin */ 822 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) 823 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ, 824 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, 825 ee->ee_margin_tx_rx[ee_mode]); 826 } 827 828 /* XPA delays */ 829 ath5k_hw_reg_write(ah, 830 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | 831 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | 832 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | 833 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4); 834 835 /* XLNA delay */ 836 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3, 837 AR5K_PHY_RF_CTL3_TXE2XLNA_ON, 838 ee->ee_tx_end2xlna_enable[ee_mode]); 839 840 /* Thresh64 (ANI) */ 841 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF, 842 AR5K_PHY_NF_THRESH62, 843 ee->ee_thr_62[ee_mode]); 844 845 /* False detect backoff for channels 846 * that have spur noise. Write the new 847 * cyclic power RSSI threshold. */ 848 if (ath5k_hw_chan_has_spur_noise(ah, channel)) 849 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 850 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, 851 AR5K_INIT_CYCRSSI_THR1 + 852 ee->ee_false_detect[ee_mode]); 853 else 854 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 855 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, 856 AR5K_INIT_CYCRSSI_THR1); 857 858 /* I/Q correction (set enable bit last to match HAL sources) */ 859 /* TODO: Per channel i/q infos ? */ 860 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { 861 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, 862 ee->ee_i_cal[ee_mode]); 863 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, 864 ee->ee_q_cal[ee_mode]); 865 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); 866 } 867 868 /* Heavy clipping -disable for now */ 869 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1) 870 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE); 871 } 872 873 /* 874 * Main reset function 875 */ 876 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 877 struct ieee80211_channel *channel, bool change_channel) 878 { 879 struct ath_common *common = ath5k_hw_common(ah); 880 u32 s_seq[10], s_led[3], staid1_flags, tsf_up, tsf_lo; 881 u32 phy_tst1; 882 u8 mode, freq, ee_mode; 883 int i, ret; 884 885 ee_mode = 0; 886 staid1_flags = 0; 887 tsf_up = 0; 888 tsf_lo = 0; 889 freq = 0; 890 mode = 0; 891 892 /* 893 * Save some registers before a reset 894 */ 895 /*DCU/Antenna selection not available on 5210*/ 896 if (ah->ah_version != AR5K_AR5210) { 897 898 switch (channel->hw_value & CHANNEL_MODES) { 899 case CHANNEL_A: 900 mode = AR5K_MODE_11A; 901 freq = AR5K_INI_RFGAIN_5GHZ; 902 ee_mode = AR5K_EEPROM_MODE_11A; 903 break; 904 case CHANNEL_G: 905 mode = AR5K_MODE_11G; 906 freq = AR5K_INI_RFGAIN_2GHZ; 907 ee_mode = AR5K_EEPROM_MODE_11G; 908 break; 909 case CHANNEL_B: 910 mode = AR5K_MODE_11B; 911 freq = AR5K_INI_RFGAIN_2GHZ; 912 ee_mode = AR5K_EEPROM_MODE_11B; 913 break; 914 case CHANNEL_T: 915 mode = AR5K_MODE_11A_TURBO; 916 freq = AR5K_INI_RFGAIN_5GHZ; 917 ee_mode = AR5K_EEPROM_MODE_11A; 918 break; 919 case CHANNEL_TG: 920 if (ah->ah_version == AR5K_AR5211) { 921 ATH5K_ERR(ah->ah_sc, 922 "TurboG mode not available on 5211"); 923 return -EINVAL; 924 } 925 mode = AR5K_MODE_11G_TURBO; 926 freq = AR5K_INI_RFGAIN_2GHZ; 927 ee_mode = AR5K_EEPROM_MODE_11G; 928 break; 929 case CHANNEL_XR: 930 if (ah->ah_version == AR5K_AR5211) { 931 ATH5K_ERR(ah->ah_sc, 932 "XR mode not available on 5211"); 933 return -EINVAL; 934 } 935 mode = AR5K_MODE_XR; 936 freq = AR5K_INI_RFGAIN_5GHZ; 937 ee_mode = AR5K_EEPROM_MODE_11A; 938 break; 939 default: 940 ATH5K_ERR(ah->ah_sc, 941 "invalid channel: %d\n", channel->center_freq); 942 return -EINVAL; 943 } 944 945 if (change_channel) { 946 /* 947 * Save frame sequence count 948 * For revs. after Oahu, only save 949 * seq num for DCU 0 (Global seq num) 950 */ 951 if (ah->ah_mac_srev < AR5K_SREV_AR5211) { 952 953 for (i = 0; i < 10; i++) 954 s_seq[i] = ath5k_hw_reg_read(ah, 955 AR5K_QUEUE_DCU_SEQNUM(i)); 956 957 } else { 958 s_seq[0] = ath5k_hw_reg_read(ah, 959 AR5K_QUEUE_DCU_SEQNUM(0)); 960 } 961 962 /* TSF accelerates on AR5211 durring reset 963 * As a workaround save it here and restore 964 * it later so that it's back in time after 965 * reset. This way it'll get re-synced on the 966 * next beacon without breaking ad-hoc. 967 * 968 * On AR5212 TSF is almost preserved across a 969 * reset so it stays back in time anyway and 970 * we don't have to save/restore it. 971 * 972 * XXX: Since this breaks power saving we have 973 * to disable power saving until we receive the 974 * next beacon, so we can resync beacon timers */ 975 if (ah->ah_version == AR5K_AR5211) { 976 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 977 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32); 978 } 979 } 980 981 if (ah->ah_version == AR5K_AR5212) { 982 /* Restore normal 32/40MHz clock operation 983 * to avoid register access delay on certain 984 * PHY registers */ 985 ath5k_hw_set_sleep_clock(ah, false); 986 987 /* Since we are going to write rf buffer 988 * check if we have any pending gain_F 989 * optimization settings */ 990 if (change_channel && ah->ah_rf_banks != NULL) 991 ath5k_hw_gainf_calibrate(ah); 992 } 993 } 994 995 /*GPIOs*/ 996 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & 997 AR5K_PCICFG_LEDSTATE; 998 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR); 999 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO); 1000 1001 /* AR5K_STA_ID1 flags, only preserve antenna 1002 * settings and ack/cts rate mode */ 1003 staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 1004 (AR5K_STA_ID1_DEFAULT_ANTENNA | 1005 AR5K_STA_ID1_DESC_ANTENNA | 1006 AR5K_STA_ID1_RTS_DEF_ANTENNA | 1007 AR5K_STA_ID1_ACKCTS_6MB | 1008 AR5K_STA_ID1_BASE_RATE_11B | 1009 AR5K_STA_ID1_SELFGEN_DEF_ANT); 1010 1011 /* Wakeup the device */ 1012 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false); 1013 if (ret) 1014 return ret; 1015 1016 /* PHY access enable */ 1017 if (ah->ah_mac_srev >= AR5K_SREV_AR5211) 1018 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 1019 else 1020 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40, 1021 AR5K_PHY(0)); 1022 1023 /* Write initial settings */ 1024 ret = ath5k_hw_write_initvals(ah, mode, change_channel); 1025 if (ret) 1026 return ret; 1027 1028 /* 1029 * 5211/5212 Specific 1030 */ 1031 if (ah->ah_version != AR5K_AR5210) { 1032 1033 /* 1034 * Write initial RF gain settings 1035 * This should work for both 5111/5112 1036 */ 1037 ret = ath5k_hw_rfgain_init(ah, freq); 1038 if (ret) 1039 return ret; 1040 1041 mdelay(1); 1042 1043 /* 1044 * Tweak initval settings for revised 1045 * chipsets and add some more config 1046 * bits 1047 */ 1048 ath5k_hw_tweak_initval_settings(ah, channel); 1049 1050 /* 1051 * Set TX power 1052 */ 1053 ret = ath5k_hw_txpower(ah, channel, ee_mode, 1054 ah->ah_txpower.txp_max_pwr / 2); 1055 if (ret) 1056 return ret; 1057 1058 /* Write rate duration table only on AR5212 and if 1059 * virtual interface has already been brought up 1060 * XXX: rethink this after new mode changes to 1061 * mac80211 are integrated */ 1062 if (ah->ah_version == AR5K_AR5212 && 1063 ah->ah_sc->vif != NULL) 1064 ath5k_hw_write_rate_duration(ah, mode); 1065 1066 /* 1067 * Write RF buffer 1068 */ 1069 ret = ath5k_hw_rfregs_init(ah, channel, mode); 1070 if (ret) 1071 return ret; 1072 1073 1074 /* Write OFDM timings on 5212*/ 1075 if (ah->ah_version == AR5K_AR5212 && 1076 channel->hw_value & CHANNEL_OFDM) { 1077 1078 ret = ath5k_hw_write_ofdm_timings(ah, channel); 1079 if (ret) 1080 return ret; 1081 1082 /* Spur info is available only from EEPROM versions 1083 * bigger than 5.3 but but the EEPOM routines will use 1084 * static values for older versions */ 1085 if (ah->ah_mac_srev >= AR5K_SREV_AR5424) 1086 ath5k_hw_set_spur_mitigation_filter(ah, 1087 channel); 1088 } 1089 1090 /*Enable/disable 802.11b mode on 5111 1091 (enable 2111 frequency converter + CCK)*/ 1092 if (ah->ah_radio == AR5K_RF5111) { 1093 if (mode == AR5K_MODE_11B) 1094 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, 1095 AR5K_TXCFG_B_MODE); 1096 else 1097 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 1098 AR5K_TXCFG_B_MODE); 1099 } 1100 1101 /* Commit values from EEPROM */ 1102 ath5k_hw_commit_eeprom_settings(ah, channel, ee_mode); 1103 1104 } else { 1105 /* 1106 * For 5210 we do all initialization using 1107 * initvals, so we don't have to modify 1108 * any settings (5210 also only supports 1109 * a/aturbo modes) 1110 */ 1111 mdelay(1); 1112 /* Disable phy and wait */ 1113 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 1114 mdelay(1); 1115 } 1116 1117 /* 1118 * Restore saved values 1119 */ 1120 1121 /*DCU/Antenna selection not available on 5210*/ 1122 if (ah->ah_version != AR5K_AR5210) { 1123 1124 if (change_channel) { 1125 if (ah->ah_mac_srev < AR5K_SREV_AR5211) { 1126 for (i = 0; i < 10; i++) 1127 ath5k_hw_reg_write(ah, s_seq[i], 1128 AR5K_QUEUE_DCU_SEQNUM(i)); 1129 } else { 1130 ath5k_hw_reg_write(ah, s_seq[0], 1131 AR5K_QUEUE_DCU_SEQNUM(0)); 1132 } 1133 1134 1135 if (ah->ah_version == AR5K_AR5211) { 1136 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32); 1137 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32); 1138 } 1139 } 1140 } 1141 1142 /* Ledstate */ 1143 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]); 1144 1145 /* Gpio settings */ 1146 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR); 1147 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO); 1148 1149 /* Restore sta_id flags and preserve our mac address*/ 1150 ath5k_hw_reg_write(ah, 1151 get_unaligned_le32(common->macaddr), 1152 AR5K_STA_ID0); 1153 ath5k_hw_reg_write(ah, 1154 staid1_flags | get_unaligned_le16(common->macaddr + 4), 1155 AR5K_STA_ID1); 1156 1157 1158 /* 1159 * Configure PCU 1160 */ 1161 1162 /* Restore bssid and bssid mask */ 1163 ath5k_hw_set_bssid(ah); 1164 1165 /* Set PCU config */ 1166 ath5k_hw_set_opmode(ah, op_mode); 1167 1168 /* Clear any pending interrupts 1169 * PISR/SISR Not available on 5210 */ 1170 if (ah->ah_version != AR5K_AR5210) 1171 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR); 1172 1173 /* Set RSSI/BRSSI thresholds 1174 * 1175 * Note: If we decide to set this value 1176 * dynamicaly, have in mind that when AR5K_RSSI_THR 1177 * register is read it might return 0x40 if we haven't 1178 * wrote anything to it plus BMISS RSSI threshold is zeroed. 1179 * So doing a save/restore procedure here isn't the right 1180 * choice. Instead store it on ath5k_hw */ 1181 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES | 1182 AR5K_TUNE_BMISS_THRES << 1183 AR5K_RSSI_THR_BMISS_S), 1184 AR5K_RSSI_THR); 1185 1186 /* MIC QoS support */ 1187 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) { 1188 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL); 1189 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL); 1190 } 1191 1192 /* QoS NOACK Policy */ 1193 if (ah->ah_version == AR5K_AR5212) { 1194 ath5k_hw_reg_write(ah, 1195 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) | 1196 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) | 1197 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET), 1198 AR5K_QOS_NOACK); 1199 } 1200 1201 1202 /* 1203 * Configure PHY 1204 */ 1205 1206 /* Set channel on PHY */ 1207 ret = ath5k_hw_channel(ah, channel); 1208 if (ret) 1209 return ret; 1210 1211 /* 1212 * Enable the PHY and wait until completion 1213 * This includes BaseBand and Synthesizer 1214 * activation. 1215 */ 1216 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1217 1218 /* 1219 * On 5211+ read activation -> rx delay 1220 * and use it. 1221 * 1222 * TODO: Half/quarter rate support 1223 */ 1224 if (ah->ah_version != AR5K_AR5210) { 1225 u32 delay; 1226 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & 1227 AR5K_PHY_RX_DELAY_M; 1228 delay = (channel->hw_value & CHANNEL_CCK) ? 1229 ((delay << 2) / 22) : (delay / 10); 1230 1231 udelay(100 + (2 * delay)); 1232 } else { 1233 mdelay(1); 1234 } 1235 1236 /* 1237 * Perform ADC test to see if baseband is ready 1238 * Set tx hold and check adc test register 1239 */ 1240 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); 1241 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); 1242 for (i = 0; i <= 20; i++) { 1243 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) 1244 break; 1245 udelay(200); 1246 } 1247 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); 1248 1249 /* 1250 * Start automatic gain control calibration 1251 * 1252 * During AGC calibration RX path is re-routed to 1253 * a power detector so we don't receive anything. 1254 * 1255 * This method is used to calibrate some static offsets 1256 * used together with on-the fly I/Q calibration (the 1257 * one performed via ath5k_hw_phy_calibrate), that doesn't 1258 * interrupt rx path. 1259 * 1260 * While rx path is re-routed to the power detector we also 1261 * start a noise floor calibration, to measure the 1262 * card's noise floor (the noise we measure when we are not 1263 * transmiting or receiving anything). 1264 * 1265 * If we are in a noisy environment AGC calibration may time 1266 * out and/or noise floor calibration might timeout. 1267 */ 1268 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1269 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF); 1270 1271 /* At the same time start I/Q calibration for QAM constellation 1272 * -no need for CCK- */ 1273 ah->ah_calibration = false; 1274 if (!(mode == AR5K_MODE_11B)) { 1275 ah->ah_calibration = true; 1276 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1277 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1278 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 1279 AR5K_PHY_IQ_RUN); 1280 } 1281 1282 /* Wait for gain calibration to finish (we check for I/Q calibration 1283 * during ath5k_phy_calibrate) */ 1284 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1285 AR5K_PHY_AGCCTL_CAL, 0, false)) { 1286 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n", 1287 channel->center_freq); 1288 } 1289 1290 /* Restore antenna mode */ 1291 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); 1292 1293 /* Restore slot time and ACK timeouts */ 1294 if (ah->ah_coverage_class > 0) 1295 ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class); 1296 1297 /* 1298 * Configure QCUs/DCUs 1299 */ 1300 1301 /* TODO: HW Compression support for data queues */ 1302 /* TODO: Burst prefetch for data queues */ 1303 1304 /* 1305 * Reset queues and start beacon timers at the end of the reset routine 1306 * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping 1307 * Note: If we want we can assign multiple qcus on one dcu. 1308 */ 1309 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) { 1310 ret = ath5k_hw_reset_tx_queue(ah, i); 1311 if (ret) { 1312 ATH5K_ERR(ah->ah_sc, 1313 "failed to reset TX queue #%d\n", i); 1314 return ret; 1315 } 1316 } 1317 1318 1319 /* 1320 * Configure DMA/Interrupts 1321 */ 1322 1323 /* 1324 * Set Rx/Tx DMA Configuration 1325 * 1326 * Set standard DMA size (128). Note that 1327 * a DMA size of 512 causes rx overruns and tx errors 1328 * on pci-e cards (tested on 5424 but since rx overruns 1329 * also occur on 5416/5418 with madwifi we set 128 1330 * for all PCI-E cards to be safe). 1331 * 1332 * XXX: need to check 5210 for this 1333 * TODO: Check out tx triger level, it's always 64 on dumps but I 1334 * guess we can tweak it and see how it goes ;-) 1335 */ 1336 if (ah->ah_version != AR5K_AR5210) { 1337 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, 1338 AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B); 1339 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG, 1340 AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B); 1341 } 1342 1343 /* Pre-enable interrupts on 5211/5212*/ 1344 if (ah->ah_version != AR5K_AR5210) 1345 ath5k_hw_set_imr(ah, ah->ah_imr); 1346 1347 /* Enable 32KHz clock function for AR5212+ chips 1348 * Set clocks to 32KHz operation and use an 1349 * external 32KHz crystal when sleeping if one 1350 * exists */ 1351 if (ah->ah_version == AR5K_AR5212 && 1352 op_mode != NL80211_IFTYPE_AP) 1353 ath5k_hw_set_sleep_clock(ah, true); 1354 1355 /* 1356 * Disable beacons and reset the TSF 1357 */ 1358 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE); 1359 ath5k_hw_reset_tsf(ah); 1360 return 0; 1361 } 1362