| aqc111.h (361459cd9642631f048719169da9ef14cbf4a932) | aqc111.h (0203146646be831de832e7fd2dc4ef1f32958f51) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0-or-later 2 * Aquantia Corp. Aquantia AQtion USB to 5GbE Controller 3 * Copyright (C) 2003-2005 David Hollis <dhollis@davehollis.com> 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> 5 * Copyright (C) 2002-2003 TiVo Inc. 6 * Copyright (C) 2017-2018 ASIX 7 * Copyright (C) 2018 Aquantia Corp. 8 */ --- 7 unchanged lines hidden (view full) --- 16#define AQ_FLASH_PARAMETERS 0x20 17#define AQ_PHY_POWER 0x31 18#define AQ_PHY_OPS 0x61 19 20#define AQ_USB_PHY_SET_TIMEOUT 10000 21#define AQ_USB_SET_TIMEOUT 4000 22 23/* Feature. ********************************************/ | 1/* SPDX-License-Identifier: GPL-2.0-or-later 2 * Aquantia Corp. Aquantia AQtion USB to 5GbE Controller 3 * Copyright (C) 2003-2005 David Hollis <dhollis@davehollis.com> 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> 5 * Copyright (C) 2002-2003 TiVo Inc. 6 * Copyright (C) 2017-2018 ASIX 7 * Copyright (C) 2018 Aquantia Corp. 8 */ --- 7 unchanged lines hidden (view full) --- 16#define AQ_FLASH_PARAMETERS 0x20 17#define AQ_PHY_POWER 0x31 18#define AQ_PHY_OPS 0x61 19 20#define AQ_USB_PHY_SET_TIMEOUT 10000 21#define AQ_USB_SET_TIMEOUT 4000 22 23/* Feature. ********************************************/ |
| 24#define AQ_SUPPORT_FEATURE (NETIF_F_SG) 25#define AQ_SUPPORT_HW_FEATURE (NETIF_F_SG) | 24#define AQ_SUPPORT_FEATURE (NETIF_F_SG | NETIF_F_IP_CSUM |\ 25 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM) |
| 26 | 26 |
| 27#define AQ_SUPPORT_HW_FEATURE (NETIF_F_SG | NETIF_F_IP_CSUM |\ 28 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM) 29 |
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| 27/* SFR Reg. ********************************************/ 28 29#define SFR_GENERAL_STATUS 0x03 30#define SFR_CHIP_STATUS 0x05 31#define SFR_RX_CTL 0x0B 32 #define SFR_RX_CTL_TXPADCRC 0x0400 33 #define SFR_RX_CTL_IPE 0x0200 34 #define SFR_RX_CTL_DROPCRCERR 0x0100 --- 122 unchanged lines hidden (view full) --- 157 158/* TX Descriptor */ 159#define AQ_TX_DESC_LEN_MASK 0x1FFFFF 160#define AQ_TX_DESC_DROP_PADD BIT(28) 161 162#define AQ_RX_HW_PAD 0x02 163 164/* RX Packet Descriptor */ | 30/* SFR Reg. ********************************************/ 31 32#define SFR_GENERAL_STATUS 0x03 33#define SFR_CHIP_STATUS 0x05 34#define SFR_RX_CTL 0x0B 35 #define SFR_RX_CTL_TXPADCRC 0x0400 36 #define SFR_RX_CTL_IPE 0x0200 37 #define SFR_RX_CTL_DROPCRCERR 0x0100 --- 122 unchanged lines hidden (view full) --- 160 161/* TX Descriptor */ 162#define AQ_TX_DESC_LEN_MASK 0x1FFFFF 163#define AQ_TX_DESC_DROP_PADD BIT(28) 164 165#define AQ_RX_HW_PAD 0x02 166 167/* RX Packet Descriptor */ |
| 168#define AQ_RX_PD_L4_ERR BIT(0) 169#define AQ_RX_PD_L3_ERR BIT(1) 170#define AQ_RX_PD_L4_TYPE_MASK 0x1C 171#define AQ_RX_PD_L4_UDP 0x04 172#define AQ_RX_PD_L4_TCP 0x10 173#define AQ_RX_PD_L3_TYPE_MASK 0x60 174#define AQ_RX_PD_L3_IP 0x20 175#define AQ_RX_PD_L3_IP6 0x40 176 |
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| 165#define AQ_RX_PD_RX_OK BIT(11) 166#define AQ_RX_PD_DROP BIT(31) 167#define AQ_RX_PD_LEN_MASK 0x7FFF0000 168#define AQ_RX_PD_LEN_SHIFT 0x10 169 170/* RX Descriptor header */ 171#define AQ_RX_DH_PKT_CNT_MASK 0x1FFF 172#define AQ_RX_DH_DESC_OFFSET_MASK 0xFFFFE000 --- 17 unchanged lines hidden --- | 177#define AQ_RX_PD_RX_OK BIT(11) 178#define AQ_RX_PD_DROP BIT(31) 179#define AQ_RX_PD_LEN_MASK 0x7FFF0000 180#define AQ_RX_PD_LEN_SHIFT 0x10 181 182/* RX Descriptor header */ 183#define AQ_RX_DH_PKT_CNT_MASK 0x1FFF 184#define AQ_RX_DH_DESC_OFFSET_MASK 0xFFFFE000 --- 17 unchanged lines hidden --- |